A Heterogeneous PN-Structured Gallium Oxide Power Diode and Its Preparation Method

Abstract

The present invention relates to a heterogeneous PN - structured gallium oxide power diode and a preparation method thereof. The method includes: selecting a substrate layer, preparing a drift layer on the upper surface of the substrate layer; preparing a cathode on the lower surface of the substrate layer; etching a plurality of nano - channel structures in the drift layer; preparing an anode on the upper surface of the drift layer; performing a low - temperature annealing process on the device to obtain a gallium oxide power diode; wherein, both the substrate layer and the drift layer are Si - or Sn - doped β - Ga2O3 materials, and the doping concentration of the drift layer is lower than that of the substrate layer, the anode is a Ni / Au metal stack, and a NiO layer with P - type characteristics is formed at the interface between the metal Ni and the drift layer, and the NiO layer and the drift layer form a heterogeneous PN - junction structure. In the preparation method of the present invention, a thin NiO layer with P - type characteristics is formed through low - temperature annealing, which can form a heterogeneous PN - junction structure with β - Ga2O3, reduce the reverse leakage current, and improve the breakdown voltage of the device. The nano - channel structure has a three - dimensional modulation effect, thereby modulating the electric field distribution.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and particularly relates to a heterojunction PN structure gallium oxide power diode and a preparation method thereof. Background Art

[0002] Due to the ultra-wide bandgap width and relatively high breakdown field strength of the β-Ga2O3 crystal material, β-Ga2O3 has the potential to fabricate high-voltage-resistant, high-power, and low-loss power devices and can be applied in the high-voltage and high-power fields. In recent years, many scholars have started to research the β-Ga2O3 crystal material and power devices. However, there is still a large gap between the breakdown field strength of its devices and the theoretical limit. At the same time, the thermionic field emission current (TFE leakage current) is still very large. Summary of the Invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a heterojunction PN structure gallium oxide power diode and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0004] The present invention provides a preparation method of a heterojunction PN structure gallium oxide power diode, including:

[0005] S1: Select a substrate layer, and prepare a drift layer on the upper surface of the substrate layer;

[0006] S2: Prepare a cathode on the lower surface of the substrate layer;

[0007] S3: Etch a plurality of nano-channel structures on the drift layer;

[0008] S4: Prepare an anode on the upper surface of the drift layer;

[0009] S5: Perform a low-temperature annealing process on the device to obtain a gallium oxide power diode;

[0010] Wherein, both the substrate layer and the drift layer are Si- or Sn-doped β-Ga2O3 materials, and the doping concentration of the drift layer is lower than that of the substrate layer. The anode is a Ni / Au metal stack, and a NiO layer with P-type characteristics is formed at the interface between the metal Ni and the drift layer. The NiO layer and the drift layer form a heterojunction PN junction structure.

[0011] In an embodiment of the present invention, the thickness of the drift layer is 2-14 μm, and the doping concentration is 1×10 15 cm -3 -1×10 17 cm -3 .

[0012] In one embodiment of the present invention, S2 includes:

[0013] S21: Depositing a Ti / Au metal stack on the lower surface of the substrate layer;

[0014] S22: Rapidly annealing the device in an N2 atmosphere to form a cathode, wherein the annealing temperature is 400 - 600 °C.

[0015] In one embodiment of the present invention, the etching depth of the nanogroove structure is 100 - 1300 nm, and the width of the nanogroove structure is 100 - 900 nm.

[0016] In one embodiment of the present invention, in S5, the annealing temperature of the low-temperature annealing process is 100 - 500 °C.

[0017] The present invention also provides a heterojunction PN structure gallium oxide power diode, which is characterized by including: a cathode, a substrate layer, a drift layer, and an anode, wherein,

[0018] The cathode, the substrate layer, and the drift layer are stacked in sequence from bottom to top;

[0019] A plurality of nanogroove structures are etched on the upper surface of the drift layer;

[0020] The anode is disposed on the drift layer, as well as the bottom and inner walls of the rice groove structure;

[0021] The anode is a Ni / Au metal stack, and a NiO layer with P-type characteristics is formed at the interface between the metal Ni and the drift layer, and the NiO layer and the drift layer form a heterojunction PN junction structure.

[0022] In one embodiment of the present invention, both the substrate layer and the drift layer are Si- or Sn-doped β-Ga2O3 materials, and the doping concentration of the drift layer is lower than that of the substrate layer.

[0023] In one embodiment of the present invention, the doping concentration of the drift layer is 1×10 15 cm -3 -1×10 17 cm -3 , and the thickness is 2 - 14 μm.

[0024] In one embodiment of the present invention, the etching depth of the nanogroove structure is 100 - 1300 nm, and the width of the nanogroove structure is 100 - 900 nm.

[0025] In one embodiment of the present invention, the cathode is a Ti / Au metal stack.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0027] 1. In the method for preparing a gallium oxide power diode with a heterojunction PN structure of the present invention, through low-temperature annealing, the anode metal Ni reacts with oxygen in the β-Ga2O3 drift layer to form a NiO layer with P-type characteristics and a thickness of 1-5 nm. The NiO layer can form a heterojunction PN structure with the β-Ga2O3 drift layer. The heterojunction PN structure can reduce the concentration of carbon compounds on the surface of gallium oxide, improve the interface characteristics between the anode metal and gallium oxide, thereby reducing the reverse leakage current and increasing the breakdown voltage of the device. At the same time, the set nano-channel structure has a three-dimensional modulation effect, thus modulating the electric field distribution;

[0028] 2. In the method for preparing a gallium oxide power diode with a heterojunction PN structure of the present invention, there is no need to deposit P-type materials, and the heterojunction PN structure is achieved only through annealing. The technical method is simple and easy to implement;

[0029] 3. In the method for preparing a gallium oxide power diode with a heterojunction PN structure of the present invention, the NiO layer with P-type characteristics formed by low-temperature annealing is relatively thin, overcoming the defect that other devices cannot deposit and grow a relatively thin NiO layer, and avoiding the problem of an increase in the on-resistance of the device caused by introducing a relatively thick NiO layer.

[0030] The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the content of the specification. In order to make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the accompanying drawings. Description of the Drawings

[0031] Figure 1 is a flowchart of a method for preparing a gallium oxide power diode with a heterojunction PN structure provided by an embodiment of the present invention;

[0032] Figures 2a - 2e is a process flowchart for preparing a gallium oxide power diode with a heterojunction PN structure provided by an embodiment of the present invention;

[0033] Figure 3 is a schematic structural diagram of a gallium oxide power diode with a heterojunction PN structure provided by an embodiment of the present invention. Detailed Embodiments

[0034] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following provides a detailed description of a gallium oxide power diode with a heterojunction PN structure and a method for preparing the same according to the present invention in conjunction with the accompanying drawings and specific embodiments.

[0035] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the predetermined purpose can be obtained. However, the accompanying drawings are only for reference and illustration, and are not used to limit the technical solution of the present invention.

[0036] Example 1

[0037] Please refer to Figure 1 , Figure 1 which is a flowchart of a method for fabricating a heterojunction PN structure gallium oxide power diode provided by an embodiment of the present invention. As shown in the figure, the method for fabricating a heterojunction PN structure gallium oxide power diode in this embodiment includes:

[0038] S1: Select a substrate layer and fabricate a drift layer on the upper surface of the substrate layer;

[0039] In this embodiment, optionally, Si- or Sn-heavily doped β-Ga2O3 is selected as the substrate layer, and a layer of Si- or Sn-lightly doped β-Ga2O3 is grown above the Si- or Sn-heavily doped β-Ga2O3 substrate by using the HVPE (Hydride Vapor Phase Epitaxy) process as the drift layer.

[0040] In this embodiment, the doping concentration of the drift layer is lower than that of the substrate layer.

[0041] Optionally, the doping concentration of the substrate layer is 5×10 18 cm -3 -5×10 19 cm -3 .

[0042] Optionally, the thickness of the drift layer is 2 - 14 μm, and the doping concentration is 1×10 15 cm -3 -1×10 17 cm -3 .

[0043] S2: Fabricate a cathode on the lower surface of the substrate layer;

[0044] Specifically, it includes:

[0045] S21: Deposit a Ti / Au metal stack on the lower surface of the substrate layer;

[0046] S22: Perform rapid annealing treatment on the device in an N2 atmosphere to form a cathode, where the annealing temperature is 400 - 600 °C.

[0047] In this embodiment, optionally, the thicknesses of the Ti / Au metal stack are 20 / 200 nm respectively.

[0048] S3: Etch a plurality of nano-channel structures in the drift layer;

[0049] Specifically, an ICP plasma etcher is used to selectively etch the drift layer to form a plurality of nano-channel structures.

[0050] In this embodiment, the etching depth of the nano-channel structures is 100 - 1300 nm, and the width of the nano-channel structures is 100 - 900 nm.

[0051] S4: Fabricate an anode on the upper surface of the drift layer;

[0052] Specifically, deposit a Ni / Au metal stack on the upper surface of the drift layer as the anode.

[0053] In this embodiment, the anode metal is deposited on the drift layer, as well as the bottom and inner walls of the nano-channel structures. Optionally, the thicknesses of the Ni / Au metal stack are 45 / 400 nm respectively.

[0054] S5: Perform a low-temperature annealing process on the device to obtain a gallium oxide power diode;

[0055] Specifically, place the device in an annealing furnace for a low-temperature annealing process, where the annealing temperature is 100 - 500 °C.

[0056] In this embodiment, when the device is placed in an annealing furnace for a low-temperature annealing process, at this time, the metal Ni in the Ni / Au metal stack and the oxygen in the β-Ga2O3 drift layer form a NiO layer with P-type characteristics at high temperature, with a thickness of 1 - 5 nm. This NiO layer can form a heterojunction PN junction structure with the β-Ga2O3 drift layer. The heterojunction PN junction structure can reduce the concentration of carbon compounds on the surface of gallium oxide, improve the interface characteristics between the anode metal and gallium oxide, thereby reducing the reverse leakage current and increasing the breakdown voltage of the device. At the same time, the set nano-channel structures have a three-dimensional modulation effect, thus modulating the electric field distribution.

[0057] The method for fabricating a gallium oxide power diode with a heterojunction PN structure in this embodiment does not require depositing P-type materials. Only through annealing, a heterojunction PN junction structure is achieved. The technical method is simple and easy to implement. Moreover, the NiO layer with P-type characteristics formed by low-temperature annealing is relatively thin, overcoming the defect that other devices cannot deposit and grow a relatively thin NiO layer, and avoiding the problem of increasing the on-resistance of the device due to the introduction of a relatively thick NiO layer.

[0058] Embodiment Two

[0059] Please refer to Figures 2a - 2e ,Figures 2a - 2e It is a process flow chart for fabricating a heterojunction PN - structured gallium oxide power diode provided by an embodiment of the present invention; this embodiment specifically describes the fabrication method of the heterojunction PN - structured gallium oxide power diode in Embodiment 1.

[0060] 1. Fabricate a gallium oxide power diode with a drift layer thickness of 2 μm

[0061] Step 1. Select a substrate layer and fabricate a drift layer on the upper surface of the substrate layer.

[0062] Select Si - heavily - doped β - Ga2O3 as the substrate layer, with a doping concentration of 5×10 18 cm -3 , above the Si - heavily - doped β - Ga2O3, use the HVPE process to epitaxially grow a layer of Si - lightly - doped β - Ga2O3 as the drift layer, where the thickness of the drift layer is 2 μm and the doping concentration of the drift layer is 1×10 15 cm -3 , as shown in Figure 2a Figure.

[0063] Step 2. Fabricate the cathode electrode.

[0064] 2.1) Below the substrate layer, sputter the cathode metal through a Sputter device. The metals are Ti / Au in sequence, with thicknesses of 20 / 200 nm respectively;

[0065] 2.2) Then use an annealing furnace to perform rapid thermal annealing for 30 s in an N2 atmosphere at 400 °C to alloy the cathode metal and complete the fabrication of the cathode electrode, as shown in Figure 2b Figure.

[0066] Step 3. Fabricate the nanogroove structure.

[0067] Use an ICP plasma etching machine to etch the lightly - doped β - Ga2O3 drift layer to form a nanogroove structure. Among them, the etching depth of the nanogroove structure is 100 nm and the width of the nanogroove structure is 100 nm, as shown in Figure 2c Figure.

[0068] Step 4. Deposit the anode metal and form NiO.

[0069] 4.1) Above the nanogroove structure, use an electron beam evaporation platform to fabricate the anode electrode. The metals are Ni / Au in sequence, with thicknesses of 45 / 400 nm respectively. After the metal evaporation is completed, perform metal lift - off to form the anode electrode, as shown in Figure 2d Figure, where the anode metal is deposited on the drift layer, as well as the bottom and inner walls of the nanogroove structure;

[0070] 4.2) Place the device in an annealing furnace and perform thermal annealing for 10 min in an N2 atmosphere at 100 °C. At this time, the metal Ni in the Ni / Au metal stack and the oxygen in the β-Ga2O3 drift layer form a thin NiO layer with P-type characteristics at high temperature, obtaining a gallium oxide power diode with a high breakdown voltage, as Figure 2e shown.

[0071] 2. Fabricate a gallium oxide power diode with a drift layer thickness of 8 μm

[0072] Step 1. Select a substrate layer and fabricate a drift layer on the upper surface of the substrate layer.

[0073] Select Si-heavily doped β-Ga2O3 as the substrate layer. Above the Si-heavily doped β-Ga2O3, use the HVPE process to epitaxially grow a layer of Si-lightly doped β-Ga2O3 layer as the drift layer, where the thickness of the drift layer is 8 μm and the doping concentration of the drift layer is 1×10 16 cm -3 , as Figure 2a shown.

[0074] Step 2. Fabricate the cathode electrode.

[0075] 2.1) Below the substrate layer, sputter the cathode metal through a Sputter device. The metals are Ti / Au in sequence, with thicknesses of 20 / 200 nm respectively;

[0076] 2.2) Then use an annealing furnace to perform rapid thermal annealing for 30 s in an N2 atmosphere at 500 °C to alloy the cathode metal and complete the fabrication of the cathode electrode, as Figure 2b shown.

[0077] Step 3. Fabricate the nanogroove structure.

[0078] Use an ICP plasma etching machine to etch the lightly doped β-Ga2O3 drift layer to form a nanogroove structure. Among them, the etching depth of the nanogroove structure is 700 nm and the width of the nanogroove structure is 500 nm, as Figure 2c shown.

[0079] Step 4. Deposit the anode metal and form NiO.

[0080] 4.1) Above the nanogroove structure, use an electron beam evaporation platform to fabricate the anode electrode. The metals are Ni / Au in sequence, with thicknesses of 45 / 400 nm respectively. After the metal evaporation is completed, perform metal lift-off to form the anode electrode, as Figure 2d shown, where the anode metal is deposited on the drift layer, as well as the bottom and inner walls of the nanogroove structure;

[0081] 4.2) Place the device in an annealing furnace and perform thermal annealing for 10 min in an N2 atmosphere at 300 °C. At this time, the metal Ni in the Ni / Au metal stack and the oxygen in the β-Ga2O3 drift layer form a thin NiO layer with P-type characteristics at high temperature, obtaining a gallium oxide power diode with a high breakdown voltage, as Figure 2e shown.

[0082] 3. Fabricate a gallium oxide power diode with a drift layer thickness of 14 μm

[0083] Step 1. Select a substrate layer and fabricate a drift layer on the upper surface of the substrate layer.

[0084] Select Si-heavily doped β-Ga2O3 as the substrate layer. Above the Si-heavily doped β-Ga2O3, use the HVPE process to epitaxially grow a layer of Si-lightly doped β-Ga2O3 layer as the drift layer, where the drift layer thickness is 14 μm and the doping concentration of the drift layer is 1×10 17 cm -3 , as Figure 2a shown.

[0085] Step 2. Fabricate the cathode electrode.

[0086] 2.1) Sputter the cathode metal below the substrate layer through a Sputter device. The metals are Ti / Au in sequence, with thicknesses of 20 / 200 nm respectively;

[0087] 2.2) Then use an annealing furnace to perform rapid thermal annealing for 30 s in an N2 atmosphere at 600 °C to alloy the cathode metal and complete the fabrication of the cathode electrode, as Figure 2b shown.

[0088] Step 3. Fabricate the nanochannel structure.

[0089] Use an ICP plasma etcher to etch the lightly doped β-Ga2O3 drift layer to form a nanochannel structure. Among them, the etching depth of the nanochannel structure is 1300 nm, and the width of the nanochannel structure is 900 nm, as Figure 2c shown.

[0090] Step 4. Deposit the anode metal and form NiO.

[0091] 4.1) Fabricate the anode electrode above the nanochannel structure using an electron beam evaporation platform. The metals are Ni / Au in sequence, with thicknesses of 45 / 400 nm respectively. After the metal evaporation is completed, perform metal lift-off to form the anode electrode, as Figure 2d shown, where the anode metal is deposited on the drift layer, as well as the bottom and inner walls of the nanochannel structure;

[0092] 4.2) Place the device in an annealing furnace and perform thermal annealing for 10 min in an N2 atmosphere at 500 °C. At this time, the metal Ni in the Ni / Au metal stack and the oxygen in the β-Ga2O3 drift layer form a thin NiO layer with P-type characteristics at high temperature, obtaining a gallium oxide power diode with a high breakdown voltage, as Figure 2e shown.

[0093] Example 3

[0094] This embodiment provides a gallium oxide power diode with a heterojunction PN structure. Please refer to Figure 3 , Figure 3 is a schematic structural diagram of a gallium oxide power diode with a heterojunction PN structure provided by an embodiment of the present invention. As shown in the figure, the PN structure gallium oxide power diode of this embodiment includes: a cathode 1, a substrate layer 2, a drift layer 3, and an anode 4. Among them, the cathode 1, the substrate layer 2, and the drift layer 3 are stacked in sequence from bottom to top; a plurality of nano-channel structures 301 are etched on the upper surface of the drift layer 3; the anode 4 is disposed on the drift layer 3, as well as at the bottom and inner walls of the nano-channel structures 301; the anode 4 is a Ni / Au metal stack, and a NiO layer 5 with P-type characteristics is formed at the interface between the metal Ni and the drift layer 3, and the NiO layer 5 and the drift layer 3 form a heterojunction PN junction structure.

[0095] In this embodiment, both the substrate layer 2 and the drift layer 3 are Si- or Sn-doped β-Ga2O3 materials, and the doping concentration of the drift layer 3 is lower than that of the substrate layer 2.

[0096] Optionally, the doping concentration of the drift layer 3 is 1×10 15 cm -3 -1×10 17 cm -3 , and the thickness is 2 - 14 μm.

[0097] In this embodiment, the cathode 1 is a Ti / Au metal stack. Optionally, the thickness of the Ti / Au metal stack is 20 / 200 nm. Optionally, the thickness of the Ni / Au metal stack is 45 / 400 nm.

[0098] In this embodiment, the etching depth of the nano-channel structures 301 is 100 - 1300 nm, and the width of the nano-channel structures 301 is 100 - 900 nm.

[0099] It should be noted that in this embodiment, when fabricating the heterojunction PN structure gallium oxide power diode, the anode metal Ni reacts with oxygen in the β-Ga2O3 drift layer through a low-temperature annealing process to form a NiO layer with P-type characteristics. This NiO layer can form a heterojunction PN structure with the β-Ga2O3 drift layer. The heterojunction PN structure can reduce the concentration of carbon compounds on the surface of gallium oxide, improve the interface characteristics between the anode metal and gallium oxide, thereby reducing the reverse leakage current and increasing the breakdown voltage of the device. At the same time, the set nano-channel structure has a three-dimensional modulation effect, thus modulating the electric field distribution.

[0100] In addition, since the NiO layer with P-type characteristics formed by low-temperature annealing is relatively thin, the problem of increased on-resistance of the device caused by introducing a thicker NiO layer is avoided.

[0101] It should be noted that in this article, the terms "including", "comprising" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements but also other elements not explicitly listed. Without further limitations, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the article or device including the said element. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on the present invention.

[0102] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A preparation method of a heterogeneous PN structure gallium oxide power diode, characterized in that, Including: S1: Select a substrate layer, and fabricate a drift layer on the upper surface of the substrate layer; S2: Fabricate a cathode on the lower surface of the substrate layer; S3: Etch a plurality of nano-channel structures in the drift layer; S4: Fabricate an anode on the upper surface of the drift layer; S5: Perform a low-temperature annealing process on the device to obtain a gallium oxide power diode; Wherein, both the substrate layer and the drift layer are Si- or Sn-doped β-Ga2O3 materials, and the doping concentration of the drift layer is lower than that of the substrate layer. The anode is a Ni / Au metal stack, and a NiO layer with P-type characteristics is formed at the interface between the metal Ni and the drift layer. The NiO layer and the drift layer form a heterojunction PN junction structure; Forming a NiO layer with P-type characteristics at the interface between the metal Ni and the drift layer includes: Using the metal Ni in the Ni / Au metal stack and the oxygen in the β-Ga2O3 drift layer to form the NiO layer with P-type characteristics at high temperature.

2. The manufacturing method of the heterogeneous PN structure gallium oxide power diode according to claim 1, characterized in that, The thickness of the drift layer is 2 - 14 μm, and the doping concentration is 1×10 15 cm -3 -1×10 17 cm -3 .

3. The manufacturing method of the gallium oxide power diode with a heterogeneous PN structure according to claim 1, characterized in that, The S2 includes: S21: Deposit a Ti / Au metal stack on the lower surface of the substrate layer; S22: Perform a rapid annealing process on the device in an N2 atmosphere to form a cathode, where the annealing temperature is 400 - 600 °C.

4. The manufacturing method of the heterogeneous PN structure gallium oxide power diode according to claim 1, characterized in that, The etching depth of the nano-channel structure is 100 - 1300 nm, and the width of the nano-channel structure is 100 - 900 nm.

5. The preparation method of the heterogeneous PN structure gallium oxide power diode according to claim 1, characterized in that, In the S5, the annealing temperature of the low-temperature annealing process is 100 - 500 °C.

6. A heterojunction PN - structured gallium oxide power diode, characterized in that, Including: Cathode (1), substrate layer (2), drift layer (3) and anode (4), wherein, The cathode (1), the substrate layer (2) and the drift layer (3) are stacked in sequence from bottom to top; A plurality of nano-channel structures (301) are etched on the upper surface of the drift layer (3); The anode (4) is disposed on the drift layer (3), as well as the bottom and inner walls of the rice-channel structure (301); The anode (4) is a Ni / Au metal stack, and a NiO layer (5) with P-type characteristics is formed at the interface between the metal Ni and the drift layer (3). The NiO layer (5) and the drift layer (3) form a heterojunction PN junction structure. Forming a NiO layer (5) with P-type characteristics at the interface between the metal Ni and the drift layer (3) includes using the metal Ni in the Ni / Au metal stack and the oxygen in the β-Ga2O3 drift layer to form the NiO layer (5) with P-type characteristics at high temperature.

7. The gallium oxide power diode with a heterogeneous PN structure according to claim 6, wherein Both the substrate layer (2) and the drift layer (3) are Si- or Sn-doped β-Ga2O3 materials, and the doping concentration of the drift layer (3) is lower than that of the substrate layer (2).

8. The gallium oxide power diode with a heterogeneous PN structure according to claim 7, wherein, The doping concentration of the drift layer (3) is 1×10 15 cm -3 -1×10 17 cm -3 , and the thickness is 2 - 14 μm.

9. The gallium oxide power diode with a heterogeneous PN structure according to claim 6, characterized in that, The etching depth of the nano-channel structure (301) is 100 - 1300 nm, and the width of the nano-channel structure (301) is 100 - 900 nm.

10. The gallium oxide power diode with a heterogeneous PN structure according to claim 6, characterized in that, The cathode (1) is a Ti / Au metal stack.

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