Three-dimensional memory device and method of manufacturing the same

Abstract

The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, wherein the three-dimensional memory device includes: an electrode structure, which includes a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a substrate; a first step structure and a second step structure, which are defined in the electrode structure and are located at different heights from each other; a sidewall of the electrode structure formed due to a height difference between the first step structure and the second step structure; and a dielectric support member, which passes through the electrode structure and isolates a corner of the sidewall from the plurality of electrode layers.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor technology, and more particularly, to a three-dimensional memory device and a method of manufacturing the same. Background Art

[0002] In order to meet the excellent performance and low price required by consumers, it is necessary to improve the integration of memory devices. The integration of two-dimensional or planar memory devices is mainly determined by the area occupied by the unit memory cell, so the integration is greatly affected by the level of fine pattern forming technology. However, because it takes quite expensive equipment to form fine patterns, although the integration of two-dimensional memory devices is increasing, it is still limited. As an alternative to overcome this limitation, a three-dimensional memory device including a three-dimensionally arranged memory cell has been proposed. In a three-dimensional memory device, the integration can be improved by increasing the number of stacked electrode layers connected to the memory cell. Summary of the invention

[0003] Various embodiments are directed to measures that can help reduce failures in three-dimensional memory devices.

[0004] In one embodiment, a three-dimensional memory device may include: an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a substrate; a first step structure and a second step structure defined in the electrode structure and located at different heights from each other; a sidewall of the electrode structure between the first step structure and the second step structure; and a dielectric support member passing through the electrode structure and isolating a corner of the sidewall from the plurality of electrode layers.

[0005] In one embodiment, a method for manufacturing a three-dimensional memory device may include the following steps: forming a pre-stack by alternately stacking a plurality of interlayer dielectric layers and a plurality of sacrificial layers on a substrate; forming a dielectric support member passing through the pre-stack; forming a first stepped structure on top of the pre-stack in a thinned region; forming a second stepped structure by transferring a portion of the first stepped structure downward by etching the pre-stack; and replacing the sacrificial layer with an electrode layer. In the step of forming the second stepped structure, a corner of a sidewall formed in the pre-stack by etching may be isolated from the plurality of sacrificial layers by the dielectric support member.

[0006] In one embodiment, a method for manufacturing a three-dimensional memory device may include the following steps: forming a pre-stack by alternately stacking a plurality of interlayer dielectric layers and a plurality of sacrificial layers on a substrate; forming a first stepped structure on top of the pre-stack; forming a second stepped structure by transferring a portion of the first stepped structure downward by etching the pre-stack; forming a vertical hole passing through the pre-stack at a corner periphery of a sidewall formed in the pre-stack in the step of forming the second stepped structure; forming a plurality of horizontal grooves by removing a plurality of sacrificial layers formed at the corners through the vertical holes; forming a dielectric support in the vertical holes and the plurality of horizontal grooves; and replacing the sacrificial layers with electrode layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram showing a representation of a three-dimensional memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It is shown Figure 1 An equivalent circuit diagram of a representation of a memory block is shown.

[0009] Figure 3A and Figure 3B is a cross-sectional view showing a representation of a schematic layout of a three-dimensional memory device according to an embodiment of the present disclosure.

[0010] Figure 4 is a top view showing a representation of an electrode structure of a three-dimensional memory device according to an embodiment of the present disclosure, and Figure 5 It is shown Figure 4 A stereogram showing a portion of a .

[0011] 6A to 9A is a representation of a top view that helps explain the steps of fabricating a three-dimensional memory device according to an embodiment of the present disclosure.

[0012] FIG. 6B to FIG. 9B is a representation of a perspective view that helps explain the steps of fabricating a three-dimensional memory device according to an embodiment of the present disclosure.

[0013] Fig.10 is a top view showing a representation of a dielectric support according to another embodiment of the present disclosure.

[0014] Fig.11 is a top view showing a representation of a dielectric support according to yet another embodiment of the present disclosure.

[0015] Fig.12 It is along Fig.11 A cross-sectional view taken along line II'.

[0016] FIG. 13A to FIG. 13C It helps explain the formation Fig.11 and Fig.12A representation of a cross-sectional view of the method of the dielectric support is shown.

[0017] Fig.14 is a top view showing a representation of an example of a dielectric support according to yet another embodiment of the present disclosure.

[0018] Fig.15 It is shown Fig.14 A stereogram of a portion of.

[0019] FIG. 16A to FIG. 21B is to help explain manufacturing including Fig.14 and Fig.15 A representation of a method of a three-dimensional memory device with a dielectric support is shown.

[0020] Fig. 22 is a block diagram schematically illustrating a representation of a memory system including a memory device according to an embodiment of the present disclosure.

[0021] Fig.23 is a block diagram schematically illustrating a representation of a computing system including a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The advantages and features of the present disclosure and methods for implementing the same will become apparent from the description of the exemplary embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0023] Because the numerical values, dimensions, ratios, angles, and number of elements describing the embodiments of the present disclosure given in the drawings are only illustrative, the present disclosure is not limited to the contents shown. Throughout the specification, the same reference numerals represent the same components. When describing the present disclosure, when it is determined that the detailed description of the related art may obscure the main points or clarity of the present disclosure, its detailed description will be omitted. It should be understood that the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the means listed thereafter, unless otherwise specifically stated. In the case of using an indefinite article or a definite article (e.g., "one", "an" or "the") when referring to a singular noun, the article may include the plural noun, unless otherwise specifically stated. When explaining the components in the embodiments of the present disclosure, even if there is no clear description, it should be interpreted as including error tolerance.

[0024] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a) and (b) may be used. These terms are only used to distinguish one component from another component, and do not limit the material, order, sequence or quantity of the components. In addition, the components in the embodiments of the present disclosure are limited by these terms. These terms are only used to distinguish one component from another component. Therefore, as used herein, within the technical spirit of the present disclosure, a first component may be a second component.

[0025] If a component is described as being "connected," "coupled," or "linked" to another component, it should be understood that the component may be directly "connected," "coupled," or "linked" to the other component, but another component may be "interposed" therebetween, or the component may be "connected," "coupled," or "linked" to the other component via another component. When describing a positional relationship, such as "element A on element B," "element A above element B," "element A below element B," and "element A next to element B," one or more other elements may be disposed between element A and element B, unless the term "directly" or "just" is explicitly used.

[0026] The features of the various exemplary embodiments of the present disclosure may be coupled, combined, or separated in part or in whole. Various technical interactions and operations may be performed. The various exemplary embodiments may be implemented individually or in combination.

[0027] Figure 1 is a block diagram showing a representation of a three-dimensional memory device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 , a memory device 100 according to an embodiment of the present disclosure may include a memory cell array 110 , a row decoder 120 , a page buffer circuit 130 , and a peripheral circuit 140 .

[0029] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKn. Although not shown, each of the memory blocks BLK1 to BLKn may include a plurality of memory cells. The memory cells may be accessed through word lines and bit lines. The memory cells may be volatile memory cells that lose the data stored therein when the power is interrupted, or may be non-volatile memory cells that retain the data stored therein even if the power is interrupted. Although the memory device 100 is described below as a vertical NAND flash memory device, it should be noted that the technical spirit of the present disclosure is not limited thereto.

[0030] The row decoder 120 may be coupled to the memory cell array 110 via a row line RL. The row line RL may include at least one drain selection line, a plurality of word lines, and at least one source selection line. The row decoder 120 may select a memory block from the memory blocks BLK1 to BLKn of the memory cell array 110 according to the address information. The row decoder 120 may transmit an operation voltage X_V (e.g., a programming voltage, a pass voltage, and a read voltage) from the peripheral circuit 140 to the row line RL coupled to the selected memory block. In order to transmit the operation voltage X_V, the row decoder 120 may include a plurality of transmission transistors coupled to the row lines RL, respectively.

[0031] The page buffer circuit 130 may be coupled to the memory cell array 110 through the bit lines BL. The page buffer circuit 130 may include a plurality of page buffers PB respectively coupled to the bit lines BL. The page buffer circuit 130 may receive a page buffer control signal PB_C from the peripheral circuit 140, and may transmit and receive a data signal DATA to and from the peripheral circuit 140.

[0032] The page buffer circuit 130 may control the bit line BL coupled to the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 130 may detect data stored in the memory cell of the memory cell array 110 by sensing the signal of the bit line BL of the memory cell array 110 in response to the page buffer control signal PB_C, and may transmit the data signal DATA to the peripheral circuit 140 according to the detected data. The page buffer circuit 130 may apply a signal to the bit line BL based on the data signal DATA received from the peripheral circuit 140 in response to the page buffer control signal PB_C, and may thereby write data into the memory cell of the memory cell array 110. The page buffer circuit 130 may write data into or read data from the memory cell coupled to the word line activated by the row decoder 120.

[0033] The peripheral circuit 140 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the memory device 100, and may send data DATA to a device (e.g., a memory controller) outside the memory device 100 and receive data DATA from a device outside the memory device 100. The peripheral circuit 140 may output signals (e.g., a row address X_A and a page buffer control signal PB_C, etc.) for writing data DATA to the memory cell array 110 or reading data DATA from the memory cell array 110 based on the command signal CMD, the address signal ADD, and the control signal CTRL. The peripheral circuit 140 may generate various voltages including an operating voltage X_V required in the memory device 100.

[0034] Hereinafter, in the accompanying drawings, a direction protruding vertically from the top surface of the substrate is defined as a vertical direction VD, and two directions parallel to the top surface of the substrate and intersecting each other are defined as a first direction FD and a second direction SD, respectively. For example, the first direction FD may correspond to the extension direction of the word line and the arrangement direction of the bit line, and the second direction SD may correspond to the extension direction of the bit line and the arrangement direction of the word line. The first direction FD and the second direction SD may substantially intersect each other perpendicularly. The first direction FD and the second direction SD may be orthogonal to the vertical direction VD. In the accompanying drawings, the direction indicated by the arrow and the direction opposite thereto represent the same direction.

[0035] Figure 2 It is shown Figure 1 An equivalent circuit diagram of a representation of a memory block is shown.

[0036] Reference Figure 2 , the memory block BLKi may include a plurality of cell strings CSTR connected between a plurality of bit lines BL and a common source line CSL. The bit lines BL may extend in the second direction SD and may be arranged in the first direction FD. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to a common source line CSL. A plurality of cell strings CSTR may be connected between the plurality of bit lines BL and the one common source line CSL.

[0037] Each cell string CSTR may include a drain select transistor DST coupled to a bit line BL, a source select transistor SST coupled to a common source line CSL, and a plurality of memory cells MC coupled between the drain select transistor DST and the source select transistor SST. The drain select transistor DST, the memory cells MC, and the source select transistor SST may be coupled in series in a vertical direction VD.

[0038] The drain selection line DSL, the plurality of word lines WL, and the source selection line SSL may be stacked between the bit line BL and the common source line CSL in the vertical direction VD. Each drain selection line DSL may be connected to the gate of the corresponding drain selection transistor DST. Each word line WL may be connected to the gate of the corresponding memory cell MC. The source selection line SSL may be connected to the gate of the source selection transistor SST.

[0039] The memory cells MC included in the memory block BLKi may be divided into physical page units or logical page units. For example, memory cells MC that share one word line WL and are connected to different cell strings CSTR may configure one physical page. Such a page may be a basic unit of a read operation.

[0040] Figure 3A and Figure 3B is a cross-sectional view showing a representation of a schematic layout of a three-dimensional memory device according to an embodiment of the present disclosure.

[0041] Reference Figure 3A According to an embodiment of the present disclosure, a three-dimensional memory device 100 may include a first substrate 1, a logic structure 2 disposed on the first substrate 1, a second substrate 3 disposed on the logic structure 2, and a memory structure 4 disposed on the second substrate 3. The logic structure 2 may include Figure 1 The row decoder 120, the page buffer circuit 130 and the peripheral circuit 140, and the memory structure 4 may include Figure 1 A memory cell array 110 is provided. Figure 3A The memory device 100 may have a peri under cell (PUC) structure.

[0042] Reference Figure 3B , a three-dimensional memory device 100 according to an embodiment of the present disclosure may include a cell wafer CW and a peripheral wafer PW bonded to the cell wafer CW. The peripheral wafer PW may include a first substrate 1 and a logic structure 2 disposed on the first substrate 1. The cell wafer CW may include a second substrate 3 and a memory structure 4 disposed on the second substrate 3.

[0043] The memory structure 4 may include Figure 1 The memory cell array 110, and the logic structure 2 may include Figure 1 The peripheral wafer PW includes a row decoder 120, a page buffer circuit 130, and a peripheral circuit 140. After the peripheral wafer PW is turned upside down so that the logic structure 2 faces the memory structure 4, the peripheral wafer PW can be bonded to the cell wafer CW. Figure 3B The memory device 100 may have a peri over cell (POC) structure.

[0044] Figure 4 is a top view showing a representation of an electrode structure of a three-dimensional memory device according to an embodiment of the present disclosure, and Figure 5 It is shown Figure 4 A stereogram showing a portion of a .

[0045] Reference Figure 4 and Figure 5, the memory structure 4 or the substrate 3 may include a first cell region CR1, a slimming region SR extending from the first cell region CR1 in a first direction FD, and a second cell region CR2 extending from the slimming region SR in the first direction FD. The slimming region SR may include a first region SR1 and a second region SR2 arranged in a row in the first direction FD. Although the present embodiment shows the slimming region SR having two regions, it should be noted that the slimming region SR may be configured as a single region, or may include at least three regions arranged in a row in the first direction FD.

[0046] The substrate 3 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and compounds thereof. The substrate 3 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG).

[0047] The memory structure 4 may include an electrode structure ES disposed on the substrate 3. The electrode structure ES may extend in the first direction FD and may traverse the first cell region CR1, the thinning region SR, and the second cell region CR2. The electrode structure ES may configure the memory block ( Figure 1 Although not shown, a plurality of electrode structures may be arranged in the second direction SD, and thereby a memory cell array ( Figure 1 of 110).

[0048] The electrode structure ES may include a plurality of electrode layers 10 a to 10 c , 20 a to 20 c , and 30 a to 30 c and a plurality of interlayer dielectric layers 40 alternately stacked on the substrate 3 in the vertical direction VD.

[0049] The electrode layers 10a to 10c, 20a to 20c, and 30a to 30c may include a conductive material. For example, the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c may include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). Among the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c, at least one electrode layer from the bottom electrode layer may configure a source selection line. Among the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c, at least one electrode layer from the top electrode layer may configure a drain selection line. The electrode layer between the source selection line and the drain selection line may configure a word line. The interlayer dielectric layer 40 may be formed of an oxide (e.g., silicon oxide).

[0050] A plurality of vertical channels CH passing through the plurality of electrode layers 10 a to 10 c , 20 a to 20 c , and 30 a to 30 c and the plurality of interlayer dielectric layers 40 in the vertical direction VD may be defined in the first and second cell regions CR1 and CR2 .

[0051] Each vertical channel CH may include a channel layer and a gate dielectric layer. The channel layer may include polycrystalline silicon or monocrystalline silicon, and may include p-type impurities such as boron (B) in some regions thereof. The channel layer may have the shape of a pillar that is completely filled up to its center, or the shape of a solid cylinder. Although not shown, the channel layer may have the shape of a tube with an opening in the central region. In this example, a buried dielectric layer may be formed in the open central region of the channel layer. The gate dielectric layer may have the shape of a straw or a cylindrical shell surrounding the outer wall of the channel layer. Although not shown, the gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a blocking layer sequentially stacked from the outer wall of the channel layer. The gate dielectric layer may have an oxide-nitride-oxide (ONO) stacked structure, in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

[0052] The electrode structure ES may include a lower stack 10 , an intermediate stack 20 stacked on the lower stack 10 , and an upper stack 30 stacked on the intermediate stack 20 .

[0053] The upper stack 30 may include a plurality of upper electrode layers 30a to 30c alternately stacked with the interlayer dielectric layer 40 in the vertical direction VD. The number of upper electrode layers configuring the upper stack 30 may be k (where k is a natural number of two (2) or greater). The present embodiment shows an upper stack 30 having three upper electrode layers 30a to 30c.

[0054] In the first region SR1, a portion of each of the upper electrode layers 30a to 30c may be exposed. In the first region SR1, each of the upper electrode layers 30a to 30c may have a first upper pad region UP1 exposed by the upper electrode layer located thereon. The first upper pad regions UP1 of the upper electrode layers 30a to 30c may be arranged in a stepwise manner in the first direction FD. A first stairway structure ST1 may be formed in the upper stack 30 by the first upper pad regions UP1 of the upper electrode layers 30a to 30c. The first stairway structure ST1 may have a first inclination angle θ1 relative to the top surface of the substrate 3. The present embodiment shows a first stairway structure ST1 having a stairway shape that gradually rises from a central portion of the first stairway structure ST1 to both sides of the first stairway structure ST1 in the first direction FD.

[0055] In the first region SR1, the upper laminate 30 may expose a portion of each of the intermediate laminates 20. In the first region SR1, the upper intermediate laminate 20 may expose a portion of the lower intermediate laminate 20 located below the upper intermediate laminate 20.

[0056] Each intermediate stack 20 may include a plurality of intermediate electrode layers 20a to 20c alternately stacked with the interlayer dielectric layer 40 in the vertical direction VD. The number of intermediate electrode layers configuring each intermediate stack 20 may be m (where m is a natural number of 2 or greater). This embodiment shows each intermediate stack 20 having three intermediate electrode layers 20a to 20c.

[0057] In the first region SR1, a portion of the intermediate electrode layers 20a to 20c of each intermediate laminate 20 may be exposed. In the first region SR1, each of the intermediate electrode layers 20a to 20c may have an intermediate pad region MP exposed by the intermediate electrode layer located thereon. In each intermediate laminate 20, the intermediate pad regions MP of the intermediate electrode layers 20a to 20c may be arranged in a stepped manner in the first direction FD. A second stepped structure ST2 may be formed in each intermediate laminate 20 by the intermediate pad regions MP of the intermediate electrode layers 20a to 20c. The second stepped structure ST2 may have a first inclination angle θ1 relative to the top surface of the substrate 3.

[0058] The second stepped structure ST2 may have the same shape as the first stepped structure ST1. If the first stepped structure ST1 has a stepped shape gradually rising from a central portion of the first stepped structure ST1 to both sides of the first stepped structure ST1 in the first direction FD, the second stepped structure ST2 may also have a stepped shape gradually rising from a central portion of the second stepped structure ST2 to both sides of the second stepped structure ST2 in the first direction FD.

[0059] The first stepped structure ST1 of the upper stack 30 and the second stepped structure ST2 of the intermediate stack 20 may be arranged in the second direction SD (when viewed from the top) and may be located at different heights from each other. For example, as the distance from the first stepped structure ST1 in the second direction SD increases, the first stepped structure ST1 of the upper stack 30 may be farthest from the substrate 3, and the second stepped structure ST2 of the intermediate stack 20 may be closer to the substrate 3.

[0060] When viewed from the top, the upper electrode layers 30a to 30c of the upper stack 30 may be separated in the first region SR1 to form both sides of the first stepped structure ST1 and expose both sides of the second stepped structure ST2. However, a portion of each intermediate stack 20 may overlap the first stepped structure ST1 in the vertical direction VD. Since there is a portion overlapping the first stepped structure ST1 in the vertical direction VD, the intermediate electrode layers 20a to 20c of the intermediate stack 20 are not separated in the first region SR1.

[0061] In the first region SR1, a first side wall SW1 and a second side wall SW2 may be formed in the electrode structure ES. The first side wall SW1 may couple the first stepped structure ST1 of the upper stack 30 and the second stepped structure ST2 of the uppermost intermediate stack 20. The height of the first side wall SW1 may correspond to a difference between a vertical position of a top of the first stepped structure ST1 of the upper stack 30 and a vertical position of a top of the second stepped structure ST2 of the uppermost intermediate stack 20.

[0062] The second sidewall SW2 may connect the second stepped structure ST2 of the upper intermediate stack 20 located above and the second stepped structure ST2 of the lower intermediate stack 20 located below. The height of the second sidewall SW2 may correspond to the difference between the vertical positions of the top of the second stepped structure ST2 of the upper intermediate stack 20 and the top of the second stepped structure ST2 of the lower intermediate stack 20.

[0063] For example, the height of each of the first side wall SW1 and the second side wall SW2 may be equal to or greater than twice the vertical pitch of the electrode layers (e.g., 10a to 10c, 20a to 20c, and 30a to 30c). The vertical pitch of the electrode layers may be defined as the sum of the height of one electrode layer and the height of the interlayer dielectric layer 40. This embodiment shows that the height of each of the first side wall SW1 and the second side wall SW2 is three times the vertical pitch of the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c.

[0064] In the second region SR2, a portion of the upper electrode layers 30a to 30c may be exposed. In the second region SR2, each of the upper electrode layers 30a to 30c may have a second upper pad region UP2 exposed by the upper electrode layer located thereon. The second upper pad regions UP2 of the upper electrode layers 30a to 30c may be arranged in a stepped manner in the first direction FD. A third stepped structure ST3 may be formed in the upper stack 30 by the second upper pad regions UP2 of the upper electrode layers 30a to 30c. The third stepped structure ST3 may have a first inclination angle θ1 relative to the top surface of the substrate 3. The present embodiment shows a third stepped structure ST3 having a stepped shape that gradually rises from the central portion of the third stepped structure ST3 to both sides of the third stepped structure ST3 in the first direction FD.

[0065] In the second region SR2, the upper stack 30 may expose a portion of each of the lower stacks 10. In the second region SR2, the upper lower stack 10 may expose a portion of the lower lower stack 10 located therebelow.

[0066] Each lower stack 10 may include a plurality of lower electrode layers 10a to 10c alternately stacked with the interlayer dielectric layer 40 in the vertical direction VD. The number of lower electrode layers configuring each lower stack 10 may be n (where n is a natural number of 2 or greater). This embodiment shows each lower stack 10 having three lower electrode layers 10a to 10c.

[0067] In the second region SR2, a portion of the lower electrode layers 10a to 10c of each lower stack 10 may be exposed. In the second region SR2, each of the lower electrode layers 10a to 10c may have a lower pad region LP exposed by the lower electrode layer located thereon. In each lower stack 10, the lower pad regions LP of the lower electrode layers 10a to 10c may be arranged in a stepped manner in the first direction FD. A fourth stepped structure ST4 may be formed in each lower stack 10 by the lower pad regions LP of the lower electrode layers 10a to 10c. The fourth stepped structure ST4 may have a first inclination angle θ1 relative to the top surface of the substrate 3.

[0068] The fourth stepped structure ST4 may have the same shape as the third stepped structure ST3. If the third stepped structure ST3 has a stepped shape gradually rising from a central portion of the third stepped structure ST3 to both sides of the third stepped structure ST3 in the first direction FD, the fourth stepped structure ST4 may also have a stepped shape gradually rising from a central portion of the fourth stepped structure ST4 to both sides of the fourth stepped structure ST4 in the first direction FD.

[0069] The third stepped structure ST3 of the upper stack 30 and the fourth stepped structure ST4 of the lower stack 10 may be arranged in the second direction SD (when viewed from the top) and may be located at different heights from each other. For example, as the distance from the third stepped structure ST3 in the second direction SD increases, the third stepped structure ST3 of the upper stack 30 may be farthest from the substrate 3, and the fourth stepped structure ST4 of the lower stack 10 may be closer to the substrate 3.

[0070] When viewed from the top, the upper electrode layers 30a to 30c of the upper stack 30 may be separated in the second region SR2 to form both sides of the third stepped structure ST3 and expose both sides of the fourth stepped structure ST4. However, a portion of each lower stack 10 may overlap the third stepped structure ST3 in the vertical direction VD. Since there is a portion overlapping the third stepped structure ST3 in the vertical direction VD, the lower electrode layers 10a to 10c of the lower stack 10 are not separated in the second region SR2.

[0071] A third side wall SW3 and a fourth side wall SW4 may be formed in the electrode structure ES in the second region SR2. The third side wall SW3 may couple the third stepped structure ST3 of the upper stack 30 and the fourth stepped structure ST4 of the uppermost lower stack 10. The height of the third side wall SW3 may correspond to a difference between a vertical position of a top of the third stepped structure ST3 of the upper stack 30 and a vertical position of a top of the fourth stepped structure ST4 of the uppermost lower stack 10.

[0072] The fourth sidewall SW4 may connect the fourth stepped structure ST4 of the upper lower stack 10 and the fourth stepped structure ST4 of the lower lower stack 10. The height of the fourth sidewall SW4 may correspond to the difference between the vertical position of the top of the fourth stepped structure ST4 of the upper lower stack 10 and the vertical position of the top of the fourth stepped structure ST4 of the lower stack 10.

[0073] For example, the height of each of the third side wall SW3 and the fourth side wall SW4 may be equal to or greater than twice the vertical spacing of the electrode layers (e.g., 10a to 10c, 20a to 20c, and 30a to 30c). The vertical spacing of the electrode layers may be defined as the sum of the height of one electrode layer and the height of the interlayer dielectric layer 40. This embodiment shows that the heights of the third side wall SW3 and the fourth side wall SW4 are nine times and three times the vertical spacing of the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c, respectively.

[0074] In order to allow the first stepped structure ST1 and the second stepped structure ST2 to be locally formed in the first region SR1, each of the first side wall SW1 and the second side wall SW2 has at least one corner. Similarly, in order to allow the third stepped structure ST3 and the fourth stepped structure ST4 to be locally formed in the second region SR2, each of the third side wall SW3 and the fourth side wall SW4 has at least one corner.

[0075] Dielectric supports 50 may be formed at the corners of the first to fourth side walls SW1 to SW4, respectively, so that the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c may be isolated from the corners of the first to fourth side walls SW1 to SW4. Therefore, the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c are not disposed at the corners of the first to fourth side walls SW1 to SW4.

[0076] The dielectric supporter 50 may pass through the electrode structure ES at a corner. For example, the dielectric supporter 50 may have a vertical column shape passing through the electrode structure ES in the vertical direction VD. The dielectric supporter 50 may be formed of an oxide (eg, silicon oxide).

[0077] Although the present embodiment shows the dielectric supporter 50 having a circular cross-sectional shape, the present disclosure is not limited thereto. The cross-sectional shape of the dielectric supporter 50 may be a polygonal shape (eg, a triangular or quadrilateral shape) or an elliptical shape.

[0078] 6A to 9A is a representation of a top view that helps explain the steps of fabricating a three-dimensional memory device according to an embodiment of the present disclosure, and FIG. 6B to FIG. 9B is a representation of a perspective view that helps explain the steps of fabricating a three-dimensional memory device according to an embodiment of the present disclosure.

[0079] Reference Fig. 6A and Figure 6B , the first material layers 40 and the second material layers 60 may be alternately stacked on the substrate 3 , thereby forming a pre-laminated layer ML.

[0080] The first material layer 40 and the second material layer 60 may be formed of different materials. For example, the first material layer 40 may be formed of a dielectric material for an interlayer dielectric layer, and the second material layer 60 may be formed of a dielectric material for a sacrificial layer and having an etching selectivity with respect to the first material layer 40. The first material layer 40 may be formed of an oxide (e.g., silicon oxide), and the second material layer 60 may be formed of a nitride (e.g., silicon nitride).

[0081] The dielectric support 50 may be formed by filling a vertical hole passing through the pre-laminated layer ML in the vertical direction VD with a dielectric material. The dielectric support 50 may be formed of a material having an etching selectivity relative to the sacrificial layer 60. For example, if the sacrificial layer 60 is formed of nitride, the dielectric support 50 may be formed of oxide. The dielectric support 50 may be formed of the same material as the interlayer dielectric layer 40.

[0082] Reference Fig. 7A and Figure 7B , a step structure ST may be formed on the top of the pre-laminated layer ML in each of the first region SR1 and the second region SR2 .

[0083] The stair structure ST may be formed through a process to be described below.

[0084] A line type mask pattern (not shown) having a line type opening is formed on the pre-stack layer ML, the line type opening exposing the pre-stack layer ML in the form of a line extending in the second direction SD in each of the first region SR1 and the second region SR2. Then, a step structure ST may be formed by alternately and repeatedly performing a unit etching process of etching the pre-stack layer ML to a first etching depth using the line type mask pattern as an etching barrier and a trimming process of increasing the width of the line type opening in the first direction FD. The first etching depth may be the same as the vertical pitch of the second material layer 60.

[0085] The line-type mask pattern may be formed using a photolithography process, and the line-type mask pattern may be removed after the step structure ST is formed.

[0086] Reference Fig. 8A and Figure 8B In each of the first region SR1 and the second region SR2, a portion of the stepped structure ST may be transferred downward in multiple stages, and thereby stepped structures ST′ and ST″ at different heights may be formed.

[0087] Specifically, a first hole-type mask pattern (not shown) having openings (opening holes) respectively exposing a portion of each step structure ST is formed on the pre-laminated layer ML formed with the step structures ST. Each opening may have a shape that passes through the step structure ST in the first direction FD. The length of the opening in the second direction SD may be shorter than the length of the step structure ST in the second direction SD, and the width of the opening in the first direction FD may be greater than the width of the step structure ST in the first direction FD.

[0088] The first-level stepped structure ST' is formed by a first pad etching process that etches the pre-stack ML to a second etching depth using a first hole-type mask pattern as an etching barrier and thereby transfers the stepped structure ST downward. Sidewalls SW may be formed in the pre-stack ML by the first pad etching process. The height of each sidewall SW may correspond to the height difference between the top of the upper stepped structure ST and the top of the lower stepped structure ST'.

[0089] After performing a trimming process of widening the width and length of the opening in the first direction FD and the second direction SD, a second-level step structure ST' is formed by a second pad etching process using the trimmed first hole mask pattern as an etching barrier. Sidewalls SW may be additionally formed in the pre-laminated layer ML by the second pad etching process. The height of each sidewall SW may correspond to a height difference between a top of an upper step structure ST' and a top of a lower step structure ST'.

[0090] Each of the sidewalls SW formed by the first pad etching process and the second pad etching process may have at least one corner. The corners of the sidewalls SW may be aligned with the dielectric supporters 50, respectively. During the first pad etching process and the second pad etching process, the dielectric supporter 50 may be etched together with the pre-laminated layer ML and may be located at the corners of the sidewalls SW. The sacrificial layer 60 may be isolated from the corners of the sidewalls SW by the dielectric supporter 50 located at the corners of the sidewalls SW.

[0091] The first hole type mask pattern may be formed using a photolithography process, and the first hole type mask pattern may be removed after the step structures ST′ and ST″ are formed.

[0092] Reference Fig.9A and Fig. 9B , the step structures ST′ and ST″ formed in the second region SR2 may be transferred downward, and thereby step structures ST″′ and ST″″ may be formed.

[0093] The stair structures ST'" and ST"" may be formed by processes to be described below.

[0094] A second hole-type mask pattern (not shown) having openings exposing the stepped structures ST′ and ST″ of the second region SR2 is formed on the pre-stacked layer ML. The pre-stacked layer ML is etched using the second hole-type mask pattern as an etching barrier. The second hole-type mask pattern may be formed using a photolithography process, and the second hole-type mask pattern may be removed after the stepped structures ST′″ and ST″″ are formed.

[0095] Then, although not shown, after removing the second material layer 60 serving as the sacrificial layer, an electrode layer ( Figure 5 10a to 10c, 20a to 20c and 30a to 30c).

[0096] Next, effects according to the embodiments of the present disclosure will be described.

[0097] In the etching process of forming the stepped structures ST' to ST", there is a high possibility that etching residues are generated near the triple point where the corner of the side wall SW and the bottom surface located thereunder intersect. A large amount of nitride forming the second material layer 60 used as a sacrificial layer may be included in the etching residues. Due to this fact, since the nitride included in the etching residues is replaced by the electrode material during the process of replacing the sacrificial layer with the electrode layer, a conductive pattern may be formed near the triple point. Therefore, a malfunction may occur when the electrode layer is located at the corner of the side wall SW because the upper electrode and the lower electrode may be short-circuited through the conductive pattern.

[0098] According to the embodiment disclosed in this article, by forming a dielectric support member 50 at the position where the corner of the side wall SW is to be formed, and thereby isolating the electrode layers 10a to 10c, 20a to 20c and 30a to 30c from the corner of the side wall SW, even if a conductive pattern is formed near the triple point, the occurrence of failure due to a short circuit between the upper electrode and the lower electrode can be prevented.

[0099] Fig.10 is a top view showing a representation of a dielectric support according to another embodiment of the present disclosure.

[0100] Reference Fig.10 When viewed from the top, the dielectric support member 50 may have a structure corresponding to the shape of the corners of the side walls SW1 to SW4. For example, when viewed from the top, in the case where the corners of the side walls SW1 to SW4 each have an L-shape, the dielectric support member 50 may also have an L-shape.

[0101] Fig.11 is a top view showing a representation of a dielectric support according to yet another embodiment of the present disclosure, and Fig.12 It is along Fig.11 A cross-sectional view taken along line II'.

[0102] Reference Fig.11 and Fig.12Each dielectric supporter 50 may include a pillar PP and a plurality of horizontal dielectric layers EP. The pillar PP may pass through the electrode structure ES in the vertical direction VD at a corner of each of the sidewalls SW1 to SW4.

[0103] Each horizontal dielectric layer EP may extend from the outer peripheral surface of the pillar PP in a horizontal direction parallel to a plane defined by the first direction FD and the second direction SD between the interlayer dielectric layers 40. The horizontal dielectric layers EP may be disposed at the same layers as the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c, respectively. A plurality of horizontal dielectric layers EP may be alternately stacked with a plurality of interlayer dielectric layers 40 around the pillar PP.

[0104] Because the dielectric supporter 50 includes the horizontal dielectric layer EP, gaps between the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c and the corners of the side walls SW1 to SW4 may increase in a horizontal direction by the width of the horizontal dielectric layer EP.

[0105] FIG. 13A to FIG. 13C It helps explain the formation Fig.11 and Fig.12 A representation of a cross-sectional view of the method of the dielectric support is shown.

[0106] Reference Fig.13A , after the first material layers 40 and the second material layers 60 are alternately stacked on the substrate 3 and thereby form the pre-laminated layer ML, a vertical hole VH passing through the pre-laminated layer ML may be formed.

[0107] Reference Fig. 13B , the second material layer 60 around the vertical hole VH may be removed, and thereby a plurality of horizontal grooves HH may be formed. The process of forming the horizontal grooves HH may be performed by injecting an etching material (e.g., an etchant) capable of removing the second material layer 60 into the vertical hole VH. The horizontal grooves HH may extend from the sidewalls of the vertical hole VH in a horizontal direction parallel to a plane defined by the first direction FD and the second direction SD.

[0108] Reference Fig. 13C When the dielectric material is filled in the vertical hole VH and the horizontal groove HH, the dielectric supporter 50 may be formed. The portion of the dielectric supporter 50 filled in the vertical hole VH may correspond to the pillar PP, and the portion of the dielectric supporter 50 filled in the horizontal groove HH may correspond to the horizontal dielectric layer EP.

[0109] Fig.14 is a top view showing a representation of a dielectric support according to yet another embodiment of the present disclosure, and Fig.15 It is shown Fig.14 A stereogram showing a portion of a .

[0110] Reference Fig.14 and Fig.15 , each dielectric support 50 may include a column PP' and a plurality of horizontal dielectric layers EP'. The column PP' may pass through the electrode structure ES in the vertical direction VD at or near the corner vicinity of each of the side walls SW1 to SW4. Although the present embodiment shows three columns PP' formed near each corner, the present disclosure is not limited thereto. One or at least two columns PP' may be formed near each corner.

[0111] Each horizontal dielectric layer EP' may extend in a horizontal direction from the outer peripheral surface of the pillar PP' between the interlayer dielectric layers 40. The horizontal dielectric layers EP' may be disposed at the same layer as the electrode layers 10a to 10c, 20a to 20c, and 30a to 30c, respectively. At the corner, a plurality of horizontal dielectric layers EP' may be alternately disposed with a plurality of interlayer dielectric layers 40 around the pillar PP'.

[0112] FIG. 16A to FIG. 21B is to help explain manufacturing including Fig.14 and Fig.15 A representation of a method of a three-dimensional memory device with a dielectric support as shown. Specifically, FIG. 16A to FIG. 21A is a representation of a top view that helps explain the steps of a method of making a three-dimensional memory device, and FIG. 16B to FIG. 21B is a representation of a perspective view that helps explain the steps of a method of making a three-dimensional memory device.

[0113] Reference Fig.16A and Fig. 16B , the first material layer 40 and the second material layer 60 may be alternately stacked on the substrate 3, and thereby the pre-laminated layer ML may be formed. A step structure ST may be formed on the top of the pre-laminated layer ML in the first region SR1 and the second region SR2, respectively.

[0114] Reference Fig.17A and Fig. 17B In each of the first region SR1 and the second region SR2, a portion of the stepped structure ST may be transferred downward by an etching process, and thereby stepped structures ST' and ST" at different heights may be formed. Due to the height difference between the stepped structures ST, ST' and ST", a plurality of sidewalls SW may be formed in the pre-stacked layer ML.

[0115] Reference Fig.18A and Fig.18BThe stepped structures ST' and ST" formed in the second region SR2 may be transferred downward by an etching process, and thereby stepped structures ST"' and ST"" may be formed. Utilizing the different heights between the stepped structures ST, ST', ST", ST"' and ST"", a plurality of sidewalls SW may be formed in the pre-stacked layer ML.

[0116] Reference Fig.19A and Fig.19B , a plurality of vertical holes VH' passing through the pre-laminated layer ML in the vertical direction VD may be formed in the region adjacent to the corner of the side wall SW. Although the present embodiment shows three vertical holes VH' formed near each corner, the present disclosure is not limited thereto. One or at least two vertical holes VH' may be formed near each corner.

[0117] Reference Fig. 20A and Fig. 20B , when the second material layer 60 formed at the corner is removed through the vertical hole VH′, a plurality of horizontal grooves HH′ may be formed.

[0118] The process of forming the horizontal groove HH' may be performed by injecting an etching material (e.g., an etchant) capable of removing the second material layer 60 into the vertical hole VH'. The horizontal groove HH' may extend from the sidewall of the vertical hole VH' in a direction parallel to a plane defined by the first direction FD and the second direction SD, and may be coupled to the corner of the sidewall SW. Therefore, the second material layer 60 formed at the corner may be removed.

[0119] Reference Fig.21A and Fig.21B , when the dielectric material is filled in the vertical hole VH' and the horizontal groove HH', a dielectric supporter 50 may be formed. The portion of the dielectric supporter 50 filled in the vertical hole VH' may correspond to the pillar PP', and the portion of the dielectric supporter 50 filled in the horizontal groove HH' may correspond to the horizontal dielectric layer EP'.

[0120] Then, although not shown, after removing the second material layer 60 used as the sacrificial layer, an electrode layer ( Fig.15 10a to 10c, 20a to 20c and 30a to 30c).

[0121] Fig. 22 is a block diagram schematically illustrating a representation of a memory system including a memory device according to an embodiment of the present disclosure.

[0122] Reference Fig. 22 , a memory system 600 according to one embodiment may include a nonvolatile memory device (NVM device) 610 and a memory controller 620 .

[0123] The nonvolatile memory device (NVM device) 610 may be composed of the above-mentioned memory device and may be operated in the above-mentioned manner. The memory controller 620 may be configured to control the nonvolatile memory device (NVM device) 610. By the combination of the nonvolatile memory device (NVM device) 610 and the memory controller 620, a memory card or a solid state disk (SSD) may be provided. The SRAM 621 is used as a working memory of the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol of a host connected to the memory system 600.

[0124] The error correction code block (ECC) 624 detects and corrects errors included in data read from the nonvolatile memory device (NVM device) 610 .

[0125] The memory interface (memory I / F) 625 interfaces with the nonvolatile memory device (NVM device) 610 of the present embodiment. The processing unit (CPU) 622 performs general control operations for data exchange of the memory controller 620 .

[0126] Although not shown in the figure, it is obvious to those skilled in the art that the memory system 600 according to the present embodiment can be additionally provided with a ROM storing code data for interfacing with a host. The non-volatile memory device (NVM device) 610 can be provided as a multi-chip package consisting of a plurality of flash memory chips.

[0127] The memory system 600 according to the above-mentioned embodiment can be set as a high-reliability storage medium with a low probability of error occurrence. In particular, the non-volatile memory device of the present embodiment can be included in a memory system such as a solid-state disk (SSD) that is being actively studied recently. In this case, the memory controller 620 can be configured to communicate with an external device (e.g., a host) through one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect Express (PCI-E) protocol, a serial advanced technology attachment (SATA) protocol, a parallel advanced technology attachment (PATA) protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0128] Fig.23 is a block diagram schematically illustrating a representation of a computing system including a memory device according to an embodiment of the present disclosure.

[0129] Reference Fig.23, the computing system 700 according to one embodiment may include a memory system 710 electrically connected to a system bus 760, a microprocessor (CPU) 720, a RAM 730, a user interface 740, and a modem 750 such as a baseband chipset. In the case where the computing system 700 according to the embodiment is a mobile device, a battery (not shown) for providing an operating voltage of the computing system 700 may be additionally provided. Although not shown in the drawings, it is obvious to a person skilled in the art to which the embodiment belongs that the computing system 700 according to the embodiment may be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. The memory system 710 may be configured, for example, as a solid-state drive / solid-state disk (SSD) that uses a non-volatile memory to store data. In addition, the memory system 710 may be configured as a fusion flash memory (e.g., OneNAND flash memory).

[0130] Although the exemplary embodiments of the present disclosure have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered merely as descriptive and not intended to limit the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted by the appended claims and include all equivalents falling within the scope of the appended claims.

[0131] CROSS-REFERENCE TO RELATED APPLICATIONS

[0132] This application claims the priority of Korean Patent Application No. 10-2020-0089546 filed on Jul. 20, 2020 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: An electrode structure, the electrode structure comprising a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a substrate; a first stepped structure and a second stepped structure, the first stepped structure and the second stepped structure being defined in the electrode structure and being located at different heights relative to the top surface of the substrate; a side wall of the electrode structure between the first stepped structure and the second stepped structure; as well as A dielectric support passes through the electrode structure and isolates a corner of the side wall from the plurality of electrode layers.

2. The three-dimensional memory device according to claim 1, wherein: The dielectric supporter and the plurality of interlayer dielectric layers are formed of the same material.

3. The three-dimensional memory device according to claim 1, wherein: The dielectric support includes an oxide.

4. The three-dimensional memory device according to claim 1, wherein: The dielectric support includes a post passing through the electrode structure at the corner.

5. The three-dimensional memory device according to claim 1, wherein: The dielectric support has a shape corresponding to the shape of the corner portion when viewed from the top.

6. The three-dimensional memory device according to claim 1, wherein: The dielectric support comprises: a vertical post passing through the electrode structure at the corner; and A plurality of horizontal dielectric layers extend from the outer peripheral surface of the vertical pillar and are alternately disposed with the plurality of interlayer dielectric layers around the vertical pillar.

7. The three-dimensional memory device according to claim 1, wherein: The dielectric support comprises: a post passing through the electrode structure near the corner; and A plurality of horizontal dielectric layers extend from the outer peripheral surface of the pillar and are alternately disposed with the plurality of interlayer dielectric layers at the corners.

8. The three-dimensional memory device according to claim 1, in, Each of the first stepped structure and the second stepped structure includes a plurality of steps, each of the plurality of steps having the same height as a vertical pitch of the electrode layers, and The height of the side wall corresponds to K times the vertical spacing of the electrode layer, and K is a natural number of 2 or greater.

9. A method of manufacturing a three-dimensional memory device, the method comprising the steps of: forming a pre-stacked layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of sacrificial layers on a substrate; forming a dielectric support through the pre-laminate; forming a first stepped structure on top of the pre-laminate in the thinned region; forming a second stepped structure by transferring a portion of the first stepped structure downward by etching the pre-stacked layer; as well as The sacrificial layer is replaced by an electrode layer, Wherein, in the step of forming the second stepped structure, corners of the sidewalls formed in the pre-stacked layer by etching are isolated from the plurality of sacrificial layers by the dielectric support member.

10. The method according to claim 9, wherein: The dielectric supporter is formed of a material having an etching selectivity with respect to the sacrificial layer.

11. The method according to claim 9, wherein: The sacrificial layer includes nitride, and the dielectric support includes oxide.

12. The method according to claim 9, wherein: The step of forming the dielectric support comprises the following steps: forming a vertical hole through the pre-laminate; and A dielectric material is filled in the vertical hole.

13. The method according to claim 9, wherein: The dielectric supporter is formed in a shape corresponding to the shape of the corner portion when viewed from the top.

14. The method according to claim 9, wherein: The step of forming the dielectric support comprises the following steps: forming a vertical hole through the pre-laminate; forming a plurality of horizontal grooves by removing the sacrificial layer around the vertical holes; and A dielectric material is filled in the vertical hole and the plurality of horizontal grooves.

15. A method of manufacturing a three-dimensional memory device, the method comprising the steps of: forming a pre-stacked layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of sacrificial layers on a substrate; forming a first stepped structure on top of the pre-stacked layer; forming a second stepped structure by transferring a portion of the first stepped structure downward by etching the pre-stacked layer; forming a vertical hole penetrating the pre-laminated layer at a periphery of a corner of a side wall formed in the pre-laminated layer in the step of forming the second stepped structure; forming a plurality of horizontal grooves by removing the plurality of sacrificial layers formed at the corners through the vertical holes; forming a dielectric support in the vertical hole and the plurality of horizontal grooves; as well as The sacrificial layer is replaced by an electrode layer.

16. The method according to claim 15, wherein: The dielectric supporter is formed of a material having an etching selectivity with respect to the sacrificial layer.

17. The method according to claim 15, wherein: The sacrificial layer includes nitride, and the dielectric support includes oxide.

18. The method according to claim 15, wherein: When viewed from the top, the dielectric support has an L-shape corresponding to the shape of the corner portion.

19. The method according to claim 18, wherein: The dielectric support includes at least one post.

20. The method according to claim 19, wherein: The dielectric support also includes a plurality of horizontal dielectric layers extending from an outer peripheral surface of the at least one pillar to fill the L-shape.

Images