Array substrate, manufacturing method thereof and reflective liquid crystal display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a reflective liquid crystal display panel. The array substrate comprises a substrate, source and data lines arranged on the substrate, the source and the data lines being electrically connected, an active layer arranged on the source and the substrate, a drain arranged on the active layer, a projection of the drain on the substrate and a projection of the source on the substrate at least partially overlapping, the active layer being arranged between the drain and the source and being electrically connected to the drain and the source, a first insulating layer arranged on the drain and the substrate, a gate and a scanning line arranged on the first insulating layer, the gate and the scanning line being electrically connected, a second insulating layer arranged on the gate and the first insulating layer, a planar layer arranged on the second insulating layer, a reflective electrode arranged on the planar layer, the reflective electrode being electrically connected to the drain, and the projections of the drain, the active layer and the source on the substrate being located in the projection of the reflective electrode on the substrate. The array substrate can effectively obtain super-high resolution and super-high aperture ratio.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display device, in particular to an array substrate, a manufacturing method thereof and a reflective liquid crystal display panel. BACKGROUND

[0002] At present, in the conventional reflective display, there is a material limitation difficulty in improving the resolution, especially in the small size reflective display, due to the insufficient resolution, the display effect is greatly discounted, and even some required graphics cannot be displayed. Moreover, in the TFT with the traditional BCE (back channel etch) structure, the metal layer is covered on the TFT, which makes the semiconductor layer of the TFT easily affected and causes the TFT characteristics to be poor. Therefore, in the conventional reflective display, the TFT is not covered with the reflective electrode. Therefore, when the natural light irradiates the TFT area, the light reflection cannot be realized, and the aperture ratio is reduced. SUMMARY

[0003] Therefore, the present application provides an array substrate, which can effectively obtain super high resolution and super high aperture ratio.

[0004] An array substrate, comprising:

[0005] a substrate;

[0006] a source electrode and a data line arranged on the substrate, the source electrode and the data line being electrically connected;

[0007] an active layer arranged on the source electrode and the substrate;

[0008] a drain electrode arranged on the active layer;

[0009] a projection of the drain electrode on the substrate and a projection of the source electrode on the substrate at least partially overlap, and the active layer is arranged between the drain electrode and the source electrode and is electrically connected to the drain electrode and the source electrode;

[0010] a first insulating layer arranged on the drain electrode and the substrate;

[0011] a gate electrode and a scan line arranged on the first insulating layer, the gate electrode and the scan line being electrically connected;

[0012] a second insulating layer arranged on the gate electrode and the first insulating layer;

[0013] a planar layer arranged on the second insulating layer;

[0014] a reflective electrode arranged on the planar layer, the reflective electrode being electrically connected to the drain electrode;

[0015] the projections of the drain electrode, the active layer and the source electrode on the substrate are located within the projection of the reflective electrode on the substrate.

[0016] In the embodiment of the present application, the surface of the flat layer matched with the reflective electrode is provided with a first rough structure.

[0017] In the embodiment of the present application, the side of the reflective electrode facing away from the flat layer is provided with a second rough structure.

[0018] In the embodiment of the present application, the second rough structure is a plurality of protrusions, the height of each protrusion is

[0019] In the embodiment of the present application, the material of the reflective electrode is molybdenum or aluminum.

[0020] The present application also provides a reflective liquid crystal display panel comprising the array substrate, the reflective liquid crystal display panel further comprising a color film substrate opposite to the array substrate, the color film substrate comprising a substrate, one side of the substrate facing the array substrate being covered with a common electrode.

[0021] The present application also provides a manufacturing method of an array substrate, the manufacturing method comprising:

[0022] providing a substrate;

[0023] forming a first metal layer on the substrate, etching and patterning the first metal layer to form a source electrode and a data line, the source electrode being electrically connected with the data line;

[0024] forming an oxide semiconductor layer on the source electrode and the substrate, etching and patterning the oxide semiconductor layer to form an active layer;

[0025] forming a second metal layer on the active layer, etching and patterning the second metal layer to form a drain electrode;

[0026] the orthographic projection of the drain electrode on the substrate at least partially overlaps with the orthographic projection of the source electrode on the substrate, and the active layer is located between the drain electrode and the source electrode and is electrically connected with the drain electrode and the source electrode;

[0027] forming a first insulating layer on the substrate to cover the source electrode, the active layer and the drain electrode;

[0028] forming a third metal layer on the first insulating layer, etching and patterning the third metal layer to form a gate electrode and a scan line, the gate electrode and the scan line being electrically connected;

[0029] forming a second insulating layer on the first insulating layer to cover the gate electrode;

[0030] forming a flat layer on the second insulating layer;

[0031] Forming a fourth metal layer on the flat layer, and etching and patterning the fourth metal layer to form a reflective electrode, the reflective electrode being electrically connected with the drain electrode;

[0032] The normal projection of the drain electrode, the active layer and the source electrode on the substrate is located in the normal projection of the reflective electrode on the substrate.

[0033] In the embodiment of the present application, the manufacturing method further comprises: when forming the flat layer on the second insulating layer, forming a first rough structure on the surface of the flat layer matched with the reflective electrode.

[0034] In the embodiment of the present application, the manufacturing method further comprises: when etching and patterning the fourth metal layer to form the reflective electrode, forming a second rough structure on the side of the reflective electrode away from the flat layer.

[0035] In the embodiment of the present application, when etching and patterning the second metal layer to form the drain electrode, a dry etching process is adopted.

[0036] The array substrate of the present application designs the horizontal channel structure (i.e. the source electrode and the drain electrode are located in the same layer and horizontally spaced apart) of the TFT (Thin Film Transistor) into a vertical channel structure (i.e. the source electrode and the drain electrode are located in different layers and at least partially overlap, and the active layer is sandwiched between the source electrode and the drain electrode). Thus, the occupied area of the TFT on the array substrate is reduced, and the channel length of the vertical channel structure of the TFT is reduced, and the conductive capacity of the TFT is increased and the power consumption is reduced. The array substrate effectively avoids the problem that the top end of the traditional BCE (back channel etch) type channel cannot be covered by metal by using the self-shielding effect of the vertical channel structure, so that the reflective electrode can cover the area above the source electrode, the active layer and the drain electrode (i.e. the TFT area), and therefore the TFT area can also be used as a reflection area. Specifically, when the incident light irradiates the TFT area, the incident light can be reflected back by the reflective electrode corresponding to the TFT area to achieve the display effect, so that the aperture ratio is greatly improved. At the same time, the width-length ratio of the TFT vertical channel structure can be achieved by adjusting the thickness of the active layer and the shape curve of the edge of the active layer. According to strict calculation, taking the S0291 AA area (effective display area) 29056x66896um as an example, the resolution can be increased from the original 128x296 to 1937x4459 or even higher by applying this design. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 The cross-sectional manufacturing process schematic diagram of the manufacturing method of the array substrate of the present application;

[0038] Figure 2is a local plane structure schematic diagram of the array substrate of the present application;

[0039] Figure 3 is Figure 2 is a cross-sectional structure schematic diagram of the array substrate along the A-A direction shown in the figure;

[0040] Figure 4 is a local plane structure schematic diagram of the array substrate of the present application;

[0041] Figure 5 is Figure 4 is a cross-sectional structure schematic diagram of the array substrate along the B-B direction shown in the figure;

[0042] Figure 6 is a cross-sectional manufacturing process schematic diagram of the manufacturing method of the array substrate of the present application;

[0043] Figure 7 is a local plane structure schematic diagram of the array substrate of the present application;

[0044] Figure 8 is Figure 7 is a cross-sectional structure schematic diagram of the array substrate along the C-C direction shown in the figure;

[0045] Figures 9 to 10 is a cross-sectional manufacturing process schematic diagram of the manufacturing method of the array substrate of the present application;

[0046] Figure 11 is a local plane structure schematic diagram of the array substrate of the present application;

[0047] Figure 12 is Figure 11 is a cross-sectional structure schematic diagram of the array substrate along the D-D direction shown in the figure;

[0048] Figure 13 is a cross-sectional structure schematic diagram of the reflective liquid crystal display panel of the present application. DETAILED DESCRIPTION

[0049] In order to facilitate the understanding of those skilled in the art, the present application provides a specific implementation process of the technical solutions provided by the present application through the following examples.

[0050] Please refer to Figures 1 to 13 , the present application provides a manufacturing method of an array substrate, which comprises:

[0051] As Figure 1 shown, a substrate 11 is provided, wherein the substrate 11 can be made of glass, quartz, acrylic or polycarbonate and the like.

[0052] As Figure 1 and Figure 2As shown in FIG. 1, a first metal layer is formed on the substrate 11, and the first metal layer is etched and patterned to form the source electrode 12a and the data line 12, wherein the source electrode 12a and the data line 12 are both formed by the first metal layer through one patterning process, the source electrode 12a is electrically connected with the data line 12, or the source electrode 12a is a part of the data line 12. In this embodiment, the first metal layer can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo).

[0053] As shown in FIG. 2, an oxide semiconductor layer covering the source electrode 12a and the data line 12 is formed on the substrate 11, and the oxide semiconductor layer is etched and patterned to form the active layer 13, wherein the active layer 13 at least partially overlaps with the source electrode 12a. In this embodiment, the oxide semiconductor layer is made of indium gallium zinc oxide (IGZO), and the amorphous oxide IGZO is used as the material of the semiconductor layer, which can effectively reduce the problem of transistor leakage current overheating caused by traditional silicon oxide. Figures 1 to 3 As shown in FIG. 3, a second metal layer covering the active layer 13 is formed on the substrate 11, and the second metal layer is etched and patterned to form the drain electrode 14, wherein the drain electrode 14 is located above the active layer 13 and at least partially overlaps with the active layer 13, or completely overlaps with the active layer 13. In this embodiment, the drain electrode 14 completely overlaps with the active layer 13, but is not limited thereto. In this embodiment, the second metal layer can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo), or copper and aluminum (Cu / Al). When the second metal layer is etched and patterned to form the drain electrode 14, a dry etching process is used to avoid corrosion of the active layer 13.

[0054] Figure 4 As shown in FIG. 4, a first insulating layer 15 covering the source electrode 12a, the data line 12, the active layer 13 and the drain electrode 14 is formed on the substrate 11, wherein the first insulating layer 15 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two. Figure 5 As shown in FIG. 5, a second insulating layer 16 covering the first insulating layer 15 is formed on the substrate 11, wherein the second insulating layer 16 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0055] Figure 6 As shown in FIG. 6, a third insulating layer 17 covering the second insulating layer 16 is formed on the substrate 11, wherein the third insulating layer 17 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0056] As shown in FIG. 7, a fourth insulating layer 18 covering the third insulating layer 17 is formed on the substrate 11, wherein the fourth insulating layer 18 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two. Figure 7 Figure 8 ​​​As shown, a third metal layer is formed on the first insulating layer 15. The third metal layer is etched and patterned to form a gate 16a and a scan line 16. Both the gate 16a and the scan line 16 are formed from the third metal layer through a single patterning process. The gate 16a is electrically connected to the scan line 16, or the gate 16a is part of the scan line 16. In this embodiment, the third metal layer can be made of copper and molybdenum-niobium (Cu / MoNb), copper and molybdenum (Cu / Mo), or copper and aluminum (Cu / Al).

[0057] like Figure 9 As shown, a second insulating layer 17 covering the gate 16a and the scan line 16 is formed on the first insulating layer 15. The second insulating layer 17 is, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0058] like Figure 10 As shown, a planarization layer 18 is formed on the second insulating layer 17, and a through hole 101 is formed at the position corresponding to the drain electrode 14, penetrating the planarization layer 18, the second insulating layer 17 and the first insulating layer 15, so that the drain electrode 14 is exposed through the through hole 101.

[0059] like Figures 11 to 12 As shown, a fourth metal layer is formed on the planarization layer 18, and the fourth metal layer is etched and patterned to form a reflective electrode 19. The reflective electrode 19 is filled into the via 101 and electrically connected to the drain 14. The orthogonal projections of the drain 14, the active layer 13, and the source 12a onto the substrate 11 lie within the orthogonal projection of the reflective electrode 19 onto the substrate 11. In this embodiment, the reflective electrode 19 is made of an inert and highly reflective metal, such as molybdenum or aluminum.

[0060] Furthermore, when forming the planarization layer 18 on the second insulating layer 17, a first rough structure 181 is simultaneously formed on the surface of the planarization layer 18 that mates with the reflective electrode 19. In this embodiment, an imprinting process can be used to form the uneven first rough structure 181 on the outer surface of the planarization layer 18. Specifically, by designing the optimal imprinting pattern and using the corresponding planarization layer 18 material (the material of the planarization layer 18 can be a special imprinting photoresist), the pattern is imprinted before curing. After imprinting, the photoresist is cured to form the first rough structure 181. Due to the presence of the first rough structure 181, after forming the fourth metal layer on the outer surface of the planarization layer 18 with the first rough structure 181, a second rough structure 191 will be formed on the outer surface of the fourth metal layer facing away from the planarization layer 18. Then, the fourth metal layer is etched and patterned to form the reflective electrode 19 with the second rough structure 191, thereby achieving the effect of diffuse reflection.

[0061] The present invention also provides an array substrate, comprising:

[0062] like Figure 1 As shown, substrate 11, wherein substrate 11 may be made of materials such as glass, quartz, acrylic or polycarbonate.

[0063] like Figure 1 and Figure 2 As shown, a source electrode 12a and a data line 12 are disposed on a substrate 11. The source electrode 12a and the data line 12 are electrically connected. The source electrode 12a and the data line 12 are both formed by a single patterning process, or the source electrode 12a is part of the data line 12. In this embodiment, the source electrode 12a and the data line 12 can be made of copper and molybdenum niobium (Cu / MoNb) or copper and molybdenum (Cu / Mo).

[0064] like Figures 1 to 3 As shown, an active layer 13 is disposed on the source electrode 12a and the substrate 11, and the active layer 13 at least partially overlaps with the source electrode 12a. The active layer 13 is indium gallium zinc oxide (IGZO). Using amorphous oxide IGZO as the semiconductor layer material can effectively reduce the leakage current and overheating problems of transistors using traditional silicon oxide. In this embodiment, the active layer 13 includes a first connection portion 131 and a second connection portion 132 connected to the first connection portion 131. The first connection portion 131 is located above and overlaps with the source electrode 12a, and the orthographic projection of the first connection portion 131 on the substrate 11 lies within the orthographic projection of the source electrode 12a on the substrate 11. The second connection portion 132 is located on the substrate 11 and is disposed side-by-side with the source electrode 12a.

[0065] like Figures 3 to 5 As shown, a drain 14 covers the active layer 13, and the drain 14 at least partially or completely overlaps with the active layer 13. The drain 14 can be made of copper and molybdenum-niobium (Cu / MoNb), copper and molybdenum (Cu / Mo), or copper and aluminum (Cu / Al). In this embodiment, the drain 14 and the active layer 13 completely overlap, but this is not a limitation. Specifically, the drain 14 includes a third connection portion 141 and a fourth connection portion 142 connected to the third connection portion 141. The third connection portion 141 overlaps above the first connection portion 131, and the fourth connection portion 142 overlaps above the second connection portion 132. The thicknesses of the third connection portion 141 and the fourth connection portion 142 can be selected according to actual needs, specifically, it is optimal that the total thickness of the source 12a, the first connection portion 131, and the third connection portion 141 is equal to the total thickness of the second connection portion 132 and the fourth connection portion 142.

[0066] like Figure 6As shown in FIG. 1, a first insulating layer 15 is formed on the source 12a, the data line 12, the active layer 13 and the drain 14. The first insulating layer 15 can be made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0067] As shown in FIG. 2, a gate 16a and a scan line 16 are formed on the first insulating layer 15. The gate 16a is electrically connected to the scan line 16. The third metal layer can be made of copper and molybdenum niobium (Cu / MoNb), or copper and molybdenum (Cu / Mo), or copper and aluminum (Cu / Al). Figure 7 Figure 8 As shown in FIG. 3, a second insulating layer 17 is formed on the gate 16a and the first insulating layer 15. The second insulating layer 17 can be made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination of the two.

[0068] As shown in FIG. 4, a planar layer 18 is formed on the second insulating layer 17, and a reflective electrode 19 is formed on the planar layer 18. The reflective electrode 19 is electrically connected to the drain 14. Figure 9 As shown in FIG. 5, the array substrate further comprises a through hole 101 penetrating through the planar layer 18, the second insulating layer 17 and the first insulating layer 15. The reflective electrode 19 fills the through hole 101 and is electrically connected to the drain 14. The orthogonal projection of the drain 14, the active layer 13 and the source 12a on the base 11 is within the orthogonal projection of the reflective electrode 19 on the base 11. In this embodiment, the reflective electrode 19 is made of molybdenum or aluminum.

[0069] Figures 9 to 12 The array substrate of the present application changes the horizontal channel structure (i.e. the source 12a and the drain 14 are on the same layer and horizontally spaced apart) of the TFT into a vertical channel structure (i.e. the source 12a and the drain 14 are on different layers and at least partially overlap, and the active layer 13 is between the source 12a and the drain 14). Thus, the area occupied by the TFT on the array substrate is reduced, and the channel length of the vertical channel structure of the TFT is reduced, which increases the conductivity of the TFT and reduces power consumption. The array substrate effectively avoids the problem that the top of the channel of the conventional BCE (back channel etch) type cannot be covered by metal, by using the self-shielding effect of the vertical channel structure. Thus, the reflective electrode 19 can also cover the area above the source 12a, the active layer 13 and the drain 14 (i.e. the TFT area 40 in FIG. 6), so that the TFT area can also serve as a reflective area, which increases the reflective area of the reflective electrode 19. Figure 10 Figure 11

[0070] The array substrate of the present application changes the horizontal channel structure (i.e. the source 12a and the drain 14 are on the same layer and horizontally spaced apart) of the TFT into a vertical channel structure (i.e. the source 12a and the drain 14 are on different layers and at least partially overlap, and the active layer 13 is between the source 12a and the drain 14). Thus, the area occupied by the TFT on the array substrate is reduced, and the channel length of the vertical channel structure of the TFT is reduced, which increases the conductivity of the TFT and reduces power consumption. The array substrate effectively avoids the problem that the top of the channel of the conventional BCE (back channel etch) type cannot be covered by metal, by using the self-shielding effect of the vertical channel structure. Thus, the reflective electrode 19 can also cover the area above the source 12a, the active layer 13 and the drain 14 (i.e. the TFT area 40 in FIG. 6), so that the TFT area can also serve as a reflective area, which increases the reflective area of the reflective electrode 19. Figure 7

[0071] In particular, please refer to​​​​​Figure 13 As shown, when the incident light irradiates the TFT area, the incident light can be reflected back by the reflection electrode 19 corresponding to the TFT area to realize the display effect, thus greatly improving the aperture ratio. Meanwhile, the width-length ratio of the TFT vertical channel structure can be achieved by adjusting the thickness of the active layer 13 and the shape curve of the edge of the active layer 13, for example, by designing the shape of the edge of the active layer 13 as an irregular pattern to adjust the width-length ratio. After strict calculation, taking the S0291 AA area (effective display area) 29056x66896um as an example, the resolution can be improved from the original 128x296 to 1937x4459 or even higher by applying this design.

[0072] Further, as shown in Figure 10 and Figure 12 The surface of the flat layer 18 cooperating with the reflection electrode 19 is provided with a first rough structure 181, and the side of the reflection electrode 19 facing away from the flat layer 18 is provided with a second rough structure 191, and the second rough structure 191 and the first rough structure 181 correspond to each other in shape and size. The second rough structure 191 can cause the reflection electrode 19 to diffuse reflection. In this embodiment, the first rough structure 181 can be formed on the surface of the flat layer 18 by using the imprinting process. Specifically, by designing the best imprinting pattern, the corresponding flat layer 18 material (the material of the flat layer 18 can use a special imprinting photoresist) is used before curing, the imprinting pattern is pressed, and the photoresist is cured after the imprinting is completed. And because of the existence of the first rough structure 181, after the reflection electrode 19 is deposited on the surface of the flat layer 18 with the first rough structure 181, the second rough structure 191 is formed on the side of the reflection electrode 19 facing away from the flat layer, and then the fourth metal layer is etched and patterned to form the reflection electrode 19 with the second rough structure 191, that is, the effect of diffuse reflection can be achieved.

[0073] Further, as shown in Figure 12 The first rough structure 181 and the second rough structure 191 are, for example, a plurality of protrusions, and the height of each protrusion is optimal, and the slope angle is 15-25 degrees optimal. Among them, a plurality of protrusions collectively form a first rough structure 181 or a second rough structure 191 with wave peaks and valleys.

[0074] As shown in Figure 13As shown, the present application further provides a reflective liquid crystal display panel, which comprises the array substrate and a color filter substrate opposite to the array substrate and a liquid crystal layer 30 between the array substrate and the color filter substrate. The color filter substrate comprises a substrate 21, and a common electrode 22 is covered on the side of the substrate 21 facing the array substrate, and the common electrode 22 is made of transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). In the embodiment, when natural light is incident from the side of the color filter substrate to the array substrate, the display effect of the reflective liquid crystal display panel is finally realized by applying pixel voltage on the reflective electrode 19 and common voltage Vcom on the common electrode 22 to form an electric field for controlling the deflection of the liquid crystal layer 30.

[0075] In this document, the terms "upper", "lower", "left", "right", "front", "back", etc. are defined according to the position of the structure in the drawing and the position of the structure relative to each other, only for the purpose of expressing the technical solution clearly and conveniently. It should be understood that the use of the terms should not limit the scope of the application. It should also be understood that the terms "first" and "second" used herein are only used for distinguishing names, and do not limit the number and order.

[0076] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any skilled person in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the technical solution of the present application, and the equivalent embodiments of equivalent changes are obtained. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not depart from the technical solution of the present application, is still within the protection scope of the present application.

Claims

1. An array substrate, characterized by, The application relates to a reflective liquid crystal display panel, which comprises: a substrate (11); a source electrode (12a) and a data line (12) arranged on the substrate (11), the source electrode (12a) being electrically connected with the data line (12); an active layer (13) arranged on the source electrode (12a) and the substrate (11); a drain electrode (14) covering the active layer (13), the drain electrode (14) completely overlapping the active layer (13); a normal projection of the drain electrode (14) on the substrate at least partially coinciding with a normal projection of the source electrode (12a) on the substrate, the active layer (13) being arranged between the drain electrode (14) and the source electrode (12a) and being electrically connected with the drain electrode (14) and the source electrode; the active layer (13) comprising a first connecting part (131) and a second connecting part (132) connected with the first connecting part (131), the first connecting part (131) being arranged above the source electrode (12a) and overlapping the source electrode (12a), and a normal projection of the first connecting part (131) on the substrate (11) being arranged in a normal projection of the source electrode (12a) on the substrate (11); the second connecting part (132) being arranged on the substrate (11) and being arranged side by side with the source electrode (12a); a first insulating layer (15) covering the drain electrode (14) and the substrate (11); a gate electrode (16a) and a scanning line (16) arranged on the first insulating layer (15), the gate electrode (16a) being electrically connected with the scanning line (16); a second insulating layer (17) covering the gate electrode (16a) and the first insulating layer (15); a planar layer (18) covering the second insulating layer (17); a reflective electrode (19) covering the planar layer (18), the reflective electrode (19) being electrically connected with the drain electrode (14); normal projections of the drain electrode (14), the active layer (13) and the source electrode (12a) on the substrate (11) being arranged in a normal projection of the reflective electrode (19) on the substrate (11).

2. The array substrate of claim 1, wherein, A surface of the planar layer (18) matched with the reflective electrode (19) is provided with a first rough structure (181).

3. The array substrate of claim 1, wherein, A side of the reflective electrode (19) facing away from the planar layer (18) is provided with a second rough structure (191).

4. The array substrate according to claim 3, characterized in that, The second rough structure (191) is a plurality of convex parts, and the height of each convex part is 10000-15000 angstroms.

5. The array substrate according to any one of claims 1 to 3, wherein The material of the reflective electrode (19) is molybdenum or aluminum.

6. A reflective liquid crystal display panel, characterized by comprising: The reflective liquid crystal display panel further comprises a color film substrate opposite to the array substrate, and the color film substrate comprises a substrate (21), and a common electrode (22) is arranged on a side of the substrate (21) facing the array substrate.

7. A manufacturing method of an array substrate, characterized by, The manufacturing method comprises: providing a substrate (11); Forming a first metal layer on the substrate (11), etching and patterning the first metal layer to form a source electrode (12a) and a data line (12), the source electrode (12a) being electrically connected to the data line (12); Forming an oxide semiconductor layer on the source electrode (12a) and the substrate (11), etching and patterning the oxide semiconductor layer to form an active layer (13); Forming a second metal layer on the active layer (13), etching and patterning the second metal layer to form a drain electrode (14), the drain electrode (14) completely overlapping the active layer (13); The normal projection of the drain electrode (14) on the substrate at least partially overlaps the normal projection of the source electrode (12a) on the substrate, and the active layer (13) is located between the drain electrode (14) and the source electrode (12a) and is electrically connected to the drain electrode (14) and the source electrode; The active layer (13) includes a first connecting part (131) and a second connecting part (132) connected to the first connecting part (131), the first connecting part (131) is located above the source electrode (12a) and overlaps the source electrode (12a), and the normal projection of the first connecting part (131) on the substrate (11) is located within the normal projection of the source electrode (12a) on the substrate (11); the second connecting part (132) is located on the substrate (11) and is arranged side by side with the source electrode (12a); Forming a first insulating layer (15) covering the source electrode (12a), the active layer (13) and the drain electrode (14) on the substrate (11); Forming a third metal layer on the first insulating layer (15), etching and patterning the third metal layer to form a gate electrode (16a) and a scan line (16), the gate electrode (16a) and the scan line (16) being electrically connected; Forming a second insulating layer (17) covering the gate electrode (16a) on the first insulating layer (15); Forming a planar layer (18) on the second insulating layer (17); Forming a fourth metal layer on the planar layer (18), etching and patterning the fourth metal layer to form a reflective electrode (19), the reflective electrode (19) being electrically connected to the drain electrode (14); The normal projection of the drain electrode (14), the active layer (13) and the source electrode (12a) on the substrate (11) is located within the normal projection of the reflective electrode (19) on the substrate (11).

8. The method of manufacturing an array substrate according to claim 7, wherein The manufacturing method further comprises: When forming the planar layer (18) on the second insulating layer (17), a first rough structure (181) is formed on the surface of the planar layer (18) cooperating with the reflective electrode (19).

9. The method of manufacturing an array substrate according to claim 7, wherein The manufacturing method further comprises: Etching and patterning the fourth metal layer to form a reflective electrode (19) while forming a second rough structure (191) on the side of the reflective electrode (19) facing away from the planar layer (18).

10. The method of manufacturing an array substrate according to claim 7, wherein The manufacturing method further comprises: When etching and patterning the second metal layer to form a drain electrode (14), a dry etching process is used.

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