Statistical pattern determination

Abstract

Apparatus, methods of operating the apparatus and corresponding computer programs are disclosed. In the apparatus, an input circuit receives input data comprising at least one data element, and a shift circuit generates a bit map for each data element of the input data, the bit map giving a one-hot encoding representation of the data element, wherein the position of a set bit in the bit map depends on the data element. A summing circuit generates a position sum value for each position in the bit map, wherein each position sum value is a sum across all bit maps generated by the shift circuit from the input data. A maximum value identifying circuit determines at least one maximum position sum value generated by the summing circuit, and an output circuit for generating an indication of at least one data element corresponding to the at least one maximum position sum value. Thereby, a statistical pattern of the data elements in the input data is effectively determined.

Description

TECHNICAL FIELD

[0001] The present invention relates to data processing. More specifically, the present invention relates to determining a statistical pattern in a set of data values. DETAILED DESCRIPTION

[0002] There are a range of contexts in which it can be useful for a data processing apparatus to determine a statistical pattern (i.e. the most frequent element) in a set of data values. As just one example, in an apparatus implementing a machine learning classification model, a statistical pattern operation can be used to determine a final classification selection from a plurality of candidate classifications. Finding a statistical pattern in data values given by a set of input data elements in principle comprises three sub-operations. Firstly, a set of counts (or “histograms”) of data values is found by iterating over a list of elements and forming a list of histograms. Secondly, the highest count in the list of histograms, i.e. the maximum value count, is found. Finally, one or more elements with the maximum value count are selected as the statistical pattern. Typically, implementation of these steps is carried out over several processing cycles by saving intermediate results in sequential logic such as registers. However, there can be some contexts in which a statistical pattern should be computed but which can also be useful for data processing apparatuses with limited complexity, and in such contexts the high gate count required to provide registers can make their use disadvantageous. SUMMARY

[0003] In an example embodiment described herein there is provided an apparatus comprising: input circuitry to receive input data comprising at least one data element; shift circuitry to generate, for each data element of the input data, a bit map giving a one-hot encoding representation of the data element, wherein the position of a set bit in the bit map depends on the data element; sum circuitry to generate, for each position in the bit map, a position sum value, wherein each position sum value is a sum across all bit maps generated by the shift circuitry from the input data; maximum value identification circuitry to determine at least one maximum position sum value generated by the sum circuitry; and output circuitry to generate an indication of at least one data element corresponding to the at least one maximum position sum value.

[0004] In another example embodiment described herein there is provided a method of operating an apparatus, the method comprising: receiving input data comprising at least one data element; generating a bitmap for each data element of the input data, the bitmap giving a one-hot encoding representation of the data element, wherein the position of a set bit in the bitmap depends on the data element; generating a position sum value for each position in the bitmap, wherein each position sum value is a sum across all bitmaps generated from the input data; determining at least one maximum position sum value generated; and generating an indication of at least one data element corresponding to the at least one maximum position sum value.

[0005] In another example embodiment described herein there is provided a computer program for controlling a host data processing apparatus to provide an instruction execution environment, comprising: data processing logic for performing data processing operations, the data processing logic comprising: input logic for receiving input data comprising at least one data element; shift logic for generating a bitmap for each data element of the input data, the bitmap giving a one-hot encoding representation of the data element, wherein the position of a set bit in the bitmap depends on the data element; sum logic for generating a position sum value for each position in the bitmap, wherein each position sum value is a sum across all bitmaps generated from the input data by the shift logic; maximum value identification logic for determining at least one maximum position sum value generated by the sum logic; and output logic for generating an indication of at least one data element corresponding to the at least one maximum position sum value, instruction decoder logic for decoding instructions and generating control signals in dependence on the instructions to control the data processing logic to perform the data processing operations, wherein the instruction decoder logic generates control signals to control the input logic to receive the input data from a vector input register in response to a statistical pattern instruction specifying the vector input register. BRIEF DESCRIPTION OF DRAWINGS

[0006] The application will be further described, by way of example only, with reference to embodiments thereof as illustrated in the following drawings in which:

[0007] Figure 1 An apparatus in some example embodiments is schematically illustrated;

[0008] Figure 2 An apparatus employing a reduction tree to select between a plurality of sum values in some example embodiments is schematically illustrated;

[0009] Figure 3apparatus employing shifter circuitry to determine a maximum value among a plurality of summed values is schematically illustrated in some example embodiments;

[0010] Figure 4A and Figure 4B schematically illustrates further example embodiments generally corresponding to Figure 2 and Figure 3 schematically illustrates further example embodiments generally corresponding to

[0011] Figure 5A and Figure 5B schematically illustrates apparatus in some example embodiments in which when a maximum count of more than one identical value is determined, the output circuit can be selectively configured in a variety of different ways to select an output data element;

[0012] Figure 6 schematically illustrates data processing apparatus in some example embodiments arranged to perform data processing operations in response to a sequence of instructions, in which at least one of the instructions is a statistical mode determining instruction;

[0013] Figure 7A , Figure 7B and Figure 7C schematically illustrates in further detail statistical mode circuitry of apparatus in some example embodiments; Figure 6

[0014] Figure 8 is a flow diagram illustrating a sequence of steps taken by a method in accordance with some example embodiments; and

[0015] Figure 9 schematically illustrates an emulator implementation in some example embodiments.

[0016] Implementation of example embodiments

[0017] The following description of implementations is provided as an overview of some example embodiments and is not to be understood as being an exhaustive or complete description of the example embodiments.

[0018] ​According to one example configuration, there is provided an apparatus comprising: an input circuitry to receive input data comprising at least one data element; a shift circuitry to generate, for each data element of the input data, a bit map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit map depends on the data element; a sum circuitry to generate, for each position in the bit map, a position sum value, wherein each position sum value is a sum across all bit maps generated by the shift circuitry from the input data; a maximum value identification circuitry to determine at least one maximum position sum value generated by the sum circuitry; and an output circuitry to generate an indication of at least one data element corresponding to the at least one maximum position sum value.

[0019] The present technology proposes a method according to which a "one-hot" encoding representation of each data element in a set of input data received by an apparatus is generated using a shift circuitry, a statistical pattern is to be generated for the set of input data. These one-hot encodings not only can be relatively simply generated (e.g. by using a barrel shifter), but also represent a useful simple input for a sum circuitry to compute sum values across the set of one-hot encoding representations. In effect, this then generates a histogram count for the required set, the maximum of which can then be identified, thereby providing an indication of a statistical pattern in the input data elements, i.e. the data value that occurs most frequently in the set of input data. Thereby, an efficient but uncomplicated hardware mechanism for determining a statistical pattern in a set of input data is provided.

[0020] The maximum value identification circuitry can be provided in a number of ways to determine the at least one maximum position sum value (i.e. the highest histogram count or counts), but in some embodiments the maximum value identification circuitry comprises a reduction tree circuitry to perform a comparison and selection process on the position sum values generated by the sum circuitry, wherein the comparison and selection process reduces the position sum values generated by the sum circuitry to the maximum position sum value. This therefore enables the maximum position sum value to be identified amongst the position sum values generated by the sum circuitry in an efficient manner.

[0021] Based on the identified maximum position sum value (i.e. the highest histogram count), the output generated by the output circuit (i.e. the statistical pattern in the form of at least one data value from the values provided by the at least one data element in the input data set) can be performed in a variety of ways, but in some embodiments the output circuit comprises a comparator array for generating a pattern position map from a comparison between the maximum position sum value and the position sum values of each position in the bit map, wherein the output circuit is arranged to generate the indication of the at least one data element from the pattern position map. This thus supports an efficient identification of the position of the maximum position sum value in the set of position sum values, and on this basis the output circuit can thus identify the at least one data element for output.

[0022] The maximum value identification circuit can also be provided in other ways, and in particular in some embodiments can be based on more shift circuits. For example, in some embodiments the maximum value identification circuit comprises a further shift circuit for generating a further bit map for each position sum value, the further bit map giving a one-hot encoding representation of the position sum value, wherein the position of the set bit in the further bit map depends on the position sum value, and the output circuit is arranged to generate the indication of the at least one data element from all the further bit maps generated by the further shift circuit. Thus, a set of one-hot encoding representations is further used, where in this case the representation corresponds to the respective position sum value. This enables the use of the respective position of a single set bit ("one-hot") in the generated further bit maps in order to determine the final data value or values that should be provided at the output of the circuit.

[0023] In some embodiments the maximum value identification circuit further comprises a farthest set bit identification circuit for identifying the highest set bit position between all the further bit maps generated by the further shift circuit. Thus, the highest set bit position is indicative of the position sum value having the highest value.

[0024] The highest set bit position can then be converted into an identification of the highest sum value in a variety of ways. For example, in some embodiments the farthest set bit identification circuit comprises a logical disjunction circuit for each further bit map bit position, wherein the logical disjunction circuit is arranged to generate a pattern position map to indicate where the further bit maps generated by the maximum value identification circuit have a set bit located at the further bit map bit position. The logical disjunction circuit may, for example, be embodied as a set of OR gates.

[0025] In some embodiments the shift circuit is provided by a barrel shifter circuit.

[0026] In some embodiments the shift circuit comprises a one-hot decoding circuit.

[0027] In data elements received in the input data, the represented values can be such that more than one data element corresponds to a statistical pattern. In other words, the frequency of occurrence of more than one data value in the set of data elements can equal and exceed the frequency of other data values. In such cases, the apparatus, and in particular the output circuit of the apparatus, can respond in a number of different ways. For example, in some embodiments, the output circuit generates an indication of the more than one data element corresponding to the more than one maximum position sum value in response to the determination of the more than one maximum position sum value by the maximum value identification circuit. Thus, when such a case occurs, the output circuit can explicitly generate an indication of those multiple data elements that are each an equivalent statistical pattern representation of the represented values in the input data.

[0028] However, in other example embodiments, the output circuit can select between such equivalent data elements. The selection can be based on a predetermined order of the data elements of the input data. For example, in some embodiments, the data elements of the input data have a predetermined order, and wherein the output circuit selects an indication of the at least one data element corresponding to the highest order data element in the predetermined order in response to the determination of the more than one maximum position sum value by the maximum value identification circuit. In some embodiments, the output circuit selects an indication of the at least one data element corresponding to the lowest order data element in the predetermined order in response to the determination of the more than one maximum position sum value by the maximum value identification circuit. Thus, when the input data is provided by an input register, for example, the input register can be read from left to right or right to left to find the data element to be selected for output.

[0029] In further example embodiments, a random or pseudo-random selection can be made between equivalent candidates, and thus in such embodiments, the output circuit generates an indication of a randomly selected data element between the more than one data element corresponding to the more than one maximum position sum value in response to the determination of the more than one maximum position sum value by the maximum value identification circuit.

[0030] The data elements in the input data received by the apparatus can in principle represent an unlimited variety of data types, but the inventors of the present technology have found that the developed technology can be effectively utilized in a well-defined context, where the input data represents class indications and a statistical pattern determination is to be found among these indications, such that the output of the output circuit is an indication of at least one selected class. Thus, in some embodiments at least one data element in the input data received by the input circuit is a class indication, and the indication of at least one data element corresponding to the at least one maximum position sum value generated by the output circuit is an indication of at least one class. This can for example be the case in the context of a machine learning classification model for predicting a class, where the computation of the model generates a plurality of candidate classes, one candidate class is selected from these candidate classes, and the selection can be performed by a statistical pattern selection, i.e. the class that is most frequently indicated in a given set of input data.

[0031] One context in which the disclosed technology can be applicable is within the context of a data processing system arranged to perform data processing operations in response to data processing instructions. In instructions defined for such a data processing system, the present technology proposes that at least one statistical pattern instruction is defined to allow a programmer to invoke the operation of the above-described apparatus of the present technology in any of said forms. Thus, in some embodiments a data processing system is provided, comprising: data processing circuitry for performing data processing operations, the data processing circuitry comprising the above-described apparatus; instruction decoder circuitry for decoding instructions and generating control signals in accordance with the instructions to control the data processing circuitry to perform data processing operations, wherein the instruction decoder circuitry generates control signals to control the input circuitry to receive input data from a vector input register in response to a statistical pattern instruction specifying the vector input register.

[0032] The one or more statistical pattern instructions to which the instruction decoder circuitry is configured to respond can be defined differently, such that a statistical pattern is determined based on a plurality of different possible inputs, and further such that a plurality of different representations of the output are generated. Generally, however, the statistical pattern instruction specifies a vector input register, where the contents of the vector input register provide the input data, i.e. a set of data elements from which the statistical pattern is to be determined.

[0033] In some embodiments, the instruction decoder circuit generates control signals to control the output circuit in response to the statistical pattern instruction specifying a scalar output register such that an indication of the at least one data element corresponding to the at least one maximum position sum value is stored as a scalar value in the scalar output register. The scalar output register thus stores the result of executing the statistical pattern instruction, namely the pattern of data elements provided in the vector input register. The vector input register can be configured such that if multiple statistical pattern values are found, it provides the first pattern found (e.g. when considering the contents of the vector input register in a given order), or can select between them by any other method as described herein.

[0034] In some embodiments, the instruction decoder circuit generates control signals to control the input circuit in response to the statistical pattern instruction specifying a predicate map value to receive input data from the predicate map value from the vector input register. The predicate map value thus allows selection among the potential data elements considered in the vector input register to give those data elements that are considered to find the statistical pattern.

[0035] In some embodiments, the instruction decoder circuit generates control signals to control the output circuit in response to the statistical pattern instruction specifying a pattern map scalar output register such that an indication of the at least one data element corresponding to the at least one maximum position sum value is stored as at least one set bit in the pattern map value in the pattern map scalar output register. The pattern map scalar output register thus stores a bitmap, where the set bits of the bitmap point to all statistical patterns found in the data elements in the vector input register.

[0036] In some embodiments, the instruction decoder circuit generates control signals to control the output circuit in response to the statistical pattern instruction specifying a count scalar output register such that the maximum position sum value determined by the maximum value identification circuit is stored in the count scalar output register. The count scalar output register thus stores the histogram count of the pattern, namely the maximum position sum value that causes the output to select that statistical pattern.

[0037] In some embodiments, the instruction decoder circuit generates control signals to control the output circuit in response to the statistical pattern instruction specifying a count vector output register such that all position sum values generated by the sum circuit are stored in the count vector output register. The count vector output register thus serves to store all position sum values generated as part of the statistical pattern determination (i.e. all histogram counts).

[0038] In some embodiments, when more than one maximum position sum value is determined by the maximum value identification circuit, the instruction decoder circuit generates control signals to control the output circuit to generate an indication of a selected data element corresponding to the more than one maximum position sum value in response to the statistical mode instruction specifying a tie-breaker value. The selected data element is thus selected according to the tie-breaker value. The tie-breaker value can thus be set to define how to break a tie between more than one candidate mode. This tie-breaker value can for example be a 2-bit value, where if this value is 00, the tie is broken randomly; if it is 01, the tie is broken by selecting the first mode according to a predefined ordering of the data elements; and if it is 10, the tie is broken by selecting the first mode according to an inversion of the predefined ordering of the data elements. This is of course just one specific example, and many variations are possible.

[0039] In some embodiments, the instruction decoder circuit generates control signals to control the sum circuit to generate a position sum value for each position in the bit map that is weighted by a respective weight value in a weight vector register in response to the statistical mode instruction specifying the weight vector register. The weight vector register is thus a vector register storing data element weights, and thus not an equal vote for each data element. These weights can also be used to perform a weighted vote to be used in case a tie is required to be broken.

[0040] According to one exemplary configuration, there is provided a method of operating an apparatus, the method comprising: receiving input data comprising at least one data element; generating a bit map for each data element of the input data, the bit map giving a one-hot encoding representation of the data element, wherein a position in the bit map having a set bit depends on the data element; generating a position sum value for each position in the bit map, wherein each position sum value is a sum across all bit maps generated from the input data; determining at least one maximum position sum value of the generated position sum values; and generating an indication of at least one data element corresponding to the at least one maximum position sum value.

[0041] According to one example configuration, there is provided a computer program for controlling a host data processing apparatus to provide an instruction execution environment, comprising: data processing logic for performing data processing operations, the data processing logic comprising: input logic for receiving input data comprising at least one data element; shift logic for generating, for each data element of the input data, a bit map giving a one-hot encoding representation of the data element, wherein the position of a set bit in the bit map depends on the data element; summing logic for generating, for each position in the bit map, a position sum value, wherein each position sum value is a sum across all bit maps generated by the shift logic from the input data; maximum value identification logic for determining at least one maximum position sum value generated by the summing logic; and output logic for generating an indication of at least one data element corresponding to the at least one maximum position sum value; instruction decoder logic for decoding instructions and generating control signals to control the data processing logic to perform the data processing operations in accordance with the instructions, wherein the instruction decoder logic generates the control signals to control the input logic to receive the input data from a vector input register in response to the statistical mode instruction specifying the vector input register.

[0042] A specific embodiment will now be described with reference to the accompanying drawings.

[0043] Figure 1 An apparatus 10 in some example embodiments is schematically illustrated. In general, the apparatus 10 is arranged to receive input data comprising at least one data element and to determine, based on the input data, a statistical mode of a data value represented by the at least one data element. The statistical mode value forms an output of the apparatus. An input circuit 11 of the apparatus receives the input data and passes the set of data elements to a shift circuit 12. The shift circuit 12 operates independently on each data element to generate a "one-hot" encoding representation of that data element. To generate the representation, the particular configuration of the shift circuit can take a variety of forms but can be provided, for example, by a barrel shifter. It can also be provided by a conventional one-hot decoder which will be familiar to those of ordinary skill in the art, and so this variant is not explicitly shown for the sake of brevity. Taking the one-hot encoding representations of all the data elements in the input data as a set, this can be treated as a bit map 13, Figure 1 An example of this is illustrated in Figure 1. Thus, the first row of the bit map 13 corresponds to the leftmost data element of the input data (0), the second row of the bit map 13 corresponds to the second data element of the input data (3), the third row of the bit map corresponds to the third data element of the input data (2), and the last row of the bit map 13 corresponds to the rightmost data element of the input data (3). The bit map 13 is then received by a summing circuit 14 which generates a sum value for each position in the bit map, i.e. the sum of the values in the bit map at that position, and outputs a vector of sum values 15. Figure 1The representation shown is based on a column-by-column basis. For ease of understanding based on example values ​​in bitmap 13, an exemplary position summation value 15 is shown as an example. The maximum value identification circuit 16 then determines one or more maximum values ​​among the summations generated by the summing circuit 14. Therefore, the position (i.e., column) with the maximum number of entries in bitmap 13 is identified corresponding to a given data value in the data elements of the input data. Figure 1 In the example shown, based on the input data, the identified maximum value 17 is 2. The following discussion, with reference to the diagram below, illustrates an example where the maximum value identification circuit 16 identifies more than one equal maximum value. The identified maximum value is provided to the output circuit 18, which then uses this value to identify the corresponding data value, which is... Figure 3 The example shown is a value of 3. Therefore, this provides an output value of 19 from device 10.

[0044] Figure 2 The apparatus 30 in some exemplary embodiments is schematically shown. Input data 31 forming a set of data elements is received as input to the apparatus, and these data elements are passed to a shift circuit 32, which in this embodiment is provided as a set of barrel shifters. The barrel shifters of the shift circuit 32 operate independently of each data element of the input data, thereby shifting the setpoint to the position corresponding to the value of the respective data element. Thus, a bitmap 33 is generated from a set of one-hot encoded representations of the input data elements. A set of summing circuits 41 is provided, which is connected to the output of the shift circuit, such that for each position in the bitmap (i.e., Figure 2 The columns shown in the representation are summed. This can be embodied, for example, as a "population counting" operation. For the exemplary value being processed, the resulting positional summation value 34 is in Figure 2 As shown in the diagram. The positional sums are provided as input to the reduction tree 35, which compares these values ​​to determine the maximum value among these positional sums. Figure 2 In the example shown, the maximum value is 2. The identified maximum value 36 is then provided as input to a set of comparators 37. This set of position sums 34 provides a corresponding input to each of these comparators, enabling the location where the maximum value 36 is generated to be found. The output of the comparators 37 thus provides an indication of the data value for which the maximum value was found. This indication, in the form of a binary mode position map 38, is used to generate the final output value. In the illustrated implementation, the binary mode position map 38 is combined with the position map of the data value 39 via the output circuit 40 to achieve this, but it should be noted that the use of position map 39 is not always necessary. For example, the bit index of the set bit in register 38 will automatically give the statistical mode value. In the example shown, the bit index of the set bit is 4, which is the statistical mode. In other words, the statistical mode can be derived directly in the output circuit 40.

[0045] Figure 3 The apparatus 50 in some exemplary embodiments is illustrated schematically. Similar to... Figure 2 In the example shown, the input circuitry of device 50 receives input data provided with a set of data elements 51. Shift circuit 52 (in the same manner as described above for shift circuit 32 of device 30) generates a one-hot encoded representation of each input data element that together forms a bitmap. Summation circuit 53 (which, as in...) Figure 2 As in the example, and the summing circuit 41 can be provided as a population counting array operation) to generate a summation value corresponding to each position in the one-hot encoded representation, i.e., corresponding to Figure 3 The columns in the array generate a set of positional sum values ​​54. This set of values ​​is then fed into a shift circuit 55, which converts each value into a one-hot encoded representation of each value in a manner similar to that of shift circuit 52. Thus, observing together the one-hot encoded representation provides another bitmap, and the rows of this bitmap (in the array)... Figure 3 The input is then provided to a set of gates 56. Generally, this set of gates 56 provides a logic disconnect function to determine whether any bit in a given row (i.e., bit position) is set. Figure 3 In an exemplary implementation, it is a set of OR gates. Therefore, a bitmap representation 57 of the generated position is produced. Then, the bit corresponding to the “farthest” position of the bit set in the one-hot encoded representation of the position summation is selected, thereby identifying the generated maximum summation value. This controls a multiplexer 58, to which the bitmap representation generated by the shift circuit 55 provides another input, and thus the correspondingly selected row is provided as output 59. Therefore, this output indicates the position of the statistical pattern data value, and combined with the position mapping 60, the output circuit can thus generate the statistical pattern data value of output 62, which is in Figure 3 The example value is 4. (Compared to...) Figure 2 The situation is the same, although in Figure 3 In the illustrated implementation, binary mode position mapping 59 is combined with data value position mapping 60 via output circuit 61; however, it should be noted that the use of position mapping 60 is not always necessary. For example, the bit index of the set bit in register 59 will automatically give the statistical mode value. In the illustrated example, the bit index of the set bit is 4, which is the statistical mode.

[0046] The present techniques can be applied in a wide variety of contexts, and so the data values in the data elements of the input data to the apparatus are not limited to what they can represent. However, one particular context in which the determination of statistical patterns in a set of data values can be used is in the classification model used by the apparatus in order to provide a class prediction for a data group represented by a particular set of data values. For example, in a variety of machine learning (ML) techniques, the statistical pattern operation can be employed in a final stage to select between candidate classifications, and so can provide a final class prediction generated by a trained model. Figure 4A and Figure 4B The operation of two example apparatuses is schematically illustrated, which are arranged to receive a set of data values and generate an output based on these data values, which is a class prediction according to a classification model. In Figure 4A , the set of data values 70 provides the input data received by the shift circuit. The shift circuit performs a separate shift operation on each data value to form a one-hot encoded representation, such that a bit map 71 is generated corresponding to the input data. This bit map representation 71 is fed into a population count array operation 72, which sums over the respective one-hot encoded positions (i.e., columns in the representation of Figure 4A ) to generate a histogram count corresponding to each of the class values represented in the input data. The histogram counts are received by a maximum value reduction tree circuit 73, such that the histogram counts are reduced to a single value corresponding to the highest histogram count generated. A comparator array 74 compares this maximum value to the histogram counts to generate a mode position map, which indicates the position of the maximum value within the histogram counts, i.e., also corresponding to the position of the respective possible classification. Finally, a selection circuit 75 selects the corresponding mode based on the mode position map, and indicates this as the output class prediction, which in the example given (for illustrative purposes only, in Figure 4A ) is class 4.

[0047] An alternative approach for determining a statistical pattern in input class values is illustrated for the example of Figure 4B , in which a set of class values 80 forms the input set of data elements providing the input data to the apparatus. As in Figure 4A , a shift circuit 81 operates on these data values, converting each data value into a one-hot encoded representation, such that together a bit map 81 is generated in which the position of the set bit in the bit map represents the corresponding value of the input class value. The bit map 81 provides input to a population count array 82, which sums over the one-hot encoded representation of each data element (i.e., the columns in the representation of Figure 4Beach possible position in the column of the representation to generate a set of histogram counts corresponding to each possible class. This set of histogram counts provides input to a further shift circuit which operates on each individual histogram count to generate a one-hot encoded representation of that count such that a bitmap 83 is generated overall. The inputs of a set of OR gates 84 are provided by respective rows of this bitmap such that the output of an OR gate indicates whether at least one bit is set in a given row. On this basis, the furthest row with an OR = 1 output is selected by the circuit 84 and an indication of this row is passed to a selection circuit 85 which can thus identify the selected class to be output as the pattern. In Figure 4B the example, which is class 4.

[0048] As mentioned above, for a given set of input data, it should be appreciated that a situation can arise in which more than one statistical pattern of data values can be identified. Figure 5A An apparatus 100 arranged accordingly is shown schematically. It can be seen that the input data 101 comprises a set of data elements whose values enable two statistical pattern values to be identified, namely 4 and 2. The input data 101 is processed by a circuit 102 which represents the input circuit, shift circuit, summing circuit and maximum value identification circuit discussed herein in any of its variants. The maximum value identification circuit thus generates a pattern position map 103 in which two positions are indicated by set bits. This pattern position map 103 is then received by an output circuit 104. The output circuit 104 can be variously configured to affect the manner in which it responds to a situation in which more than one pattern value is identified. This control is exerted on the output control circuit 104 by a “multiple pattern control” signal and / or a “random” control input. Based on the control signal, the output circuit 104 can generate Figure 5A one of three different types of output labelled (a) to (c) in Figure 1. Case (a) corresponds to a configuration according to which the output circuit 104 is configured to output both pattern values as its output 105. Alternatively, the output circuit 104 can be configured such that it selects between the multiple patterns so as to output only one statistical pattern value. Case (b) corresponds to one possible output 106, while case (c) corresponds to an alternative output 107. One way in which the output circuit 104 can select between is randomly (or pseudo-randomly), and can accordingly produce the output 106 or 107. Alternatively, the output circuit 104 can be configured to process the multiple patterns according to a predefined ordering of the patterns and select between them based on this ordering. For example, treating the data values as a decreasing sequence of values and selecting the first pattern value according to the decreasing sequence encountered, the output circuit 104 will output the first pattern value in case (b) and the second pattern value in case (c). Figure 5AThe example values shown select statistical mode = 4. Conversely, reversing the order of the selection sequence would cause the output circuit 104 to select statistical mode = 2 as the output. As a further alternative, the output circuit 104 can revert to considering the input data 101 in the format originally provided (e.g. referring to the vector register in which these values are stored) and select the output mode based on the first statistical mode value seen when reading from the left (i.e. mode = 4) or by picking the first mode value seen when reading from the right (i.e. mode = 2).

[0049] Figure 5B The circuit forming part of the apparatus in one example embodiment is shown schematically. From this circuit, control of the selection between the plurality of statistical modes is provided by a tie-break value 110. This tie-break value 110 provides one input to a final mode selection circuit 111. As with the mode position map 103, the input data 102 forms a further input to the final mode selection circuit 111. On this basis, in the case where the mode position map indicates two concurrent maximum values (corresponding to classes 4 and 2), the final mode selection circuit 111 is controlled by the tie-break value 110 in order to determine a single class to indicate as the statistical mode. In this example, the tie-break value is a two-bit value, where when it has the value 00, the tie is broken randomly. When it has the value Ol, the tie is broken by picking the first mode seen from the left in the input data values 102. When the tie-break value is 10, the tie is broken by picking the first mode seen from the right.

[0050] Figure 6 A data processing apparatus 150 embodying various examples of the present technology is shown schematically. The apparatus comprises data processing circuitry 151 which performs data processing operations on data items in response to sequences of instructions executed thereby. These instructions are retrieved from a memory 152 accessible to the data processing apparatus and extraction circuitry 153 is provided for this purpose in a manner familiar to those of ordinary skill in the art. Furthermore, instructions retrieved by the extraction circuitry 153 are passed to instruction decoder circuitry 154 which generates control signals arranged to control various aspects of the configuration and operation of the processing circuitry 151 as well as the register file 155. Generally, the data processing circuitry 151 can be arranged in a pipelined manner, but the specifics thereof are not germane to the present technology. Those of ordinary skill in the art will be familiar with the general configuration represented and further detailed explanation and description thereof is omitted here for the sake of brevity. Figure 6 The register file 155 includes both vector registers 156 and scalar registers 157 so that the data processing circuitry 151 can perform both vector and scalar data processing operations. The data processing circuitry 151 includes execution circuitry 158 which can be arranged in a pipelined manner as described above. Figure 6A particular part of the illustrated data processing circuit 151 is a statistical mode determination circuit 159, which can be arranged in accordance with any of the example embodiments described herein or variations thereof. Thus, generally, data values are retrieved from memory 152 to be temporarily held in registers 155, where they can be the subject of data processing operations, possibly modified, and written back to memory 152 if appropriate. The present technology provides for the data processing apparatus 150 to be responsive to at least one statistical mode operation which, when decoded by the decode circuit 154, causes the statistical mode determination circuit 159 in the data processing circuit 151 to be used in order to determine a statistical mode in data values represented by the contents of one or more specified registers 155. Note also that, Figure 6 The memory 152 in the data processing apparatus 150 generally can be seen as an example of a computer readable storage medium on which instructions of the present technology can be stored, typically as part of a predefined sequence of instructions (‘program’) for subsequent execution by the processing circuitry. However, such programs can be accessed by the processing circuitry from various different sources, such as stored in RAM, in ROM, via a network interface, etc.

[0051] Figure 7A , Figure 7B and Figure 7C An embodiment of the statistical mode circuit 159 provided when the data processing apparatus 150 is responsive to various forms of statistical mode (‘SMODE’) instructions is illustrated schematically. One such instruction has the following form:

[0052] SMODE Single_Mode_Reg, SIMD_Input_Reg

[0053] where the SIMD_Input_Reg is a vector input register (such as the input register 160) and the Single_Mode_Reg is a scalar output register (such as the output register 161) for the mode of the result, i.e. the data element. The statistical mode circuit 159 can be arranged so that when multiple modes are found, the first mode found is given.

[0054] Another SMODE instruction to which the statistical mode circuit 159 is responsive has the following form:

[0055] SMODE Single_Mode_Reg, Predicate_Map, SIMD_Input_Reg

[0056] where the SIMD_Input_Reg and Single_Mode_Reg are as described above, and the Predicate_Map is a map 162 that selects the input values in the SIMD register that are considered to be input values for which a statistical mode is found.

[0057] Another SMODE instruction to which the statistical mode circuit 159 responds has the following form:

[0058] SMODE ModeMap_Reg, SIMD_Input_Reg

[0059] where SIMD_Input_Reg is as described above, and ModeMap_Reg is a scalar output register (such as output register 163) and stores a bitmap of pointers to all modes in the data element, rather than finding a single mode.

[0060] The above variants of the SMODE instruction can be combined in a further SMODE to which the statistical mode circuit 159 responds, which has the following form:

[0061] SMODE ModeMap_Reg, Predicate_Map, SIMD_Input_Reg

[0062] where SIMD_Input_Reg, Predicate_Map, and ModeMap_Reg are as described above.

[0063] Referring now to Figure 7B but note that the same statistical mode circuit 159 is shown, indicating that one embodiment of the statistical mode circuit can respond to all of the SMODE instructions described herein. Figure 7A , Figure 7B and Figure 7C are separated only for clarity of illustration and discussion.

[0064] Another SMODE instruction to which the statistical mode circuit 159 responds has the following form:

[0065] SMODE Single_Mode_Reg, Count_Reg, SIMD_Input_Reg

[0066] where SIMD_Input_Reg and Single_Mode_Reg are as described above, and Count_Reg is a scalar output register (such as 164 in Figure 7B ) that stores a histogram count of the statistical mode. The histogram count circuit 165 and the mode selection circuit 166 of the statistical mode circuit 159 provide this value.

[0067] Another SMODE instruction to which the statistical mode circuit 159 responds has the following form:

[0068] SMODE ModeMap_Reg, Count_Reg, SIMD_Input_Reg

[0069] where SIMD_Input_Reg and ModeMap_Reg are as described above, and Count_Reg is a scalar output register (such as 164 in Figure 7B and stores the histogram count for the mode in the data element.

[0070] Another SMODE instruction to which the statistical mode circuit 159 responds has the following form:

[0071] SMODE ModeMap_Reg, All_Count_Reg, SIMD_Input_Reg

[0072] where SIMD_Input_Reg and ModeMap_Reg are as described above, and All_Count_Reg is a vector output register (such as 167 in Figure 7B and stores the histogram counts for all data elements.

[0073] Another SMODE instruction to which the statistical mode circuit 159 responds has the following form:

[0074] SMODE Single_Mode_Reg, (Predicate_Map), SIMD_Input_Reg, Tie_BreakerBitMap

[0075] where Single_Mode_Reg, Predicate_Map, and SIMD_Input_Reg are as described above, and Tie_BreakerBitMap is a bit map value (e.g., a 2-bit value) that can be given explicitly in the instruction or can be fetched from a storage location 168 as shown in Figure 7B If there is more than one statistical mode, the value of Tie_Breaker_BitMap determines how the statistical mode circuit 159 breaks the tie. When the value is 00, the tie is broken randomly. When it is 01, the tie is broken by picking the first statistical mode seen from the left in the SIMD_Input_Reg. When it is 10, the tie is broken by picking the first statistical mode seen from the right in the SIMD_Input_Reg.

[0076] See finally Figure 7C (and again review Figure 7A , Figure 7B and Figure 7C(The examples are separated for clarity of illustration and discussion only), another SMODE command that the statistical mode circuit 159 responds to has the following form:

[0077] SMODE Single_Mode_Reg, (Predicate_Map), SIMD_Input_Reg, Weight_Input_Reg

[0078] The Single_Mode_Reg, Predicate_Map, and SIMD_Input_Reg are as described above, and Weight_Input_Reg is a vector register (such as 170) that stores the weights of the data values. Here, instead of voting equally for each data value, the instruction assigns a weight to each data value. For example, in the histogram count generated for each data value, the calculated histogram count can be scaled by the weights provided by Weight_Input_Reg for each data value. This method can also be used to break ties.

[0079] Figure 8 This is a flowchart illustrating a sequence of steps taken according to a method based on some exemplary embodiments. At step 200, input data specifying at least one data element is received. Then... Figure 8 The process of iterating relative to the data elements in the input data includes steps 201 and 202, which generate a one-hot representation of the data value represented by each data element. Therefore, according to Figure 8 The process, at step 201, determines whether there is another data element to be processed into this format, and when there is a process proceeding via step 202, generates a one-hot representation for that data element in that step, where a single set bit is shifted depending on multiple positions of the value represented by the data element. It should be understood that in Figure 8 The sequential processing of data elements representing the input data is for clarity of discussion only, and the technique is not limited to specific implementations in which such serial generation of one-hot representations is performed. In practice, in many implementations, shift circuitry may be provided for each data element of the input data, such that these one-hot representations are generated in parallel with each other. However, once this stage is complete, the process proceeds to step 203, in which a sum is generated for each bit position in the one-hot representation. At step 204, it is then determined which sum is the largest (or if multiple equivalent maximum sums exist), and finally, at step 205, at least one maximum sum is used to determine at least one data value represented in the input data for use as the output.

[0080] Figure 9Embodiments of simulators that can be used are shown. While the previously described embodiments implement the application in terms of apparatus and methods for operating specific processing hardware that support the technology involved, it is also possible to provide an instruction execution environment in accordance with the embodiments described herein that is implemented through the use of a computer program. Such computer programs are often referred to as simulators, in part because they provide a software-based implementation of a hardware architecture. Categories of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. In general, a simulator implementation can run on a host processor 330 that supports the simulator program 310, which optionally runs a host operating system 320. In some arrangements, there can be multiple simulation layers between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide a simulator implementation that executes at a reasonable speed, but such an approach can be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or re-use reasons. For example, a simulator implementation can provide an instruction execution environment with additional functionality that is not supported by the host processor hardware, or provide an instruction execution environment that is normally associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0081] To the extent that the previously described embodiments have been described with reference to specific hardware configurations or features, in a simulated embodiment, equivalent functionality can be provided by suitable software configurations or features. For example, a particular circuit can be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware such as registers or cache memory can be implemented as software data structures in a simulated embodiment. To the extent that one or more of the hardware elements referenced in the previously described embodiments exist on host hardware (e.g., host processor 330), some simulated embodiments can make use of the host hardware, where appropriate.

[0082] The emulator program 310 can be stored on a computer readable storage medium, which can be a non-transitory medium, and provides a program interface (instruction execution environment) to the object code 300 that is identical to the application program interface of the hardware architecture that the emulator program 310 is modeling. Thus, program instructions of the object code 300, including the statistical mode instructions described above, can be executed from within the instruction execution environment using the emulator program 310, such that a host computer 330 that does not actually have the hardware features of the apparatus 10 described above can emulate these features.

[0083] In short, the invention discloses an apparatus, a method of operating the apparatus and a corresponding computer program. In the apparatus, an input circuit receives input data comprising at least one data element, and a shift circuit generates a bit map for each data element of the input data, the bit map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit map depends on the data element. A summing circuit generates a position sum value for each position in the bit map, wherein each position sum value is a sum across all bit maps generated by the shift circuit from the input data. A maximum value identifying circuit determines at least one maximum position sum value generated by the summing circuit, and an output circuit for generating an indication of at least one data element corresponding to the at least one maximum position sum value. Thereby, a statistical mode of the data elements in the input data is effectively determined.

[0084] In this application, the word "configured" is used to mean that an element of the apparatus has the capability to carry out a defined operation. In this context, a "configuration" means an arrangement or manner of interconnection of hardware or software. For example, the apparatus can have dedicated hardware which provides the defined operation, or a processor or other processing device can be programmed to perform the function. "Configured" does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation.

[0085] While the exemplary embodiments of the invention have been described in detail hereinabove, it is to be understood that the invention is not limited to the precise embodiments, and as such, various modifications and changes can be made by those skilled in the art without departing from the scope of the present invention which is set forth in the appended claims. For example, features of dependent claims can be combined with features of the independent claims in various combinations without departing from the scope of the present invention.

Claims

1. A data processing apparatus comprising: an input circuit for receiving input data comprising at least one data element; a shift circuit for generating, for each data element of the input data, a bit map giving a one-hot encoding representation of the data element, wherein the position of a set bit in the bit map depends on the data element; a summing circuit for generating, for each position in the bit map, a position sum value, wherein each position sum value is a sum across all bit maps generated by the shift circuit from the input data; a maximum value identification circuit for determining at least one maximum position sum value generated by the summing circuit; and an output circuit for generating an indication of at least one data element corresponding to the at least one maximum position sum value.

2. The apparatus of claim 1, wherein the maximum value identification circuit comprises a reduction tree circuit for performing a comparison and selection process on the position sum values generated by the summing circuit, wherein the comparison and selection process reduces the position sum values generated by the summing circuit to a maximum position sum value.

3. The apparatus of claim 2, wherein the output circuit comprises a comparator array for generating a pattern position map from a comparison between the maximum position sum value and the position sum values for each position in the bit map, wherein the output circuit is arranged to generate the indication of the at least one data element from the pattern position map.

4. The apparatus of any one of claims 1 to 3, wherein the maximum value identification circuit comprises a further shift circuit for generating, for each position sum value, a further bit map giving a one-hot encoding representation of the position sum value, wherein the position of a set bit in the further bit map depends on the position sum value, and the output circuit is arranged to generate the indication of the at least one data element from all further bit maps generated by the further shift circuit.

5. The apparatus of claim 4, wherein the maximum value identification circuit further comprises a furthest set bit identification circuit for identifying a highest set bit position between all further bit maps generated by the further shift circuit.

6. The apparatus of claim 5, wherein the furthest set bit identification circuit comprises a logical disjunction circuit for each further bit map bit position, wherein the logical disjunction circuit is arranged to generate a pattern position map to indicate where the further bit maps generated by the maximum value identification circuit have a set bit located at the further bit map bit position.

7. The apparatus of any one of claims 1 to 3, wherein the shift circuit comprises a barrel shifter circuit.

8. The apparatus of any one of claims 1 to 3, wherein the shift circuit comprises a one-hot decoding circuit. ​ 9. The apparatus of any one of claims 1-3, wherein the output circuit generates an indication of more than one data element corresponding to more than one maximum position sum value in response to a determination of the more than one maximum position sum value by the maximum value identification circuit.

10. The apparatus of any one of claims 1-3, wherein data elements of the input data have a predetermined order, and wherein the output circuit selects the indication of the at least one data element corresponding to a highest order data element in the predetermined order in response to a determination of more than one maximum position sum value by the maximum value identification circuit.

11. The apparatus of any one of claims 1-3, wherein data elements of the input data have a predetermined order, and wherein the output circuit selects the indication of the at least one data element corresponding to a lowest order data element in the predetermined order in response to a determination of more than one maximum position sum value by the maximum value identification circuit.

12. The apparatus of any one of claims 1-3, wherein the output circuit generates an indication of a randomly selected data element between more than one data element corresponding to more than one maximum position sum value in response to a determination of the more than one maximum position sum value by the maximum value identification circuit.

13. The apparatus of any one of claims 1-3, wherein the at least one data element in the input data received by the input circuit is a class or category indication, and the indication of the at least one data element corresponding to the at least one maximum position sum value generated by the output circuit is an indication of at least one class or category.

14. A data processing system comprising: a data processing circuit for performing data processing operations, the data processing circuit comprising an apparatus according to any one of claims 1-13; an instruction decoder circuit for decoding instructions and generating control signals in accordance with the instructions to control the data processing circuit to perform the data processing operations, wherein the instruction decoder circuit generates control signals to control the input circuit to receive the input data from a vector input register in response to a statistical pattern instruction specifying the vector input register.

15. The data processing system of claim 14, wherein the instruction decoder circuit generates control signals to control the output circuit such that the indication of the at least one data element corresponding to the at least one maximum position sum value is stored as a scalar value in a scalar output register in response to the statistical pattern instruction specifying the scalar output register.

16. The data processing system of claim 14, wherein the instruction decoder circuit generates control signals to control the input circuit to receive the input data in accordance with a predicate map value from the vector input register in response to the statistical pattern instruction specifying the predicate map value.

17. The data processing system of claim 14, wherein the instruction decoder circuit generates control signals to control the output circuit in response to the statistical pattern instruction specifying a mode mapping scalar output register, such that the indication of the at least one data element corresponding to the at least one maximum position sum value is stored as at least one set bit in a mode mapping value in the mode mapping scalar output register.

18. The data processing system of claim 14, wherein the instruction decoder circuit generates control signals to control the output circuit in response to the statistical pattern instruction specifying a count scalar output register, such that the maximum position sum value determined by the maximum value identification circuit is stored in the count scalar output register.

19. The data processing system of claim 14, wherein the instruction decoder circuit generates control signals to control the output circuit in response to the statistical pattern instruction specifying a count vector output register, such that all position sum values generated by the sum circuit are stored in the count vector output register.

20. The data processing system of any one of claims 14 to 19, wherein when more than one maximum position sum value is determined by the maximum value identification circuit, the instruction decoder circuit generates control signals to control the output circuit to generate an indication of a selected data element corresponding to the more than one maximum position sum value in response to the statistical pattern instruction specifying a tie-breaking value, wherein the selected data element is selected according to the tie-breaking value.

21. The data processing system of any one of claims 14 to 19, wherein the instruction decoder circuit generates control signals to control the sum circuit to generate the position sum value for each position in the bit map weighted by a respective weight value in a weight vector register in response to the statistical pattern instruction specifying a weight vector register.

22. A method of operating a data processing apparatus, comprising: receiving input data comprising at least one data element using an input circuit; generating a bit map for each data element of the input data using a shift circuit, the bit map giving a one-hot encoding representation of the data element, wherein set bits in the bit map depend on the data element; generating a position sum value for each position in the bit map using a sum circuit, wherein each position sum value is a sum across all bit maps generated from the input data; determining at least one maximum position sum value generated using a maximum value identification circuit; and generating an indication of at least one data element corresponding to the at least one maximum position sum value using an output circuit. The computer executable instructions, when executed by a host data processing apparatus, cause the host data processing apparatus to perform the method of claim 22.

23. A computer program product comprising computer-executable instructions, wherein, ​

Images