Standard cell layout generation using artificial intelligence

Abstract

Standard cell layout generation using artificial intelligence is disclosed. A genetic algorithm is used to generate routing candidates, to which a reinforcement learning model is applied to incrementally correct design rule constraint violations. A design rule checker provides feedback to the reinforcement learning model about violations, and the model learns how to fix the violations. A placement placer based on a simulated annealing method can also be utilized.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of U.S. Application No. 63 / 055753, filed July 23, 2020, entitled “Standard Cell Routing in Advanced Technology Nodes with Reinforcement Learning and Genetic Algorithms,” and U.S. Application No. 63 / 090037, filed October 9, 2020, entitled “Generating Standard Cell Layouts in Advanced Technology Nodes with Reinforcement Learning,” the contents of each of which are incorporated herein by reference in their entirety. BACKGROUND

[0003] A technology node is a particular semiconductor manufacturing process and its design rules. Generating a logic cell layout in an advanced technology node is challenging, due in part to the exploding number and complexity of design rule constraints (DRCs), especially when the design goal is to minimize the cell area. Different technology nodes often utilize different circuit generations and architectures in the cell library. In general, the more advanced the technology node, the smaller the feature size, resulting in smaller and more power efficient transistors.

[0004] Prior methods of cell generation layout in advanced technology nodes utilize mathematical optimization methods, such as satisfiability problems (SAT) and mixed integer programming (MILP), to identify solutions under those constraints. These mathematical optimization methods rely on manual expression of the design rules within the optimization framework and computational solvers.

[0005] Certain logic cells, known as “standard cells,” are used as building blocks for advanced technology node layouts. Such layouts can be constructed from a very large number of instances of standard cells. Semiconductor companies and intellectual property providers can have teams that design standard cell libraries specifically for a technology node. Each library can include thousands of standard cells. One cell design goal is to minimize the cell width (the cell height can be fixed within each library) to improve area efficiency.

[0006] Today, most industrial standard cell design is performed manually. Automated standard cell layout can not only speed up the design process, but enable design and technology co-optimization (DTCO), which simultaneously optimizes the standard cells and the chip design for better performance.

[0007] Standard cell layout design automation includes two main operations: placement and routing. Placement positions the devices and assigns pin locations in the layout. Routing connects the device terminals and pins based on network connectivity. Routing tends to be the more challenging of the two operations, as routing needs to satisfy a configured set of DRCs (often very large).

[0008] At advanced technology nodes, not only does the number of DRCs greatly expand, but the DRCs tend to be more complex. Much of the new complexity comes from DRCs involving multiple layout shapes that were previously independent of each other. SAT and MILP based mathematical optimization methods rely on the assumption that all design rule constraints can be expressed in the form of conjunctive normal form such as SAT or linear inequalities of MILP. It is challenging or impossible to express all DRCs in these forms effectively. A large number of constraints are needed to handle all DRCs, which makes it difficult to scale to larger designs. Furthermore, these constraints often need to be redrafted manually for each new technology node or standard cell layout template.

[0009] Existing placement techniques include heuristic based methods, exhaustive search based methods, and mathematical programming based methods. Heuristic based methods first find all possible chains in the circuit, i.e., devices that can share diffusion continuously, and then select multiple chains that cover all devices. Exhaustive search based methods go through all possible device placement configurations, and can use branch and bound or dynamic programming techniques to speed up the search process. Mathematical programming based methods utilize MILP or SAT algorithms to find the optimal device placement. It has been shown that these placement techniques can generate good placement solutions.

[0010] Existing routing techniques include signal based routing, SAT, and MILP based routing methods. Common deterministic signal based routing methods, such as LEA, Dogleg, Greedy, YACR2, etc., can only generate specific routing solutions and cannot handle DRCs well. SAT based routing creates candidate routes for each terminal pair and utilizes SAT to find feasible routing candidates for all terminal pairs. It requires DRC checks to prune all conflicting routing candidates. The quality of routing candidates also limits the final routing quality. Therefore, these techniques often cannot find routing solutions for complex cells.

[0011] MILP based routing methods formulate the routing problem as a mixed integer linear programming problem. However, these methods rely on MILP solvers to solve a large number of constraints and require DRCs to be expressed in the form of conditional equations or inequalities. This makes it difficult to support newer technology nodes. A common approach uses a combination of MILP and rip-up and reroute techniques for routing, which has similar problems as previously mentioned.

[0012] A common approach to routing problems with reinforcement learning creates routing direction actions, i.e., go north, go south, etc., at each step. Another approach uses an attention model based REINFORCE algorithm to select routing order and once the routing order is determined, a pattern router is used to generate the actual routes. Yet another approach uses Monte Carlo Tree Search (MCTS) and deep neural network based steering actions to find routes. Most of these approaches are limited to connecting routes without considering design rule violations. These approaches are not easily extended to handle DRC for complex circuit and / or standard cell routing domains. BRIEF DESCRIPTION OF DRAWINGS

[0013] For ease of reference to any particular element or action, the most significant digit or digits of the reference number refer to the figure number in which that element was first introduced.

[0014] Figure 1A A bar graph depicting embodiments of a standard latch cell.

[0015] Figure 1B A DRC conformal metal layout for double patterning is depicted.

[0016] Figure 1C A DRC violating metal layout for double patterning is depicted.

[0017] Figure 2A An exemplary routing layout generated by a genetic algorithm configured by DRC is depicted.

[0018] Figure 2B A routing layout after applying DRC fixes by a reinforcement learning algorithm is depicted. Figure 2A A routing layout after applying DRC fixes by a reinforcement learning algorithm is depicted.

[0019] Figure 3 A circuit layout router 300 according to one embodiment is depicted.

[0020] Figure 4 An incremental routing process 400 for advanced technology nodes in one embodiment is depicted.

[0021] Figure 5 A simulated annealing placement convention 500 according to one embodiment is depicted.

[0022] Figure 6 A genetic routing algorithm 600 according to one embodiment is depicted.

[0023] Figure 7 A reinforcement learning artificial neural network 700 for DRC correction according to one embodiment is depicted.

[0024] Figure 8A parallel processing unit 802a is depicted in accordance with one embodiment.

[0025] Figure 9 A general processing cluster 900 is depicted in accordance with one embodiment.

[0026] Figure 10 A memory partition unit 1000 is depicted in accordance with one embodiment.

[0027] Figure 11 A streaming multiprocessor 1100 is depicted in accordance with one embodiment.

[0028] Figure 12 A processing system 1200 is depicted in accordance with one embodiment.

[0029] Figure 13 An exemplary processing system 1300 is depicted in accordance with another embodiment.

[0030] Figure 14 A graphics processing pipeline 1400 is depicted in accordance with one embodiment. DETAILED DESCRIPTION

[0031] Techniques are disclosed for applying reinforcement learning (RL) in a manner that avoids explicit formulation of DRCs during circuit routing. The constraints are enforced by a reward given in an environment where DRC analysis is performed independently of routing optimization. Conventional approaches seek to apply reinforcement learning directly to the routing problem, i.e., such that the reinforcement learning agent generates routing actions for each wire, where the action space is routing actions (north, south, west, east) for each net of the layout. The disclosed techniques learn how to fix DRCs on existing routes, rather than having the RL agent learn the job of the maze router. The routing problem is decomposed into two independent steps: routing and DRC fixing. DRC fixing is configured through reinforcement learning and scaling to large designs, as DRC problems tend to be local, while routing can exploit global information, especially for long routes.

[0032] In one embodiment, the automated layout generator includes a simulated annealing based algorithm for device placement and pin assignment. Device pairing and placement can be performed in parallel. A genetic algorithm based routing flow is used to identify minimal routes and reduce the likelihood of DRC errors. Reinforcement learning is applied to fix DRC errors in the generated routes. The resulting model can be transferred to other cells. The model can be further retrained on each cell to improve results.

[0033] In some embodiments, routing can be performed in two steps: (1) a genetic algorithm-based routing step, and (2) a DRC fixing step based on RL. The genetic algorithm drives the maze router to create a set of routing candidates, and the DRC RL agent reduces the number of DRCs for a given routing candidate. The DRC RL agent can, for example, fix the M1 layer DRC errors, and in some embodiments can focus only on errors in that layer. M1 is the lowest routing layer that typically includes the most difficult DRC problems. Other DRC errors can be corrected during maze routing. The RL‘game’ can be configured to incrementally add additional M1 routing segments to reduce M1 DRCs. The observation space of the game can include paths in M1, DRC locations, and a routing mask.

[0034] The action space can be set to the M1 grid that will be routed in the next iteration. The reward of the game can be configured to include a small negative reward given at each step and a large positive reward associated with DRC reduction. In one embodiment, the RL agent can be implemented using a proximal policy optimization (PPO) algorithm. The policy and value networks of PPO can involve two requirements: invariance with respect to the number of networks and invariance with respect to the cell width (i.e., WM1). For a given standard cell library, the cell height HM1 can typically be constant.

[0035] The genetic algorithm-based routing algorithm can utilize multiple routing segments as a genetic representation to facilitate the preservation of very good routing islands in the routing structure during genetic operations such as crossover and mutation. The fitness of each individual chromosome in a generation can be evaluated based on two metrics: (1) the number of unrouted terminal pairs, and (2) the number of DRCs. Other metrics can also be configured into the fitness function, such as total routing cost or design for manufacturing (DFM) metrics.

[0036] Thus, in one aspect, the routing method for circuit layout disclosed herein utilizes a genetic routing algorithm to generate routing candidates. An reinforcement learning model is applied to correct design rule constraint errors caused by the routing. Uncorrected design rule constraints from the reinforcement learning model are applied to evolve the genetic routing algorithm, possibly along with other feedback from the RL model such as the number of unrouted terminal pairs. The routing can be confined to the M1 layer of the circuit layout, although this is not necessary.

[0037] In one embodiment, the reinforcement learning model can be implemented with a convolutional neural network that generates an embedding for at least one policy neural network, and a state value neural network. The convolutional neural network can receive stick figure images of the circuit layout that the reinforcement learning model converts into action probabilities (and state values).

[0038] The fitness function of the genetic router algorithm can utilize a weighted sum of the number of unrouted terminal pairs in a candidate route and the number of design rule constraint errors in the candidate route. Other technical features can be readily apparent to one skilled in the art from the following figures, descriptions, and claims.

[0039] Embodiments of a system comprising one or more processors comprising logic that, when applied to the one or more processors, operates a genetic routing algorithm to generate a plurality of candidate routed circuit layouts and operates an enhanced learning model to correct design rule constraint errors in the candidate routed circuit layouts are also described herein. The system can also include feedback from the model of several design rule constraint errors (and several unrouted terminal pairs) to evolve the genetic routing algorithm.

[0040] The system can include a plurality of policy neural networks, each policy neural network including a plurality of fully connected layers and an operation mask. The state value neural network can also include a plurality of fully connected layers. Converting a candidate routed circuit layout into action probabilities and state values can be invariant with respect to a width of a stick figure image.

[0041] The artificial neural network embodiments disclosed herein include a convolutional neural network coupled to receive a circuit layout image from a genetic router, the convolutional neural network configured to convert the circuit layout image into an embedding of a plurality of policy neural networks and a state value neural network, the plurality of policy neural networks configured to transform the embedding into action probabilities for correcting design rule constraint errors in the circuit layout image. Other technical features can be readily apparent to one skilled in the art from the following figures, descriptions, and claims.

[0042] Figure 1A A stick figure is depicted that portrays an embodiment of a standard latch cell. Stick figures are a well-known technique for prototyping circuit designs. The stick figure can include information for generating a DRC-clean layout.

[0043] In the depicted stick figure, the network can be routed in five different physical layers, referred to as drain, gate, Ml, M2, and M3. The Ml and M3 layers are restricted to horizontal routing, while the M2 layer is restricted to vertical routing. Drain connections enable some vertical routing underneath Ml in essence, and gate connections enable some (usually minimal) horizontal routing. There can be many constraints configured about how each layer can be routed in general. The most stringent DRC rules are usually configured on the Ml layer. On the Ml layer, the routing shapes are restricted to be positioned on a fixed grid, and the cut metal shapes are restricted to be inserted between adjacent routing segments on the same track. The location of the cut metal can be inferred from the routing assignment, and is usually subject to many DRC constraints.

[0044] A stick figure constrains the placement of a device to a particular location along a track. A stick figure also inherently determines where to cut certain underlying places and whether it is legal (complies with constraints). The locations of vias, pins, and text labels are also inherently inferred. Because the underlying layer shapes and metal shapes within a standard cell are constrained to a small set of allowed locations, a set of layout sub-cells can be generated that include all legal shape permutations that comply with the library template and DRC rules. These can be assembled into layout candidates. When routing a candidate layout, real-time (during routing) DRC checks can be used to provide ongoing feedback of DRC violations.

[0045] One type of DRC constraint requires that closely placed cut metal shapes be colored differently for double patterning. Double patterning is a technique that splits a dense (closely placed) pattern into two interleaved patterns of less dense features defined by two masks. Given sufficiently accurate alignment, the two patterns accumulate on the wafer surface to produce a much greater density of features than is achievable with one mask. Double patterning techniques can utilize two complementary color masks used in a litho-etch, litho-etch (LELE) process. Implementing double patterning can require that the number of shapes in a loop formed by cut metal be even, as shown in Figure 1B

[0046] If a loop has an odd number of cut metal shapes, as depicted in Figure 1C , it becomes impossible to color it correctly. Implementing this type of DRC in a MILP requires enumerating all possible loops formed by cut metal, exponentially increasing the number of constraints. However, this DRC can be easily implemented with embodiments of the disclosed method.

[0047] Figure 2A An exemplary routed layout generated by a genetic algorithm configured by DRC is depicted. Dotted lines depict Ml layer DRC violations.

[0048] Figure 2B A routed layout after applying DRC fixes by a reinforcement learning algorithm is depicted. Figure 2A

[0049] Figure 3 ​​A circuit layout router 300 in one embodiment is depicted. A layout with device placement 302 is input to a genetic router 304, which generates a set of candidate routed layouts 306. The candidate routed layouts 306 are applied to a reinforcement learning model 308, which corrects DRC errors detected in the candidate routed layouts 306 and returns a set of DRC corrected routed layouts 310 to the genetic router 304. The genetic router 304 evaluates the fitness of the DRC corrected routed layouts 310 based in part on the number of uncorrected DRC errors remaining in the DRC corrected routed layouts 310. Ultimately, the genetic router 304 evolves one or more final routed layouts 312.

[0050] Figure 4 An advanced technology node incremental routing process 400 in one embodiment is depicted. In block 402, the incremental routing process 400 executes a genetic routing algorithm to generate a route in a circuit layout. In block 404, the incremental routing process 400 applies a reinforcement learning model to correct design rule constraint errors caused by the route. In block 406, the incremental routing process 400 applies a plurality of uncorrected design rule constraint errors to evolve the genetic routing algorithm.

[0051] For a set of PMOS and NMOS devices in a standard cell, the placement algorithm strives to place them on PMOS and NMOS rows of the cell layout while satisfying technology constraints. In addition to device placement, cell pin locations can be specified during placement. Some conventional device placers split placement into two steps: pairing and ordering. The pairing step pairs each PMOS device with an NMOS device to form a device pair. The ordering step generates a placement order of the device pairs, and from the placement order and pairs infers a final placement. The two steps are interdependent, so solving one after the other is suboptimal. Therefore, in some embodiments, a simulated annealing based algorithm that performs pairing and ordering simultaneously can be utilized. Figure 5 Aspects of a simulated annealing placement routine 500 in one embodiment are depicted.

[0052] The simulated annealing placement routine 500 can perform moves on the placement template. The moves can specify a placement order of pins (block 502), an order of NMOS and PMOS devices (block 504), and whether to flip device orientation (switch source and drain locations - block 506). An objective function is optimized as a score function of the weighted sum of cell width, congestion estimate, and technology constraint violations (block 508). Moves can be categorized by type of move or by target device of the move. "Flip" changes all target devices to flip the designation. "Swap" swaps target devices. "Move" moves target devices to a specific location. The target devices can be consecutive PMOS devices, consecutive NMOS devices, consecutive PMOS / NMOS device pairs, or pins. In one embodiment, the simulated annealing algorithm can be implemented based on a modified Lam annealing schedule without the need for hyperparameter tuning.

[0053] Figure 6 A genetic routing algorithm 600 in one embodiment is depicted. The inputs to the genetic routing algorithm 600 include a set of circuit nets N(l...n) and a set of terminals T n for each net n of N. Each T n may be ordered from left to right or in some other defined order (e.g., from right to left). If ordered from left to right, a set of terminal pairs P n may be created for each net n. The union of the sets P n is the global set of terminal pairs P. A "chromosome" in the genetic routing algorithm 600 represents a possible routing solution. The set of all such chromosomes is generation G of the genetic routing algorithm 600. A particular chromosome R i of G is a set of terminal pairs p from the set P, and a set of (newly generated) routing segments r(p) between those terminal pairs. In one embodiment, the routing segments r(p) can be generated with a Lee maze router.

[0054] Each chromosome is evaluated according to a fitness function. In one embodiment, the fitness function is:

[0055]

[0056] In other words, the fitness is R i after applying reinforcement learning. U(R ithe reciprocal of the weighted sum of the number of un-routed terminal pairs in the candidate routing solution and the number of remaining DRC errors in the chromosome (DRC(Ri)). In one embodiment, the weight a is chosen to be larger than the weight b (e.g., > 2X, > 3X, > 5X, or more than one or more orders of magnitude) to prioritize fully routed solutions. Other metrics (e.g., weighted terms) can also be added to this equation, such as total wiring cost or DFM metrics. Because the PPO policy is stochastic, multiple inferences of the DRC RL agent on the same routing and final routing with the least number of DRCs are selected as the solution.

[0057] a pair of candidate solutions R mom and R dad are selected for crossover based on fitness level from the previous generation G. In one embodiment, the chromosomes R i with the highest fitness level in the generation G are selected for crossover. The probability of selection is given by the following equation:

[0058]

[0059] In other words, the candidate solutions with the highest fitness in the generation G are selected for crossover. In one embodiment, the crossover is performed as follows:

[0060] • A cut point in the chromosome is selected. The cut can be vertical or horizontal.

[0061] • For a vertical cut, the crossover operator takes all r mom (p) routes that are entirely on the left-hand side of the vertical cut and all r dad (p) routes that are entirely on the right-hand side of the cut and generates an offspring in the next generation from this pair of chromosomes.

[0062] • The crossover operator also generates another offspring in the next generation from the right-hand side routes from R mom and the left-hand side routes from R dad .

[0063] • A horizontal cut is similarly handled.

[0064] For each offspring generated by crossover, the mutation operator can randomly (with probability Prib m ) select a region in the candidate layout and remove any routes r(p) in the offspring that contact this region. After mutation, the remaining open terminal pairs can be routed using the maze router with the random terminal pair order.

[0065] Both initial routing and subsequent routing of unrouted terminal pairs can be performed with a maze router that utilizes a grid space of stick representations and the Lee algorithm to search for the minimum route between two terminals. To explore more routing space, the maze router can perform a number I > 1 of iterations and select the solution with the minimum number of unrouted pairs. The maze router can also produce any random route between two terminals at the same cost (weighted route cost per segment).

[0066] Figure 7 An enhanced learning artificial neural network 700 for DRC error in one embodiment is depicted. DRC error correction by the enhanced learning artificial neural network 700 can focus in the M1 layer, with DRC errors in other layers fixed in the routing step. M1 layer DRC errors arise from constraints on cut metal locations. Cut metal locations in turn are inherently determined by M1 routing. Thus, changing M1 routing changes cut metal locations, which in turn changes M1 DRCs. Thus, enhanced learning can be configured to incrementally change M1 routes in order to reduce M1 DRCs. In some embodiments, this approach can be extended to fix DRCs in other layers, with incremental changes to routing effective in modifying those DRCs.

[0067] Enhanced learning can be configured for restricting the addition of new routes to the M1 layer and not evaluating the removal of existing M1 routes. This constraint helps to ensure routability of the initial routed solution. Because the genetic algorithm routing step creates multiple routing solutions that expand the solution space, it imposes a limit on the solution space of the DRC fixing step, which is improved.

[0068] An enhanced learning algorithm can be characterized by its observation space, action space, internal state, reward, and completion condition. In one embodiment, the internal state of the DRC enhanced learning environment is the grid space of stick layout representations. The observation space (obs) is represented in a box tensor of dimension H M1 and W M1 are the M1 layer grid dimensions. obs[0, :, :, ] represents the M1 layer routes. obs[1, :, :, ] represents the route masks. Two conditions are configured for valid route grids: (1) they are adjacent to existing route grids, and (2) they do not create potential short circuits to other routes. obs[2, :, :, ] represents the DRC information.

[0069] The action space act is a categorical tensor of dimension [H M1 x W M1 ]. It represents the M1 layer grid [H M1 , W M1the probability that any one of the actions in the set should be routed. The stick representation of the layout is updated according to the action, and the DRC checker returns any new DRCs that apply after the action.

[0070] There are two types of rewards given by the environment. r s is a negative reward given at each step. This ongoing negative reward forces the agent to end the game as soon as possible. d is a reward associated with DRC improvement, r d = R d x ADRC, where R d is a coefficient and ADRC is the reduction in the number of DRC errors reported by the DRC checker. This reward drives the agent to reduce the DRC as much as possible.

[0071] The agent finishes its processing under two "finish" conditions. First, when there is no available action for the next step, i.e., the mask layer obs[l, :, : ] = 0. Second, when the number of DRCs is zero, i.e., the DRC layer obs[2, :, : ] = 0.

[0072] In one embodiment, a proximal policy optimization (PPO) algorithm is used for DRC fixing. The PPO algorithm is a policy gradient-based RL algorithm. The PPO algorithm includes two policy models: (1) a training model, and (2) a rollout model. The training model is responsible for learning the model parameters, and the rollout model is responsible for collecting training data while interacting with the environment.

[0073] The PPO algorithm utilizes an objective function that provides a limited divergence between the training model and the rollout model. A deep learning model utilizing PPO can include two subnetworks: (1) a state value subnetwork that predicts the state value of the current state, and (2) a policy subnetwork that produces a policy probability for each action. The two subnetworks can share a common parent network that generates an embedding that is applied in each individual subnetwork.

[0074] The reinforcement learning model of PPO can have two requirements: (1) invariance with respect to the number of nets, and (2) invariance with respect to the unit width (i.e. ) of the nets. For a given technology library, the unit height H M1 is typically a constant. The observation space described above is independent of the number of nets, thus satisfying the first requirement. However, the second requirement is not satisfied by default since both the observation space and the action space depend on . Figure 7 The reinforcement learning artificial neural network 700 embodiment depicted in FIG. 7 eliminates this dependency.

[0075] In the depicted reinforcement learning artificial neural network 700 embodiment, an observation obs (e.g., a stick layout as a two-dimensional digital image) is passed into a plurality (e.g., four) of convolutional layers 702. Each convolutional layer 702 can utilize a VALID padding technique (assuming all dimensions are valid such that the input image is completely covered by the filter and stride) to generate an output activation having the same height and width as the input vector. The output of the last convolutional layer is a state embedding 704, which in the depicted embodiment has a tensor The state embedding 704 is input to a state value network 706 and one or more policy networks 708. The depicted policy networks 708 each include a plurality (e.g., three) of fully connected layers having a channel dimension of (64, 64, 1). Each pixel of the state embedding 704 can be input to these fully connected layers. Because the channel dimension of each pixel on the state embedding 704 is fixed (e.g., at 512), the parameters of those fully connected layers do not depend on the size of the input image. The outputs of the policy networks 708 for all pixels are collected together (collected outputs 710), masked with an action mask 712 from the observation into masked outputs 714, and input to a Softmax layer 716 in order to generate a final action policy 718 vector.

[0076] To produce a state value, the state embedding 704 in this example is input to a pooling layer 720 (e.g., average pooling) to form a 512-wide vector 722. This vector 722 is input to a state value network 706 that includes a plurality (e.g., three) of fully connected layers. In the depicted example, these layers process a vector having a channel dimension of (64, 64, 1). The output of the state value network 706 is a state value prediction. The state value network 706 is independent of the size of the input stick depiction image.

[0077] The algorithms and techniques disclosed herein can be executed by computing devices that utilize one or more graphics processing units (GPUs) and / or general purpose data processors (e.g., central processing units or CPUs). Those skilled in the art will appreciate that certain GPU computing architectures, such as those provided by Nvidia As provided, features are provided that are implementation-specific to deep learning and routing algorithms. An example architecture that can be configured to execute the techniques disclosed herein on such devices will now be described.

[0078] For example, the reinforcement learning algorithm embodiments described herein can be implemented in Python based on the OpenAI GYM framework. The genetic algorithm and maze router can also be implemented in Python. Training for the reinforcement learning model can be performed on an NVIDIA V100 GPU. The genetic routing algorithm can be executed on an NVIDIA DGX server with 64 CPU cores (Intel Xeon CPU E5-2698 v4 @ 2.20 GHz) and 8 V100 GPUs. The hyperparameters for the genetic algorithm can be set as follows: G = 200, K = 24, Probm = 0.01, TR = 10, a = 100, b = 1.

[0079] The following description can use certain acronyms and abbreviations, which are defined as follows:

[0080] • “DPC” refers to “Data Processing Cluster”;

[0081] • “GPC” refers to “General Purpose Processing Cluster”;

[0082] • “I / O” refers to “Input / Output”;

[0083] • “L1 cache” refers to “Level 1 cache”;

[0084] • “L2 cache” refers to “Level 2 cache”;

[0085] • “LSU” refers to “Load / Store Unit”;

[0086] • “MMU” refers to “Memory Management Unit”;

[0087] • “MPC” refers to “M Pipe Controller”;

[0088] • “PPU” refers to “Parallel Processing Unit”;

[0089] • “PROP” refers to “Pre-Raster Operations Unit”;

[0090] • “ROP” refers to “Raster Operations”;

[0091] • “SFU” refers to “Special Function Unit”;

[0092] • “SM” refers to “Streaming Multi-Processor”;

[0093] • “Viewport SCC” refers to “Viewport Scaling, Clipping, and Culling”;

[0094] • “WDX” refers to “Work Distribution Crossbar”;

[0095] • “XBar” refers to “Crossbar Switch”.

[0096] Parallel processing unit

[0097] Figure 8 A computing system 800 including a parallel processing unit 802a is depicted in accordance with one embodiment. In one embodiment, the parallel processing unit 802a is a multi-threaded processor implemented on one or more integrated circuit devices. The parallel processing unit 802a is a latency-hiding architecture designed to process many threads in parallel. A thread (i.e., an execution thread) is an instance of a set of instructions configured to be executed by the parallel processing unit 802a. In one embodiment, the parallel processing unit 802a is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device, such as a liquid crystal display (LCD) device. In other embodiments, the parallel processing unit 802a can be used to perform general purpose computing. Although one exemplary parallel processor is provided herein for illustrative purposes, it should be specifically noted that this processor is set forth for illustrative purposes only and any processor can be used in addition to and / or in place of this processor.

[0098] One or more parallel processing unit 802a modules can be configured to accelerate thousands of high performance computing (HPC), datacenter, and machine learning applications. The parallel processing unit 802a can be configured to accelerate numerous deep learning systems and applications, including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulations, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, among others.

[0099] As Figure 8The illustrated parallel processing unit 802a includes an I / O unit 804, a front-end unit 806, a scheduler unit 808, a work distribution unit 810, a hub 812, a crossbar 814, one or more general processing cluster 900 modules, and one or more memory partition unit 1000 modules. The parallel processing unit 802a can be interconnected to a host processor or other parallel processing units 802a modules via one or more high-speed NVLinks 816. The parallel processing unit 802a can be connected to a host processor or other peripheral devices via an interconnect 818. The parallel processing unit 802a can also be connected to local memory which can include a number of memory devices 820. In one embodiment, the local memory can include a number of dynamic random access memory (DRAM) devices. The DRAM devices can be configured as a high-bandwidth memory (HBM) subsystem in which a number of DRAM dies are stacked within each device. The memory 820 can include logic to configure the parallel processing unit 802a to perform aspects of the techniques disclosed herein.

[0100] The NVLink 816 interconnect enables the system to scale with additional parallel processing unit 802a modules combined with one or more CPUs, supports cache coherency between the parallel processing unit 802a modules and the CPUs, and CPU offloading. Data and / or commands can be sent by the NVLink 816 to other units of the parallel processing unit 802a, such as one or more copy engines, video encoders, video decoders, power management units, etc. (not explicitly shown), from the hub 812. In conjunction with the Figure 12 The NVLink 816 is described in further detail.

[0101] The I / O unit 804 is configured to transmit and receive communications (e.g., commands, data, etc.) from a host processor (not shown) over the interconnect 818. The I / O unit 804 can communicate directly with the host processor via the interconnect 818 or via one or more intermediate devices such as a memory bridge. In one embodiment, the I / O unit 804 can communicate with one or more other processors (e.g., one or more of the parallel processing units 802a modules) via the interconnect 818. In one embodiment, the I / O unit 804 implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus, and the interconnect 818 is a PCIe bus. In alternative embodiments, the I / O unit 804 can implement another type of known interface for communicating with external devices.

[0102] The I / O unit 804 decodes data packets received via the interconnect 818. In one embodiment, the data packets represent commands configured to cause the parallel processing unit 802a to perform various operations. The I / O unit 804 sends decoded commands, as specified by the commands, to various other units of the parallel processing unit 802a. For example, some commands can be sent to the front end unit 806. Other commands can be sent to the hub 812 or to other units such as one or more copy engines, video encoders, video decoders, power management units, etc. (not explicitly shown). In other words, the I / O unit 804 is configured to route communications between and among various logical units of the parallel processing unit 802a.

[0103] In one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload for the parallel processing unit 802a to process. The workload can include a number of instructions and data to be processed by those instructions. The buffer is a region of memory that is accessible (e.g., read / write) by both the host processor and the parallel processing unit 802a. For example, the I / O unit 804 can be configured to access the buffer in a system memory connected to the interconnect 818 via memory requests transmitted over the interconnect 818. In one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to a start of the command stream to the parallel processing unit 802a. The front end unit 806 receives the pointer to the one or more command streams. The front end unit 806 manages the one or more streams, reading commands from the streams and forwarding the commands to various units of the parallel processing unit 802a.

[0104] The front end unit 806 is coupled to a scheduler unit 808, which is configured to schedule tasks for execution by one or more of the general processing clusters 900. The scheduler unit 808 keeps track of which tasks have been assigned to which general processing clusters 900, which tasks are active, and which tasks have completed. In one embodiment, the scheduler unit 808 also manages integration of tasks from different streams. In some embodiments, the scheduler unit 808 also manages a priority level of each task. In one embodiment, the priority level indicates the desirability with which the task is to be performed. The scheduler unit 808 makes a determination as to where to place tasks based on a variety of factors such as availability of general processing clusters 900, priority level, and others.

[0105] The scheduler unit 808 is coupled to a work distribution unit 810, which is configured to distribute tasks for execution on the general processing cluster 900 modules. The work distribution unit 810 can track a number of scheduled tasks received from the scheduler unit 808. In one embodiment, the work distribution unit 810 manages a pending task pool and an active task pool for each general processing cluster 900 module. The pending task pool can include a number of slots (e.g., 32 slots) that contain tasks that are assigned to be processed by a particular general processing cluster 900. The active task pool can include a number of slots (e.g., 4 slots) for tasks that are actively being processed by a general processing cluster 900 module. When a general processing cluster 900 completes execution of a task, the task is evicted from the active task pool for the general processing cluster 900 and one of the other tasks from the pending task pool is selected and scheduled for execution on the general processing cluster 900. If the active task on a general processing cluster 900 has idled, e.g., while waiting for a data dependency to be resolved, then the active task can be evicted from the general processing cluster 900 and returned to the pending task pool, and another task in the pending task pool is selected and scheduled for execution on the general processing cluster 900.

[0106] The work distribution unit 810 communicates with one or more general processing cluster 900 modules via a crossbar 814. The crossbar 814 is an interconnect network that couples many units of the parallel processing unit 802a to other units of the parallel processing unit 802a. For example, the crossbar 814 can be configured to couple the work distribution unit 810 to a particular general processing cluster 900. Although not explicitly shown, one or more other units of the parallel processing unit 802a can also be connected to the crossbar 814 via the hub 812.

[0107] A task is managed by the scheduler unit 808 and distributed to a general processing cluster 900 by the work distribution unit 810. The general processing cluster 900 is configured to process the task and generate results. The results can be consumed by other tasks within the general processing cluster 900, routed to a different general processing cluster 900 via the crossbar 814, or stored in the memory 820. The results can be written to memory 820 via a memory partition unit 1000, which modules the memory interface for reading from and writing to memory 820. The results can be sent over the NVLink 816 to another parallel processing unit 802a or CPU. In one embodiment, the parallel processing unit 802a includes a number U of memory partition units 1000 equal to the number of independent and distinct memory 820 devices coupled to the parallel processing unit 802a. The memory partition unit 1000 will be described in greater detail below in conjunction with FIG. 10. Figure 10 The memory partition unit 1000 is described in greater detail.

[0108] In one embodiment, the host processor executes a driver kernel that implements an application programming interface (API), enabling the execution of one or more applications on the host processor to schedule operations for execution on the parallel processing unit 802a. In one embodiment, multiple computing applications are executed concurrently by the parallel processing unit 802a, and the parallel processing unit 802a provides isolation, quality of service (QoS), and independent address spaces for the multiple computing applications. Applications can generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks to be executed by the parallel processing unit 802a. The driver kernel outputs the tasks to one or more streams being processed by the parallel processing unit 802a. Each task may include one or more associated thread groups, referred to herein as a warp. In one embodiment, a warp includes 32 associated threads that can execute in parallel. Cooperative threads can refer to multiple threads that include instructions for executing tasks and can exchange data via shared memory. Figure 11 A more detailed description of threads and cooperative threads.

[0109] Figure 9 An embodiment is shown. Figure 8 The general-purpose processing cluster 900 is a parallel processing unit 802a. For example... Figure 9 As shown, each general-purpose processing cluster 900 includes multiple hardware units for processing tasks. In one embodiment, each general-purpose processing cluster 900 includes a pipeline manager 902, a pre-raster operation unit 904, a raster engine 906, a job allocation crossbar switch 908, a memory management unit 910, and one or more data processing clusters 912. It should be understood that... Figure 9 The general-purpose processing cluster 900 can include alternatives Figure 9 Other hardware units of the unit shown or excluding Figure 9 Other hardware units besides the unit shown.

[0110] In one embodiment, the operations of the general processing cluster 900 are controlled by a pipeline manager 902. The pipeline manager 902 manages configuration of one or more data processing cluster 912 modules for processing tasks assigned to the general processing cluster 900. In one embodiment, the pipeline manager 902 can configure at least one of the one or more data processing cluster 912 modules to implement at least a portion of a graphics rendering pipeline. For example, a data processing cluster 912 can be configured to execute a vertex shading program on the programmable streaming multi-processor 1100. The pipeline manager 902 can also be configured to route data packets received from the work distribution unit 810 to appropriate logical units in the general processing cluster 900. For example, some data packets can be routed to fixed function hardware units in the pre-raster operations unit 904 and / or the raster engine 906, while other data packets can be routed to a data processing cluster 912 module for processing by a geometry engine 914 or streaming multi-processor 1100. In one embodiment, the pipeline manager 902 can configure at least one of the one or more data processing cluster 912 modules to implement a neural network model and / or compute pipeline.

[0111] The pre-raster operations unit 904 is configured to route data generated by the raster engine 906 and the data processing cluster 912 modules to a raster operations (ROP) unit for Figure 10 are described in greater detail. The pre-raster operations unit 904 can also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and / or the like.

[0112] The raster engine 906 includes a number of fixed function hardware units that are configured to perform various raster operations. In one embodiment, the raster engine 906 includes a setup engine, a coarse raster engine, a cull engine, a clip engine, a fine raster engine, and a tile aggregation engine. The setup engine receives transformed vertices and generates a plane equation associated with a geometric primitive defined by the vertices. The plane equation is sent to the coarse raster engine to produce coverage information (e.g., x, y coverage masks for tiles) of the geometric primitive. The output of the coarse raster engine is sent to the cull engine where fragments associated with primitives that fail a z-test are culled, and to the clip engine where fragments that are outside the view volume are clipped. Those fragments that remain after clipping and culling can be passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equation generated by the setup engine. The output of the raster engine 906 includes, for example, fragments to be processed by a fragment shader implemented within the data processing cluster 912.

[0113] Each data processing cluster 912 included in the general processing cluster 900 includes an M-pipe controller 916, a geometry engine 914, and one or more streaming multiprocessors 1100 modules. The M-pipe controller 916 controls the operation of the data processing cluster 912, routing data packets received from the pipeline manager 902 to the appropriate unit in the data processing cluster 912. For example, data packets associated with a vertex can be routed to the geometry engine 914, which is configured to fetch vertex attributes associated with the vertex from the memory 820. Conversely, data packets associated with a shader program can be sent to the streaming multiprocessor 1100.

[0114] The streaming multiprocessor 1100 includes a programmable streaming processor configured to process tasks represented by a plurality of threads. Each streaming multiprocessor 1100 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a particular thread group simultaneously. In one embodiment, the streaming multiprocessor 1100 implements a single-instruction, multiple-data (SIMD) architecture wherein each thread in the thread group (e.g., a thread warp) is configured to process a different data set based on the same set of instructions. All threads in the thread group execute the same instructions. In another embodiment, the streaming multiprocessor 1100 implements a single-instruction, multiple-thread (SIMT) architecture wherein each thread in the thread group is configured to process a different data set based on the same set of instructions, but where individual threads in the thread group are allowed to diverge during execution. In one embodiment, a program counter, call stack, and execution state are maintained for each thread warp, enabling concurrent between thread warps and serial execution within thread warps when threads within the thread warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, enabling equal concurrency between all threads within and between thread warps. When execution state is maintained for each individual thread, threads executing the same instruction can be converged and executed in parallel for maximum efficiency. The following discussion is presented to enable others skilled in the art to make and use embodiments of the application in the best mode contemplated by the inventors. Thus, the following discussion is presented with the understanding that the Figure 11 The streaming multiprocessor 1100 is described in more detail.

[0115] The memory management unit 910 provides an interface between the general processing cluster 900 and the memory partition unit 1000. The memory management unit 910 can provide translations of virtual addresses to physical addresses, memory protection, and arbitration of memory requests. In one embodiment, the memory management unit 910 provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses to physical addresses in the memory 820.

[0116] Figure 10 A memory partition unit 1000 of the parallel processing unit 802a in accordance with one embodiment is depicted. Figure 8 Figure 10 ​As shown, the memory partition unit 1000 includes a raster operations unit 1002, a level two cache 1004, and a memory interface 1006. The memory interface 1006 is coupled to the memory 820. The memory interface 1006 can implement a 32, 64, 128, 1024-bit data bus, etc. for carrying data to and from memory. In one embodiment, the parallel processing unit 802a incorporates U memory interfaces 1006 modules, one for each pair of memory partition unit 1000 modules, with each pair of memory partition unit 1000 modules connected to a corresponding memory 820 device. For example, the parallel processing unit 802a can be connected to up to Y memory 820 devices, such as high bandwidth memory stacks or graphics double data rate version 5 synchronous dynamic random access memory or other types of persistent storage.

[0117] In one embodiment, the memory interface 1006 implements an HBM2 memory interface and Y is equal to half of U. In one embodiment, the HBM2 memory stacks are located on the same physical package as the parallel processing unit 802a, providing significant power and area savings compared to a conventional GDDR5 SDRAM system. In one embodiment, each HBM2 stack includes four memory dies and Y is equal to 4, with the HBM2 stack including two 128-bit channels per die, for a total of 8 channels and a data bus width of 1024 bits.

[0118] In one embodiment, the memory 820 supports single error correction double error detection (SECDED) error correcting code (ECC) to protect data. For compute applications that are sensitive to data corruption, the ECC provides higher reliability of the data. In large cluster computing environments, the parallel processing unit 802a modules are particularly important to reliability given the large size of the data sets and / or long periods of execution of an application.

[0119] In one embodiment, the parallel processing unit 802a implements a multi-level memory hierarchy. In one embodiment, the memory partition unit 1000 supports a unified memory to provide a single unified virtual address space for the CPU and the parallel processing unit 802a memory, enabling a sharing of data between the virtual memory systems. In one embodiment, the frequency of access to a memory page by a parallel processing unit 802a is tracked, such that memory pages that are frequently accessed by a parallel processing unit 802a are moved to the memory 820 of that parallel processing unit 802a. In one embodiment, the NVLink 816 supports an address translation service, which allows the parallel processing unit 802a to access page tables of the CPU directly and provide full access to CPU memory by the parallel processing unit 802a.

[0120] In one embodiment, the copy engine transfers data between multiple parallel processing unit 802a modules or between a parallel processing unit 802a module and a CPU. The copy engine can generate a page fault for an address that is not mapped to a page table. The memory partition unit 1000 can then service the page fault, map the address into a page table, after which the copy engine can perform the transfer. In conventional systems, memory is fixed (e.g., non-paged) for multiple copy engine operations between multiple processors, reducing the available memory. Due to the hardware page fault, an address can be passed to the copy engine without worrying about whether a memory page is resident, and whether the copy process is transparent.

[0121] Data from memory 820 or other system memory can be retrieved and stored by the memory partition unit 1000 and stored in a level two cache 1004, which is on-chip and shared between various general processing cluster 900 modules. As shown, each memory partition unit 1000 includes a portion of the level two cache 1004 that is associated with a corresponding memory 820 device. Lower level caches can then be implemented in multiple units within the general processing cluster 900 module. For example, each streaming multi-processor 1100 module can implement a LI cache. The LI cache is a dedicated memory for a particular streaming multi-processor 1100. Data from the level two cache 1004 can be fetched and stored in each LI cache for processing in the functional units of the streaming multi-processor 1100 module. The level two cache 1004 is coupled to the memory interface 1006 and the crossbar 814.

[0122] The raster operations unit 1002 performs graphics raster operations related to pixel colors such as color compression, pixel blending, etc. The raster operations unit 1002 also implements depth testing with the raster engine 906, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine 906. The depth for the sample location associated with the fragment is tested against a corresponding depth in a depth buffer. If the fragment passes the depth test for the sample location, the raster operations unit 1002 updates the depth buffer and sends the results of the depth test to the raster engine 906. It will be appreciated that the number of memory partition unit 1000 modules can be different from the number of general processing cluster 900 modules, and thus each raster operations unit 1002 can be coupled to each general processing cluster 900 module. The raster operations unit 1002 tracks data packets received from different general processing cluster 900 modules and determines to which general processing cluster 900 the results generated by the raster operations unit 1002 are routed through the crossbar 814. Although in the embodiment shown in FIG. 10, the raster operations unit 1002 is shown as a separate unit from the memory partition unit 1000, it will be appreciated that the raster operations unit 1002 can be implemented as part of the memory partition unit 1000. Figure 10The raster operation unit 1002 is included within the memory partition unit 1000, but in other embodiments, the raster operation unit 1002 may be located outside the memory partition unit 1000. For example, the raster operation unit 1002 may reside in the general-purpose processing cluster 900 or another unit.

[0123] Figure 11 An embodiment is shown. Figure 9 The streaming multiprocessor 1100. For example... Figure 11 As shown, the streaming multiprocessor 1100 includes an instruction cache 1102, one or more scheduler units 1104 modules (e.g., scheduler unit 808), a register file 1106, one or more processing cores 1108 modules, one or more special function units 1110 modules, one or more load / store units 1112 modules, an interconnect network 1114, and a shared memory / L1 cache 1116.

[0124] As described above, the work allocation unit 810 schedules tasks to be executed on the general-purpose processing cluster 900 module of the parallel processing unit 802a. Tasks are assigned to a specific data processing cluster 912 within the general-purpose processing cluster 900, and if the task is associated with a shader program, it can be assigned to the streaming multiprocessor 1100. The scheduler unit 1104 receives tasks from the work allocation unit 810 and manages the instruction scheduling of one or more thread blocks assigned to the streaming multiprocessor 1100. The scheduler unit 1104 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In one embodiment, each thread bundle executes 32 threads. The scheduler unit 1104 can manage multiple different thread blocks, assign thread bundles to different thread blocks, and then dispatch instructions from multiple different cooperative groups to various functional units (i.e., the core 1108 module, the special function unit 1110 module, and the load / store unit 1112 module) during each clock cycle.

[0125] Cooperative groups are a programming model for organizing groups of communicating threads that allow developers to express the granularity at which threads are communicating, enabling richer, more efficient parallel decomposition. Cooperative launch APIs support synchronization between thread blocks to execute parallel algorithms. Conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, programmers often want to define thread groups at a granularity smaller than a thread block and synchronize within the defined groups to enable higher performance, design flexibility, and software reuse in the form of collective group-wide function interfaces.

[0126] Cooperative groups enable programmers to explicitly define thread groups at sub-block (e.g., as small as individual threads) and multi-block granularities and perform collective operations, such as synchronization across threads in a cooperative group. The programming model supports clean composition across software boundaries so that libraries and utility functions can safely synchronize in their local environment without making assumptions about convergence. Cooperative group primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire thread block grid.

[0127] The dispatch 1118 units are configured within the scheduler unit 1104 to issue instructions to one or more functional units. In this embodiment, the scheduler unit 1104 includes two dispatch 1118 units that enable two different instructions from the same warp to be scheduled during each clock cycle. In alternative embodiments, each scheduler unit 1104 can include a single dispatch 1118 unit or additional dispatch 1118 units.

[0128] Each streaming multiprocessor 1100 includes a register file 1106 that provides a set of registers for the functional units of the streaming multiprocessor 1100. In one embodiment, the register file 1106 is partitioned between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 1106. In another embodiment, the register file 1106 is partitioned between different warps executed by the streaming multiprocessor 1100. The register file 1106 provides temporary storage for operands of the data

[0129] Each streaming multiprocessor 1100 includes L processing core 1108 modules. In one embodiment, the streaming multiprocessor 1100 includes a large number (e.g., 128, etc.) of distinct processing core 1108 modules. Each core 1108 can include a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit that includes floating-point and integer arithmetic logic units. In one embodiment, the floating-point arithmetic logic units implement the IEEE 754-2008 standard for floating-point operations. In one embodiment, the core 1108 modules include 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0130] The tensor cores are configured to perform matrix operations, and in one embodiment, one or more tensor cores are included in the core 1108 module. Specifically, the tensor cores are configured to perform deep learning matrix operations, such as convolution operations for neural network training and inference. In one embodiment, each tensor core operates on 4x4 matrices and performs matrix multiply and accumulate operations D = A x B + C, where A, B, C, and D are 4x4 matrices.

[0131] In one embodiment, the matrix multiply inputs A and B are 16-bit floating-point matrices, while the accumulate matrices C and D can be 16-bit floating-point or 32-bit floating-point matrices. The tensor cores operate on 16-bit floating-point input data and 32-bit floating-point accumulation. The 16-bit floating-point multiplication contains 64 operations that produce a full-precision product, which is then accumulated using 32-bit floating-point addition with other intermediate products of the 4x4x4 matrix multiplication. In practice, the tensor cores are used to perform larger two-dimensional or higher-dimensional matrix operations built up from these smaller elements. APIs, such as the CUDA 9 C++ API, expose specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16x16 size matrices across all 32 threads of a warp.

[0132] Each streaming multiprocessor 1100 also includes M special-function units 1110 modules that perform special functions, such as attribute evaluations, inverse square root, etc. In one embodiment, the special-function units 1110 modules can include a tree traversal unit configured to traverse a hierarchical tree data structure. In one embodiment, the special-function units 1110 modules can include a texture unit configured to perform texture map filtering operations. In one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texture pixels) from memory 820 and sample the texture map to produce sampled texture values for use in a shader program executed by the streaming multiprocessor 1100. In one embodiment, the texture map is stored in shared memory / L1 cache 1006. The texture unit implements texture operations, such as filtering operations using mip maps (i.e., texture maps of varying levels of detail). In one embodiment, each streaming multiprocessor 1100 includes two texture units.

[0133] Each streaming multiprocessor 1100 also includes N load / store units 1112 modules that implement load and store operations between shared memory / L1 cache 1116 and register file 1106. Each streaming multiprocessor 1100 includes an interconnect network 1114 that connects each functional unit to the register file 1106, as well as connects the load / store units 1112 to the register file 1106, shared memory / L1 cache 1116. In one embodiment, the interconnect network 1114 is a crossbar that can be configured to connect any functional unit to any register in the register file 1106, as well as connect the load / store units 1112 modules to memory locations in the register file and shared memory / L1 cache 1116.

[0134] Shared memory / L1 cache 1116 is an on-chip memory array that allows data storage and communication between the streaming multiprocessors 1100 and the primitive engine 914, as well as between threads in the streaming multiprocessors 1100. In one embodiment, shared memory / L1 cache 1116 includes 128 KB of storage capacity and is in the path from the streaming multiprocessors 1100 to the memory partition unit 1000. Shared memory / L1 cache 1116 can be used for cache reads and writes. One or more of shared memory / L1 cache 1116, level two cache 1004, and memory 820 are backing stores.

[0135] Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity can be used by a program as a cache that does not use shared memory. For example, if the shared memory is configured to use half the capacity, then texture and load / store operations can use the remaining capacity. The integration within the shared memory / L1 cache 1116 causes the shared memory / L1 cache 1116 to function as a high-throughput pipeline for streaming data and, at the same time, provide high bandwidth and low latency access to frequently reused data.

[0136] When configured for general-purpose parallel computation, a simpler configuration can be used compared to graphics processing. Specifically, Figure 8 The illustrated fixed function graphics processing units are bypassed, creating a simpler programming model. In the general-purpose parallel computation configuration, the work distribution unit 810 assigns and dispatches thread blocks directly to the data processing cluster 912 modules. The threads in a block execute the same program, using the unique thread ID in the computation to ensure each thread generates a unique result, using the streaming multiprocessor 1100 to execute the program and perform the computation, using the shared memory / L1 cache 1116 to communicate between threads, and using the load / store unit 1112 to read and write global memory through the shared memory / L1 cache 1116 and the memory partition unit 1000. When configured for general-purpose parallel computation, the streaming multiprocessor 1100 can also write commands to the scheduler unit 808 usable to launch new work on the data processing cluster 912 modules.

[0137] The parallel processing unit 802a can be included in a desktop computer, laptop computer, tablet computer, server computer, supercomputer, smart- phone (e.g., wireless, hand-held device), personal digital assistant (PDA), digital camera, vehicle, head mounted display, hand-held electronic device, etc. In one embodiment, the parallel processing unit 802a is contained on a single semiconductor substrate. In another embodiment, the parallel processing unit 802a is included on a system-on-a-chip (SoC) along with one or more other devices, such as additional parallel processing unit 802a modules, memory 820, reduced instruction set computer (RISC) CPU, memory management unit (MMU), digital-to-analog converter (DAC), etc.

[0138] In one embodiment, the parallel processing unit 802a can be included on a graphics card that includes one or more memory 820 devices. The graphics card can be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the parallel processing unit 802a can be an integrated graphics processing unit (iGPU) or parallel processor contained in a chipset of a motherboard.

[0139] Exemplary computing system

[0140] Systems with multiple GPUs and CPUs are being used across various industries as developers expose to and leverage greater parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to thousands of compute nodes are being deployed in data centers, research institutions, and supercomputers to tackle larger problems. As the number of processing devices within high-performance systems increases, communication and data transmission mechanisms need to be scaled to support this increased bandwidth.

[0141] Figure 12 This is based on the use of one embodiment. Figure 8 A conceptual diagram of a processing system 1200 implemented by a parallel processing unit 802a is shown. The processing system 1200 includes a central processing unit 1202, a switch 1204, and each of multiple parallel processing units 802a, 802b, 802c, and 802d, as well as corresponding memory modules 820. An NVLink 816 provides a high-speed communication link between each parallel processing unit 802a module. Although... Figure 12 A specific number of NVLink 816 and interconnect 818 connections are shown, but the number of connections to each parallel processing unit 802a and central processing unit 1202 can vary. A switch 1204 interfaces between the interconnect 818 and the central processing unit 1202. The parallel processing unit 802a module, memory 820 module, and NVLink 816 connections can reside on a single semiconductor platform to form the parallel processing module 1206. In one embodiment, the switch 1204 supports two or more protocols that interface between various different connections and / or links.

[0142] In another embodiment (not shown), NVLinks 816 provide one or more high-speed communication links between each parallel processing unit module (parallel processing unit 802b, parallel processing unit 802a, parallel processing unit 802a, parallel processing unit 802c) and central processing unit 1202, and a switch 1204 interfaces between interconnect 818 and each parallel processing unit module. The parallel processing unit modules, memory 820 modules, and interconnect 818 can be located on a single semiconductor platform to form a parallel processing module 1206. In yet another embodiment (not shown), interconnect 818 provides one or more communication links between each parallel processing unit module and central processing unit 1202, and a switch 1204 uses NVLinks 816 to interface between each parallel processing unit module to provide one or more high-speed communication links between parallel processing unit modules. In another embodiment (not shown), NVLinks 816 provide one or more high-speed communication links between parallel processing unit modules and central processing unit 1202 through switch 1204. In yet another embodiment (not shown), interconnect 818 directly provides one or more communication links between each parallel processing unit module. One or more NVLink 816 high-speed communication links can be implemented as physical NVLink interconnects or on-chip or off-chip interconnects using the same protocol as NVLinks 816.

[0143] In the context of this specification, a single semiconductor platform can refer to a sole unitary semiconductor-based integrated circuit that is fabricated in a single fabrication operation. It should be noted that the term single semiconductor platform can also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional bus implementation. Of course, the various circuits or devices can alternatively be formed on a single semiconductor platform depending on the desires of a user.

[0144] In one embodiment, the signaling rate of each NVLink 816 is 20 to 25 gigabits / second, and each parallel processing unit module includes six NVLink 816 interfaces (as Figure 12As shown, each parallel processing unit module includes five NVLink 816 interfaces). Each NVLink 816 provides a 25 gigabit / second data transfer rate in each direction, with six lanes providing 300 gigabit / second. When the central processing unit 1202 also includes one or more NVLink 816 interfaces, the NVLink 816 can be used exclusively to implement the CPU to GPU communication, or some combination of PPU to PPU and PPU to CPU. Figure 12 As shown, PPU to PPU communication, or some combination of PPU to PPU and PPU to CPU.

[0145] In one embodiment, the NVLink 816 allows direct load / store / atomic operations from the central processing unit 1202 to the memory 820 of each parallel processing unit module. In one embodiment, the NVLink 816 supports coherency operations allowing data read from the memory 820 module to be stored in the cache hierarchy of the central processing unit 1202, reducing cache access latency for the central processing unit 1202. In one embodiment, the NVLink 816 includes support for address translation services (ATS) such that the parallel processing unit module has direct access to page tables within the central processing unit 1202. One or more NVLink 816 can also be configured to operate in a low power mode.

[0146] Figure 13 An exemplary processing system 1300 is depicted in which various previously described embodiments of various architectures and / or functionality can be implemented. As shown, the exemplary processing system 1300 provides for at least one central processing unit 1202 connected to a communication bus 1302. The communication bus 1302 can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The exemplary processing system 1300 also includes main memory 1304. Control logic (software) and data are stored in the main memory 1304, which can take the form of random access memory (RAM).

[0147] The exemplary processing system 1300 also includes input device(s) 1306, parallel processing module(s) 1206, and display device(s) 1308, such as a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light-emitting diode), plasma display, or the like. User input can be received from input device(s) 1306, e.g., keyboard, mouse, touchpad, microphone, etc. Each of the foregoing modules and / or devices can even be located on a single semiconductor platform, e.g., a system on a chip. Alternatively, various modules can be located on different semiconductor platforms, which can be arranged to interact and work together. The input device(s) also can be used to receive data into the processing system 1300 or to retrieve data or other

[0148] In addition, exemplary processing system 1300 can be coupled to a network (e.g., a telecommunications network, a local area network (LAN), a wireless network, a wide area network (WAN) such as the Internet, a peer-to-peer network, a cable network, etc.) through network interface 1310 for communication purposes.

[0149] Exemplary processing system 1300 can also include secondary storage (not shown). Secondary storage 610 includes, for example, a hard disk drive and / or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash drive. The removable storage drive reads from and / or writes to a removable storage unit in a well-known manner.

[0150] Computer programs, or computer control logic algorithms, can be stored in main memory 1304 and / or secondary storage. These computer programs, when executed, enable the exemplary processing system 1300 to perform various functions. Main memory 1304, storage, and / or any other storage are possible examples of computer-readable media.

[0151] The architectures and / or functionalities of the various preceding figures can be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, a special purpose system, and / or any other desired system. For example, exemplary processing system 1300 can take the form of a desktop computer, laptop computer, tablet computer, server computer, super computer, smart telephone (e.g., wireless, hand-held device), personal digital assistant (PDA), digital camera, vehicle, head mounted display, hand-held electronic device, mobile telephone device, television, workstation, game console, embedded system, and / or any other type of logic.

[0152] While various embodiments have been described, it will be apparent that many modifications, additions, replacements, deletions, and substitutions are possible without departing the scope and spirit of the embodiments. As such, the breadth and scope of the embodiments should not be limited by any of the above described exemplary embodiments, but should be defined in accordance with the following claims and their equivalents.

[0153] Graphics Processing Pipeline

[0154] Figure 14 is performed by a graphics processing pipeline in accordance with an embodiment Figure 8FIG. 14 is a conceptual diagram of a graphics processing pipeline 1400 implemented by the parallel processing unit 802a. In one embodiment, the parallel processing unit 802a comprises a graphics processing unit (GPU). The parallel processing unit 802a is configured to receive commands defining a shading program to be used for processing graphics data. The graphics data can be defined as a set of primitives, such as points, lines, triangles, quads, triangle strips, etc. Typically, a primitive includes data specifying a plurality of vertices (e.g., in a model space coordinate system) and attributes associated with each vertex of the primitive. The parallel processing unit 802a can be configured to process the primitives to generate a frame buffer (e.g., pixel data for each of the pixels in a display).

[0155] An application writes model data (e.g., a collection of vertices and attributes) for a scene to memory, such as system memory or memory 820. The model data defines each of the objects that can be visible on a display. The application then makes an API call to a driver kernel, which requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to one or more streams to perform operations to process the model data. These commands can reference different shading programs to be implemented on the streaming multi-processor 1100 modules of the parallel processing unit 802a, including one or more of vertex shading, hull shading, domain shading, geometry shading, and pixel shading. For example, one or more of the streaming multi-processor 1100 modules can be configured to execute a vertex shading program that processes a plurality of vertices defined by the model data. In one embodiment, different streaming multi-processor 1100 modules can be configured to simultaneously execute different shading programs. For example, a first subset of the streaming multi-processor 1100 modules can be configured to execute a vertex shading program while a second subset of the streaming multi-processor 1100 modules can be configured to execute a pixel shading program. The first subset of streaming multi-processor 1100 modules processes the vertex data to produce processed vertex data and writes the processed vertex data to the L2 cache 1004 and / or memory 820. After the processed vertex data is rasterized (e.g., converted from three-dimensional data into two-dimensional data in screen space) to produce fragment data, the second subset of streaming multi-processor 1100 modules executes the pixel shading to produce processed fragment data, which is then blended with other processed fragment data and written to a frame buffer in memory 820. The vertex shading program and the pixel shading program can be executed simultaneously, processing different data from the same scene in a pipelined fashion until all of the model data for the scene has been rendered to the frame buffer. The contents of the frame buffer are then transmitted to a display controller for display on a display device.

[0156] The graphics processing pipeline 1400 is an abstract flowchart of processing steps implemented to generate 2D computer-generated images from 3D geometric data. It is well known that pipeline architectures can more efficiently perform long-latency operations by dividing operations into multiple stages, where the output of each stage is coupled to the input of the next successive stage. Therefore, the graphics processing pipeline 1400 receives input data 601 passed from one stage of the graphics processing pipeline 1400 to the next stage to generate output data 1402. In one embodiment, the graphics processing pipeline 1400 may represent a process... The graphics processing pipeline is defined by the API. Alternatively, the graphics processing pipeline 1400 can be implemented within the context of the functionality and architecture of previous figures and / or one or more subsequent figures.

[0157] like Figure 14 As shown, the graphics processing pipeline 1400 includes a pipeline architecture comprising multiple stages. These stages include, but are not limited to, a data assembly stage 1404, a vertex shading stage 1406, a primitive assembly stage 1408, a geometry shading stage 1410, a viewport SCC stage 1412, a rasterization stage 1414, a fragment shading stage 1416, and a raster operation stage 1418. In one embodiment, input data 1420 includes commands that configure processing units to implement the stages of the graphics processing pipeline 1400 and configure geometric primitives (e.g., points, lines, triangles, quadrilaterals, triangular strips, or sectors, etc.) to be processed by these stages. Output data 1402 may include pixel data (i.e., color data), which is copied to a frame buffer or other type of surface data structure in memory.

[0158] The data assembly stage 1404 receives input data 1420, which specifies vertex data for higher-order surfaces, primitives, etc. The data assembly stage 1404 collects vertex data from temporary storage or queues, such as by receiving a command from the host processor including a pointer to a buffer in memory and reading vertex data from that buffer. The vertex data is then passed to the vertex shading stage 1406 for processing.

[0159] The vertex shading 1406 stage processes vertex data by performing a set of operations (e.g., a vertex shader or program) on each of the vertices. A vertex can be specified, for example, as a 4-coordinate vector (e.g., <x, y, z, w>) associated with one or more vertex attributes (e.g., color, texture coordinates, surface normal, etc.). The vertex shading 1406 stage can manipulate individual vertex attributes, such as position, color, texture coordinates, etc. In other words, the vertex shading 1406 stage performs operations on vertex coordinates or other vertex attributes associated with a vertex. These operations typically include lighting operations (e.g., modifying a color attribute of a vertex) and transformation operations (e.g., modifying a coordinate space of a vertex). For example, a vertex can be specified using coordinates in an object coordinate space, which are transformed by multiplying the coordinates by a matrix that converts the coordinates from the object coordinate space to a world space or a normalized-device-coordinate (NDC) space. The vertex shading 1406 stage generates transformed vertex data that is passed to the primitive assembly 1408 stage.

[0160] The primitive assembly 1408 stage collects vertices output by the vertex shading 1406 stage and groups the vertices into geometric primitives for processing by the geometry shading 1410 stage. For example, the primitive assembly 1408 stage can be configured to group every three consecutive vertices into a geometric primitive (e.g., a triangle) for passing to the geometry shading 1410 stage. In some embodiments, particular vertices can be reused for consecutive geometric primitives (e.g., two consecutive triangles in a triangle strip can share two vertices). The primitive assembly 1408 stage passes geometric primitives (e.g., a set of associated vertices) to the geometry shading 1410 stage.

[0161] The geometry shading 1410 stage processes geometric primitives by performing a set of operations (e.g., a geometry shader or program) on the geometric primitives. Tessellation operations can generate one or more geometric primitives from each geometric primitive. In other words, the geometry shading 1410 stage can tessellate each geometric primitive into a finer mesh of two or more geometric primitives for processing by the remainder of the graphics processing pipeline 1400. The geometry shading 1410 stage passes geometric primitives to the viewport SCC 1412 stage.

[0162] In one embodiment, graphics processing pipeline 1400 can perform processing operations in sequence at stream multi-processor and vertex shading 1406 stage, primitive assembly 1408 stage, geometry shading 1410 stage, fragment shading 1416 stage, and / or hardware / software internal operations associated therewith. Once the sequential processing operations are complete, in one embodiment, viewport SCC 1412 stage can utilize the data. In one embodiment, primitive data processed by one or more of the stages in graphics processing pipeline 1400 can be written into a cache (e.g., LI cache, vertex cache, etc.). In this case, in one embodiment, viewport SCC 1412 stage can access the data in the cache. In one embodiment, viewport SCC 1412 stage and rasterization 1414 stage are implemented as fixed function circuitry.

[0163] Viewport SCC 1412 stage performs viewport scaling, culling, and clipping of the geometric primitives. Each surface being rendered is associated with an abstract camera position. The camera position represents the position of a viewer who is looking at the scene and defines a view frustum that encloses the objects of the scene. The view frustum can include a viewing plane, a back plane, and four clipping planes. Any geometric primitive that is completely outside of the view frustum can be culled (e.g., discarded) because it will not contribute to the final rendered scene. Any geometric primitive that is partially inside the view frustum and partially outside the view frustum can be clipped (e.g., converted to new geometric primitives that are enclosed within the view frustum). In addition, each geometric primitive can be scaled based on the depth of the view frustum. All potentially visible geometric primitives are then passed to rasterization 1414 stage.

[0164] Rasterization 1414 stage converts 3D geometric primitives into 2D fragments (e.g., capable of being used for display, etc.). Rasterization 1414 stage can be configured to set up a set of plane equations with the vertices of the geometric primitive from which various attributes can be interpolated. Rasterization 1414 stage can also compute a coverage mask for a plurality of pixels that indicates whether one or more sample locations of the pixel intercept the geometric primitive. In one embodiment, a z-test can also be performed to determine whether the geometric primitive is occluded by other geometric primitives that have already been rasterized. Rasterization 1414 stage generates fragment data (e.g., interpolated vertex attributes associated with particular sample locations of each covered pixel) that is passed to fragment shading 1416 stage.

[0165] Fragment shading 1416 stage processes the fragment data by performing a set of operations (e.g., a fragment shader or program) on each of the fragments. Fragment shading 1416 stage can generate pixel data (e.g., color values) for the fragments, such as by performing lighting operations or sampling texture maps using interpolated texture coordinates for the fragments. Fragment shading 1416 stage generates pixel data that is sent to raster operations 1418 stage.

[0166] The raster operations 1418 stage can perform various operations on the pixel data, such as performing alpha tests, stencil tests, and blending the pixel data with other pixel data corresponding to other fragments associated with the pixel. When the raster operations 1418 stage has completed processing of the pixel data (e.g., output data 1402), the pixel data can be written to a render target, such as a frame buffer, color buffer, etc.

[0167] It should be appreciated that one or more additional stages can be included in the graphics processing pipeline 1400 in addition to or instead of one or more of the stages described above. Different stages can be implemented by various implementations of an abstract graphics processing pipeline. Further, in some embodiments, one or more of the stages described above can be excluded from the graphics processing pipeline (such as the geometry shading 1410 stage). Other types of graphics processing pipelines are contemplated as being within the scope of the present disclosure. Further, any of the stages of the graphics processing pipeline 1400 can be implemented by one or more specialized hardware units within a graphics processor, such as the parallel processing unit 802a. Other stages of the graphics processing pipeline 1400 can be implemented by programmable hardware units, such as the streaming multiprocessors 1100 of the parallel processing unit 802a.

[0168] The graphics processing pipeline 1400 can be implemented via an application program executed by a host processor, such as a CPU. In one embodiment, a device driver can implement an application programming interface (API) that defines various functions that can be utilized by an application program to generate graphics data for display. The device driver is a software program that includes a plurality of instructions that control the operation of the parallel processing unit 802a. The API provides an abstraction for programmers that allows the programmers to generate graphics data utilizing specialized graphics hardware, such as the parallel processing unit 802a, without requiring the programmers to utilize the specific instruction set of the parallel processing unit 802a. The application program can include API calls that are routed to the device driver of the parallel processing unit 802a. The device driver interprets the API calls and performs various operations in response to the API calls. In some cases, the device driver can perform operations by executing instructions on the CPU. In other cases, the device driver can perform operations at least partially by initiating operations on the parallel processing unit 802a utilizing an input / output interface between the CPU and the parallel processing unit 802a. In one embodiment, the device driver is configured to utilize the hardware of the parallel processing unit 802a to implement the graphics processing pipeline 1400.

[0169] Various programs can be executed within the parallel processing unit 802a in order to implement various stages of the graphics processing pipeline 1400. For example, a device driver can launch a kernel on the parallel processing unit 802a to execute the vertex shading 1406 stage of the graphics processing pipeline 1400 on one streaming multi-processor 1100 (or multiple streaming multi-processor 1100 modules). The device driver (or initial kernel executed by the parallel processing unit 802a) can also launch further kernels on the parallel processing unit 802a to execute other stages of the graphics processing pipeline 1400, such as the geometry shading 1410 and fragment shading 1416 stages. In addition, some of the stages of the graphics processing pipeline 1400 can be implemented on fixed function hardware, such as a rasterizer or a data assembler implemented within the parallel processing unit 802a. It will be appreciated that the results of a stage, before being processed by a subsequent stage, can be stored in memory such as one or more of the shared memory 802b, the local memory 802c, or the system memory 810.

[0170] List of Drawing Elements

[0171] 300 circuit layout router

[0172] 302 layout with device placement

[0173] 304 genetic router

[0174] 306 candidate routed layout

[0175] 308 reinforcement learning model

[0176] 310 DRC corrected routed layout

[0177] 312 final routed layout

[0178] 400 incremental routing process

[0179] 402 block

[0180] 404 block

[0181] 406 block

[0182] 500 simulated annealing placement program

[0183] 502 block

[0184] 504 block

[0185] 506 block

[0186] 508 block

[0187] 600 genetic routing algorithm

[0188] 700 reinforcement learning artificial neural network

[0189] 702 convolution layer

[0190] 704 state embedding

[0191] 706 state value network

[0192] 708 policy network

[0193] 710 collected outputs

[0194] 712 action mask

[0195] 714 masked outputs

[0196] 716 soft max layer

[0197] 718 action policy

[0198] 720 pooling layer

[0199] 722 vector

[0200] 800 computing system

[0201] 802a parallel processing unit

[0202] 802b parallel processing unit

[0203] 802c parallel processing unit

[0204] 802d parallel processing unit

[0205] 804 I / O unit

[0206] 806 front end unit

[0207] 808 scheduler unit

[0208] 810 work distribution unit

[0209] 812 hub

[0210] 814 crossbar

[0211] 816 NV link

[0212] 818 interconnect

[0213] 820 memory

[0214] 900 general processing cluster

[0215] 902 pipeline manager

[0216] 904 pre-raster operations unit

[0217] 906 raster engine

[0218] 908 Work Assignment Cross Switch

[0219] 910 Memory Management Unit

[0220] 912 Data Processing Cluster

[0221] 914 Metaverse Engine

[0222] 916 M Pipe Controller

[0223] 1000 memory partition units

[0224] 1002 Raster Operation Unit

[0225] 1004 L2 cache

[0226] 1006 Memory Interface

[0227] 1100 Streaming Multiprocessors

[0228] 1102 Instruction Cache

[0229] 1104 Scheduler Unit

[0230] 1106 Register File

[0231] 1108 Core

[0232] 1110 Special Function Unit

[0233] 1112 Load / Storage Unit

[0234] 1114 Interconnection Network

[0235] 1116 Shared memory / L1 cache

[0236] 1118 Distribution

[0237] 1200 processing system

[0238] 1202 Central Processing Unit

[0239] 1204 switch

[0240] 1206 Parallel Processing Module

[0241] 1300 Exemplary Processing System

[0242] 1302 Communication Bus

[0243] 1304 Main Memory

[0244] 1306 Input Device

[0245] 1308 Display Device

[0246] 1310 network interface

[0247] 1400 graphics processing pipeline

[0248] 1402 output data

[0249] 1404 data assembly

[0250] 1406 vertex shading

[0251] 1408 primitive assembly

[0252] 1410 geometry shading

[0253] 1412 viewport SCC

[0254] 1414 rasterization

[0255] 1416 fragment shading

[0256] 1418 raster operations

[0257] 1420 input data

[0258] The different functional operations described herein can be implemented in logic that performs the recited operations or functions. For example, an association operation can be performed by an "associator" or an "associator." Likewise, a switch operation can be performed by a "switcher," a selection operation can be performed by a "selector," etc. Logic is specially configured or constructed, through its materials and / or material energy configuration, to include control and / or process signals, and / or settings and values (such as resistors, impedances, capacitances, inductances, currents / voltage ratings, etc.) that can be applied to affect the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and non-volatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (however, machine memory including software and thereby forming a material configuration is not excluded).

[0259] Within the present disclosure, different entities (which can variously be referred to as “units,” “circuits,” other components, etc.) can be described or claimed as “configured” to perform one or more tasks or operations. Such a configuration— e.g., a “configured” entity— is intended to refer to structure (i.e., that which is physically instantiated). More specifically, such a “configured” entity is intended to refer to structure that is arranged to perform one or more tasks during operation. An entity can be said to be “configured to” perform some task where, for example, the entity is in a physical configuration intended to carry out the task. A “credit allocation circuit configured to allocate credits to a plurality of processor cores” is intended to cover, for example, an integrated circuit having circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as “configured to” perform some task is intended to refer to a physical entity that is physically configured to perform the task. This phrase is not used herein to refer to software or firmware configured to perform the task, although a physical entity configured to perform some task necessarily has software or firmware configured to make the physical entity so configured.

[0260] The term “configured” is used herein to refer to a physical arrangement of structure that is intended to perform some task or tasks. For example, an FPGA that is programmed to perform some task is said to be “configured to” perform that task, even if the FPGA is not currently being used (e.g., a power supply is not connected to it). Thus, the term “configured” is used herein to refer to a physical arrangement of structure that is intended to perform some task or tasks.

[0261] A structure recited in a claim as “configured to” perform one or more tasks is expressly

[0262] As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose additional factors that can affect a determination. That is, a determination can be solely based on specified factors or based on specified factors and other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that affects the determination of A. This phrase does not foreclose the determination of A from also being based on some other factor, such as C. This phrase also allows for a determination of A to be based on B alone. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”

[0263] As used herein, the phrase "in response to" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors can influence or otherwise trigger the recited effect. That is, the effect can be in response to only those factors, or can be in response to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." This phrase specifies that B is a factor that triggers the performance of A. This phrase does not exclude the possibility that A can also be performed in response to some other factor, e.g., C. The phrase is intended to cover both embodiments in which A is performed exclusively in response to B, and embodiments in which A is performed in response to a combination of B and some other factor.

[0264] As used herein, the terms "first," "second," and the like, are used as labels for nouns that they precede, and do not necessarily describe any type of chronology or order unless specifically stated to do so. For example, in a register file having eight registers, the terms "first register" and "second register" can be used to refer to any two of the eight registers, not just, for example, logical registers 0 and 1.

[0265] The term "or" as used in a claim is used as an inclusive or and not as an exclusive or. For example, the phrase "at least one of x, y, or z" means any one of x, y, and z, as well as any combination thereof.

[0266] As used herein, recitations of "and / or" in reference to two or more elements should be interpreted as meaning only one element or a combination of the elements. For example, "element A, element B, and / or element C" can include just element A, just element B, just element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. Further, "at least one of element A or element B" can include at least one of element A, at least one of element B, or at least one of each of element A and element B. Further still, "at least one of element A and element B" can include at least one of element A, at least one of element B, or at least one of each of element A and element B.

[0267] The subject matter of the present disclosure is now specifically described in order to meet statutory requirements. However, this description in no way serves to limit the scope of the present disclosure. Rather, the inventors have contemplated that the claimed subject matter can also be embodied in other specific forms without departing from the spirit or essential characteristics thereof. To clearly ascertain the scope of the claimed subject matter, reference is made to the appended claims, along with their full scope of equivalents. Furthermore, the terms "step" and / or "block" as used herein encompasses any appropriately designed processes known to those of ordinary skill in the art.

[0268] Having thus described in detail preferred embodiments of the application, it will be apparent to those skilled in the art that modifications and variations are possible without departing from the scope of the application as claimed. The scope of the inventive subject matter is not to be limited, however, to the specific embodiments presented herein, but includes whatever falls within the scope of the appended claims.

Claims

1. A method for routing of a circuit layout, the method comprising: executing a genetic routing algorithm to generate a route in the circuit layout; applying a reinforcement learning model to correct design rule constraint errors caused by the route; and applying a plurality of uncorrected design rule constraint errors to evolve a chromosome of the genetic routing algorithm.

2. The method of claim 1, further comprising: executing a simulated annealing algorithm to perform device placement in the circuit layout.

3. The method of claim 1, further comprising applying a plurality of unrouted terminal pairs to evolve the genetic routing algorithm.

4. The method of claim 1, wherein, the reinforcement learning model comprises a convolutional neural network that generates an embedding for at least one policy neural network and a state value neural network.

5. The method of claim 4, wherein, the at least one policy neural network comprises a plurality of fully connected layers and an operation mask.

6. The method of claim 4, wherein, the state value neural network comprises a plurality of fully connected layers.

7. The method of claim 1, further comprising: the reinforcement learning model receives an image of a stick figure of the circuit layout; and the reinforcement learning model converts the image into an action probability and a state value.

8. The method of claim 7, wherein, the conversion into the action probability and the state value is invariant with respect to a width of the stick figure.

9. The method of claim 1, wherein, a fitness function of the genetic routing algorithm comprises a weighted sum of a number of unrouted terminal pairs in the route and a number of the design rule constraint errors in the route.

10. A system comprising: one or more processors; and logic which, when applied to the one or more processors, then: operates a simulated annealing algorithm to perform device placement on a circuit layout; operates a genetic routing algorithm on the circuit layout to generate a plurality of candidate routed circuit layouts; operates a reinforcement learning model to correct design rule constraint errors in the candidate routed circuit layouts; and applies feedback of a plurality of uncorrected design rule constraint errors in a fitness function to evolve a chromosome of the genetic routing algorithm. the design rule constraint errors are applied to a fitness function of the genetic routing algorithm.

11. The system of claim 10, wherein, a plurality of unrouted terminal pairs are also applied to the fitness function of the genetic routing algorithm.

12. The system of claim 11, wherein, the reinforcement learning model comprises a convolutional neural network and a state value neural network that generates an embedding for a plurality of policy neural networks.

13. The system of claim 10, wherein, the policy neural networks comprise a plurality of fully connected layers and an operation mask.

14. The system of claim 13, wherein, 15. The system of claim 13, further comprising: a pooling layer; and the state value neural network comprises a plurality of fully connected layers coupled to receive an output of the pooling layer.

16. The system of claim 10, the reinforcement learning model configured to: receive an image of a stick figure of the candidate routed circuit layout; and convert the image of the stick figure into an action probability for correcting the design rule constraint errors. the conversion into the action probability is invariant with respect to a width of the image of the stick figure.

18. The system of claim 10, the genetic routing algorithm further comprising:

17. The system of claim 16, wherein, ​ ​ a fitness function comprising an inverse of a weighted sum of a number of unrouted terminal pairs in the candidate routed circuit layout and a number of design rule constraint errors in the candidate routed circuit layout.

19. An artificial neural network comprising: a convolutional neural network coupled to receive a circuit layout image from a genetic router; the convolutional neural network configured to convert the circuit layout image into an embedding to a plurality of policy neural networks and a state value neural network; and the plurality of policy neural networks configured to transform the embedding into action probabilities for correcting design rule constraint errors in the circuit layout image, wherein a plurality of uncorrected design rule constraint errors are returned to the genetic router to evolve a chromosome of a genetic routing algorithm.

20. The artificial neural network of claim 19, further comprising: the state value neural network configured to convert the embedding into a state vector.

Images