A layout implementation method for local dynamic reconfiguration

Abstract

The present invention provides a layout implementation method for local dynamic reconfiguration. The method is implemented by using a filling-type local dynamic reconfiguration layout tool, and specifically includes a main process and a reconfiguration process. The main process includes five steps: compilation and synthesis, boundary identification, layout, routing, and bit stream generation; the reconfiguration process includes five steps: compilation and synthesis, reading boundary information output by the main process, layout, routing, and bit stream generation. The present invention solves the problems of complex design schemes, long development cycles, and high maintenance costs caused by the use of incremental compilation for local dynamic reconfiguration in the prior art, by performing boundary identification before layout of the main process and reading boundary identification information in the reconfiguration process to perform layout and routing of the reconfiguration process. The method avoids the problem of difficulty in implementing local dynamic reconfiguration caused by the lack of support for incremental compilation functions by EDA tools in the early stages of design.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and relates to a layout technology of a programmable logic device chip integrated circuit software tool in an integrated circuit, and in particular to a layout implementation method of local dynamic reconfiguration. Background Art

[0002] Local dynamic reconfiguration involves reconfiguring parts of the logic in a programmable logic device (PLD) chip while the logic is operating normally. This is achieved by using EDA (Electronic Design Automation) software tools that support local upgrades of the PLD chip based on existing layout and routing results.

[0003] In the existing technology, local dynamic reconfiguration is completed using incremental compilation. Incremental compilation is a complex project throughout the entire process, with the disadvantages of complex design schemes, long development cycles, and high maintenance costs. Moreover, if the EDA software tool does not support incremental compilation function in the early design stage, then the local dynamic reconfiguration function will be even more difficult to implement, and it will also cause performance fluctuations in the tool. Summary of the Invention

[0004] The problem solved by the present invention is to provide a layout implementation method for local dynamic reconfiguration, which solves the problems of complex design schemes, long development cycles and high maintenance costs caused by local dynamic reconfiguration through incremental compilation in the prior art, and avoids the problem that local dynamic reconfiguration is more difficult to implement due to the fact that EDA tools do not support incremental compilation functions in the early stage of design.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] 1. A method for implementing a layout of a local dynamic reconfiguration, characterized in that the method is implemented using a filling-type local dynamic reconfiguration layout tool, the filling-type local dynamic reconfiguration tool comprising:

[0007] The main process is used to compile the complete logic function of the programmable logic device chip for the first time; and

[0008] The reconfiguration process is used to separately compile the reconfiguration function when reconfiguring part of the logic of the programmable logic device chip.

[0009] Furthermore, the main process includes:

[0010] Step 101: Compile and synthesize: convert the logic functions written in the hardware description language in the user's initial design file into logic units defined by the manufacturer;

[0011] Step 103: Boundary identification: This is used to analyze the logical units compiled and synthesized in step 101, redefine the boundaries, and identify the boundaries between static logic and dynamic logic. The dynamic logic is the functional modules marked by the user for future reconfiguration, and the static logic is the functional modules not marked by the user.

[0012] Step 104: Layout: Mapping the logic cells in the user design file after boundary identification in step 103 to a physical location on the programmable logic device chip;

[0013] Step 105: Wiring: Based on the layout results, the signal paths between the logic units are opened up through the algorithm;

[0014] Step 106: Generate bitstream: Generate a configuration file, ie, a bitstream file, for the programmable logic device chip according to the result of the placement and routing.

[0015] Furthermore, after the step 101 compilation and synthesis step and before the step 103 boundary identification step, the step 102 logic mapping is also included: converting the user-oriented highly abstract logic unit in the logic unit compiled and synthesized in step 101 into a lightly abstract logic unit oriented to the algorithm, and then outputting the converted logic unit to step 103 boundary identification.

[0016] Furthermore, the boundary identification in step 103 further includes:

[0017] Traverse all logic signals in the user design file. If the logic unit at one end of the logic signal has a user mark, while the logic unit at the other end does not have a user mark, then the logic signal is the boundary to be identified, that is, the dynamic and static logic boundary.

[0018] Furthermore, the main process also includes the step of outputting boundary information, specifically:

[0019] The physical location information generated when the routing path of the boundary signal crosses the boundary of the dynamic area is the boundary information. The main process outputs the physical location information to the reconfiguration process after the routing step in step 105.

[0020] Furthermore, the reconfiguration process includes:

[0021] Step 201 compiles and synthesizes: converts the logic functions written in the hardware description language in the reconfiguration file in the user's initial design file into the manufacturer-defined logic units;

[0022] Step 203: The reconfiguration process reads the boundary information output by the main process and establishes an anchor point based on the boundary information;

[0023] Step 204: Layout: Map the logic unit compiled and synthesized in step 201 to a physical location on the programmable logic device chip; perform layout based on the guidance of the anchor points established in step 203;

[0024] Step 205: Routing: Based on the layout results, signal paths between logic units are opened according to the boundary information provided in step 203;

[0025] Step 206 generates a bitstream: generating a configuration file, namely a bitstream file, for the programmable logic device chip according to the placement and routing results.

[0026] Furthermore, after the step 201 compilation and synthesis step and before the step 203 layout step, the step 202 logic mapping is also included: converting the user-oriented highly abstract logic units in the logic units compiled and synthesized in step 201 into algorithm-oriented lightly abstract logic units, and then outputting the converted logic units to step 204 layout.

[0027] The beneficial effects of the present invention are:

[0028] The present invention provides a layout implementation method for local dynamic reconfiguration. In the main process of programmable logic device chip compilation, boundary identification is performed before layout begins. After layout is completed, boundary information from boundary identification is output to the reconfiguration process. This allows the reconfiguration process to read the boundary information before layout and routing, utilize the boundary information to obtain better layout and routing results, and complete local dynamic reconfiguration during the programmable logic device chip compilation process. Compared to existing incremental compilation, the present invention reduces the design complexity of local dynamic reconfiguration layout, shortens the development cycle, reduces maintenance costs, and avoids the problem of local dynamic reconfiguration being more difficult to implement due to EDA tools not supporting incremental compilation in the early stages of design. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 This is a flowchart of the main process and the reconfiguration process

[0031] Figure 2 is the boundary graph of the boundary identification process

[0032] Figure 3 It is the boundary information map output by the main process

[0033] Figure 4It is the anchor graph established by the reconfiguration process based on the boundary information output by the main process

[0034] Figure 5 It is a timing diagram without establishing an anchor point for reconfiguration process layout DETAILED DESCRIPTION

[0035] A layout implementation method for local dynamic reconfiguration according to an embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0036] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0037] The embodiment of the present invention provides a layout implementation method for local dynamic reconfiguration, the specific solution is as follows:

[0038] The method is implemented using a filling-type local dynamic reconfiguration layout tool, which includes:

[0039] The main process is used to compile the complete logic function of the programmable logic device chip for the first time; and

[0040] The reconfiguration process is used to separately compile the reconfiguration function when reconfiguring part of the logic of the programmable logic device chip.

[0041] Furthermore, the main process includes:

[0042] Step 101 compiles and synthesizes: converts the logic functions written in the hardware description language in the user's initial design file into manufacturer-defined logic units. This conversion process is a common process of EDA software tools and belongs to the existing technology, so it will not be described in detail here.

[0043] Step 103 Boundary Identification: This is used to analyze the logic units compiled and synthesized in step 101, redefine the boundaries, and identify the boundaries between static logic and dynamic logic. Before using the local dynamic reconfiguration function, the user has already identified the functional modules that need to be reconfigured, and will use the interface provided by the EDA tool to mark the functional modules that need to be reconfigured. The functional modules marked by the user are dynamic logic, and the functional modules not marked by the user are static logic.

[0044] Step 104: Layout: Map the logic cells in the user design file after the boundary identification in step 103 to a physical location on the programmable logic device chip. The implementation of this process is an important step in the EDA tool and belongs to the existing technology, so it will not be described in detail here.

[0045] Step 105: Wiring: Based on the layout results, the signal paths between the logic units are opened up through the algorithm. The algorithm is not the focus of this solution and can be implemented through existing technologies. This solution is mainly an improvement on the existing technical solutions.

[0046] Step 106: Generate bitstream: Generate a configuration file, ie, a bitstream file, for the programmable logic device chip according to the result of the placement and routing.

[0047] Furthermore, after step 101 of compilation and synthesis and before step 103 of boundary identification, the process also includes step 102 of logic mapping: converting the highly abstract user-oriented logic units in the logic units compiled and synthesized in step 101 into lightly abstract algorithm-oriented logic units, and then outputting the converted logic units to step 103 of boundary identification. This step improves user convenience throughout the entire programmable logic device chip process and conciseness of the programmable logic device chip algorithm. However, this step is not essential to the entire process and can be omitted. Whether it appears in the process depends on the manufacturer's modeling strategy.

[0048] Furthermore, the boundary identification in step 103 further includes:

[0049] Traverse all logic signals in the user design file. If the logic unit at one end of the logic signal has a user mark, while the logic unit at the other end does not have a user mark, then the logic signal is the boundary to be identified, that is, the dynamic and static logic boundary.

[0050] like Figure 2 As shown, the white circle represents the dynamic logic unit marked by the user, the black circle is the static logic unit, and the dotted line in the middle is the boundary.

[0051] Furthermore, the main process also includes the step of outputting boundary information, specifically:

[0052] The physical location information generated when a boundary signal's routing path crosses a dynamic region boundary is called boundary information. The main process outputs this physical location information to the relocation process after the routing step in step 105. In the local dynamic relocation function, dynamic logic and static logic are physically separated. The user-specified layout area for dynamic logic is called the dynamic region. The physical location information generated when a boundary signal's routing path crosses a dynamic region boundary is called physical location information, or boundary information.

[0053] like Figure 3As shown in the figure, the dotted grid constitutes the coordinate system of the programmable logic device chip resources. The black-bordered rectangle is the dynamic area, the white circle represents dynamic logic, the black circle represents static logic, the dotted arrow represents the signal at the boundary of dynamic and static logic, and the coordinate position marked by the shaded mark is the physical position information generated when the boundary signal crosses the boundary of the dynamic area.

[0054] Furthermore, the reconfiguration process includes:

[0055] Step 201 compiles and synthesizes: converts the logic functions written in the hardware description language in the reconfiguration file in the user's initial design file into the manufacturer-defined logic units. This conversion process is a common process of EDA software tools and belongs to the existing technology, so it will not be described in detail here.

[0056] Step 203: The reconfiguration process reads the boundary information output by the main process and establishes an anchor point based on the boundary information;

[0057] like Figure 4 As shown in the figure, the black circles represent the anchor points established based on the boundary information generated by the main process, and the white circles represent the dynamic logic. If there is no guidance from the anchor points, according to the layout optimization goal of the shortest line length, the white circles in the figure will be squeezed together in the center of the dynamic area, causing increased signal delay and timing failure. Figure 5 The dotted arrow part.

[0058] Step 204: Layout: The logic units compiled and synthesized in step 201 are laid out according to the guidance of the anchor points established in step 203. The implementation of the specific layout process is an important step of the EDA tool and belongs to the existing technology, so it will not be described in detail here.

[0059] Step 205: Wiring: Based on the layout results, the signal paths between the logic units are opened up through an algorithm according to the boundary information provided in step 203. The algorithm is not the focus of this solution and can be implemented through existing technologies. This solution is mainly an improvement on existing technical solutions.

[0060] Step 206 generates a bitstream: generating a configuration file, namely a bitstream file, for the programmable logic device chip according to the placement and routing results.

[0061] Furthermore, after the compilation and synthesis step 201 and before the layout step 203, the process also includes step 202: logic mapping, which converts the highly abstract user-oriented logic units in the compiled and synthesized logic units of step 201 into lightly abstract algorithm-oriented logic units. The converted logic units are then output to the layout step 204. This step improves user convenience throughout the entire programmable logic device chip process and simplifies the programmable logic device chip algorithm. However, this step is not essential to the entire process and can be omitted. Whether it appears in the process depends on the manufacturer's modeling strategy.

[0062] The above content is a further detailed description of the present invention in conjunction with specific embodiments, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For those skilled in the art of the present invention, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be considered as the scope of protection of the present invention.

Claims

1. A layout implementation method for local dynamic reconfiguration, characterized in that: The method is implemented using a filling-type local dynamic reconfiguration layout tool, which includes: The main process is used to compile the complete logic function of the programmable logic device chip for the first time; and Reconfiguration process, used to compile reconfiguration functions separately when reconfiguring part of the logic of a programmable logic device chip; The main process includes: Step 101: Compile and synthesize: convert the logic functions written in the hardware description language in the user's initial design file into logic units defined by the manufacturer; Step 103: Boundary identification: This is used to analyze the logical units compiled and synthesized in step 101, redefine the boundaries, and identify the boundaries between static logic and dynamic logic. The dynamic logic is the functional modules marked by the user for future reconfiguration, and the static logic is the functional modules not marked by the user. Step 104: Layout: Mapping the logic cells in the user design file after boundary identification in step 103 onto the programmable logic device chip; Step 105: Wiring: Based on the layout results, the signal paths between the logic units are opened up through the algorithm; Step 106: Generate bitstream: Generate a configuration file, i.e., a bitstream file, for the programmable logic device chip based on the result of the layout and routing; The boundary identification step 103 further includes: Traverse all logic signals in the user design file. If the logic unit at one end of the logic signal has a user mark, while the logic unit at the other end does not have a user mark, then the logic signal is the boundary to be identified, that is, the dynamic and static logic boundary; The main process also includes the step of outputting boundary information, specifically: The physical location information generated when the routing path of the boundary signal crosses the boundary of the dynamic area is the boundary information. The main process outputs the physical location information to the reconfiguration process after the routing step in step 105; The reconfiguration process separately compiles the reconfiguration function according to the boundary information when reconfiguring part of the logic.

2. The layout implementation method of local dynamic reconfiguration according to claim 1, characterized in that: After the step 101 compilation and synthesis step and before the step 103 boundary identification step, the step 102 logic mapping is also included: converting the user-oriented highly abstract logic unit in the logic unit compiled and synthesized in step 101 into the algorithm-oriented lightly abstract logic unit, and then outputting the converted logic unit to step 103 boundary identification.

3. The layout implementation method of local dynamic reconfiguration according to claim 1, characterized in that: The reconfiguration process includes: Step 201 compiles and synthesizes: converts the logic functions written in the hardware description language in the reconfiguration file in the user's initial design file into the manufacturer-defined logic units; Step 203: The reconfiguration process reads the boundary information output by the main process and establishes an anchor point based on the boundary information; Step 204: Layout: Map the logic unit compiled and synthesized in step 201 to a physical location on the programmable logic device chip; perform layout based on the guidance of the anchor points established in step 203; Step 205: Routing: Based on the layout results, signal paths between logic units are opened according to the boundary information provided in step 203; Step 206 generates a bitstream: generates a configuration file, namely a bitstream file, for the programmable logic device chip according to the placement and routing results.

4. The layout implementation method of local dynamic reconfiguration according to claim 3, characterized in that: After the step 201 compilation and synthesis step and before the step 203 layout step, the process further includes step 202 logic mapping: converting the user-oriented highly abstract logic units in the logic units compiled and synthesized in step 201 into algorithm-oriented lightly abstract logic units, and then outputting the converted logic units to step 204 layout.

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