Data processing device, data driving device, and display device

Abstract

A data processing device, a data driving device, and a display device are provided. According to an embodiment, both high-speed communication and low-speed communication are performed using a single communication line, thereby reducing restrictions on wiring on a PCB and improving the utilization efficiency of a transmission line.

Description

Technical Field

[0001] This disclosure relates to a technique for driving a display device. Background Technology

[0002] Typically, the display panel of a display device consists of multiple pixels arranged in a matrix, and each pixel is composed of red (R), green (G), and blue (B) sub-pixels. Furthermore, an image is displayed on the display panel while each sub-pixel emits light at a grayscale corresponding to the image data.

[0003] Here, the display device may include a data processing unit called a timing controller and a data driving unit called a source driver, and image data is sent from the data processing unit to the data driving unit. The image data is sent as a digital signal, and the data driving unit converts the image data received as a digital signal into analog voltages to drive individual pixels.

[0004] On the other hand, the data processing unit and the data driving unit can perform data communication at a single clock frequency. The data processing unit and the data driving unit can consist of communication circuitry optimized for a single clock frequency. Since the communication circuitry primarily supports high-speed communication, the data processing unit and the data driving unit can also be optimized for high-speed communication.

[0005] However, since data processing devices and data driving devices optimized for high-speed communication only support high-speed communication, it may be difficult to perform both high-speed and low-speed communication.

[0006] In this regard, this embodiment provides a technology for a data processing apparatus and a data driving apparatus capable of performing both low-speed and high-speed communication using a single line. Summary of the Invention

[0007] In this context, one aspect of the present disclosure is to provide a technique for configuring a communication circuit to receive image data upon receiving a first mode signal having a first frequency, and for controlling the communication circuit to terminate the configuration upon receiving a second mode signal having a second frequency lower than the first frequency.

[0008] Another aspect of this disclosure is to provide a technique for performing both high-speed and low-speed communication using a single communication line.

[0009] To this end, in one aspect, this disclosure provides a data driving device for configuring a communication circuit to receive image data before receiving the image data. The data driving device may include: an identification circuit configured to receive a first mode signal having a first frequency and a second mode signal having a second frequency different from the first frequency, and to distinguish between the first mode signal and the second mode signal; and a control circuit configured to configure the communication circuit upon receiving the first mode signal and to terminate the configuration of the communication circuit upon receiving the second mode signal. The data driving device may further include an oscillator configured to generate a counting clock for counting the clock signals. The identification circuit further includes a frequency divider and a counter. The frequency divider is configured to generate a first divided clock from the first mode signal and a second divided clock from the second mode signal. The counter is configured to use the counting clock to count the first divided clock and the second divided clock to generate a first count value and a second count value, respectively. The control circuit identifies the first mode signal and the second mode signal based on the first count value and the second count value, respectively.

[0010] The first count value may be less than the second count value.

[0011] The control circuit can receive a count value generated from the counter, and determine the count value as the first count value or the second count value if the count value is within a predetermined range.

[0012] The control circuit can receive multiple count values ​​and determine the count value that is repeated consecutively among the multiple count values ​​as the first count value or the second count value.

[0013] The communication circuit can perform high-speed data communication according to the first protocol and low-speed data communication according to the second protocol through the same communication line.

[0014] The identification circuit can operate in the high-speed data communication rather than in the low-speed data communication.

[0015] The data driving device may further include a lock control circuit configured to generate a lock signal indicating the state of a clock used for the high-speed data communication, and to change the voltage level of the lock signal in the event of a clock interruption, wherein, if the voltage level of the lock signal changes after clock training is completed in the high-speed data communication, the control circuit changes the mode from a mode for the high-speed data communication to a mode for the low-speed data communication.

[0016] Upon receiving the first mode signal, the control circuit can set the communication frequency of the communication circuit to the first frequency, and upon receiving the second mode signal, the control circuit terminates the setting of the communication frequency.

[0017] The data driving device may further include an equalizer, wherein, upon receiving the second mode signal, the control circuit terminates the setting of the communication frequency of the communication circuit and begins to change the configuration of the equalizer.

[0018] If the second mode signal is not received within a predetermined time, the control circuit may enter a display mode for receiving the image data.

[0019] In another aspect, this disclosure provides a data processing apparatus for preparing the transmission of image data in a preparation mode prior to a display mode for transmitting image data to a data driving device. The data processing apparatus includes a transmission circuit configured to transmit a signal comprising a first mode signal having a first frequency and a second mode signal having a second frequency different from the first frequency to the data driving device, wherein the data driving device optimizes the configuration of a communication circuit according to the signal, the first mode signal indicating the start of the signal and the second mode signal indicating the end of the signal.

[0020] The preparation mode may include a high-speed mode and a low-speed mode. In the high-speed mode, high-speed data communication according to a first protocol is enabled between the data processing device for transmitting the image data and the data driving device for receiving the image data. In the low-speed mode, low-speed data communication according to a second protocol different from the first protocol is enabled. The data processing device may also include an oscillator configured to generate a clock for synchronizing the image data in the high-speed mode.

[0021] The data processing device may further include a control circuit configured to convert the image data into a serial form and encode the first mode signal or the second mode signal into a DC balanced code.

[0022] In another aspect, this disclosure provides a display device, comprising: a data processing device configured to transmit an equalizer training signal, i.e., an EQ training signal, including a first mode signal having a first frequency and a second mode signal having a second frequency different from the first frequency; and a data driving device including an equalizer, the data driving device being configured to receive the first mode signal and the second mode signal, to begin testing a configuration of the equalizer upon identification of the first mode signal, and to terminate testing the configuration of the equalizer upon identification of the second mode signal.

[0023] The data processing device can send the EQ training signal in multiple time periods, and the data driving device can perform tests on various configurations by changing the configuration of the equalizer in each time period.

[0024] The EQ training signal may include pseudo-random binary sequence data, i.e., PRBS data, and the data driving device calculates the bit error rate of the PRBS data and evaluates the performance of the equalizer configuration based on the bit error rate.

[0025] Upon identifying the final second mode signal, the data driving device can terminate the test of the equalizer.

[0026] If the first mode signal is not identified within a predetermined time, the data driving device may enter a display mode for receiving image data.

[0027] If the second mode signal is not identified within a predetermined time, the data driving device may enter a display mode for receiving image data and output a lock signal indicating unlocking.

[0028] As described above, according to this disclosure, the limitations on PCB routing can be reduced by using a single communication line to perform both high-speed and low-speed communication. Furthermore, according to this disclosure, the utilization efficiency of the transmission line can be improved by using a single communication line to perform both high-speed and low-speed communication. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0030] Figure 2 This is a block diagram illustrating a system according to an embodiment.

[0031] Figure 3 This is a diagram illustrating a coupling capacitor disposed in a first communication line according to an embodiment.

[0032] Figure 4This is an example diagram illustrating a signal sequence for pre-clock training between a data processing apparatus and a data driving apparatus according to an embodiment.

[0033] Figure 5 This is an example diagram illustrating a signal sequence for illustrating EQ training between a data processing apparatus and a data driving apparatus according to an embodiment.

[0034] Figure 6 This is an example diagram illustrating a signal sequence in an automatic training mode between a data processing apparatus and a data driving apparatus according to an embodiment.

[0035] Figure 7 This is an example diagram illustrating signals including a first mode signal and a second mode signal according to an embodiment.

[0036] Figure 8 This is a block diagram illustrating a data processing apparatus and a data driving apparatus according to an embodiment.

[0037] Figure 9 This is a diagram illustrating the identification of a first mode signal and a second mode signal by a counter according to an embodiment.

[0038] Figure 10 This is a diagram illustrating the operation of a clock recovery circuit based on a signal sequence between a data processing device and a data driving device according to an embodiment.

[0039] Figure 11 This is a flowchart illustrating the operation of a data driving device based on a signal sequence between a data processing device and a data driving device according to an embodiment. Detailed Implementation

[0040] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0041] refer to Figure 1 The display device 100 may include a panel 110, a data driving device 120, a gate driving device 130, and a data processing device 140.

[0042] On panel 110, multiple data lines DL and multiple gate lines GL can be arranged, and multiple pixels can be arranged. A pixel can be composed of multiple sub-pixels SP. Here, sub-pixels can be red (R), green (G), blue (B), white (W), etc. A pixel can be composed of RGB sub-pixels SP, RGBG sub-pixels SP, or RGBW sub-pixels SP. Hereinafter, for ease of description, we will describe a pixel as being composed of RGB sub-pixels.

[0043] The data driving device 120, the gate driving device 130, and the data processing device 140 are devices for generating signals for displaying images on the panel 110.

[0044] The gate driving device 130 can supply a gate driving signal with an on or off voltage to the gate line GL. When the gate driving signal with an on voltage is supplied to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. Subsequently, when the gate driving signal with an off voltage is supplied to the sub-pixel SP, the connection between the sub-pixel SP and the data line DL is released. The gate driving device 130 may be referred to as a gate driver.

[0045] The data driving device 120 can supply a data voltage Vp to the sub-pixel SP via the data line DL. The data voltage Vp supplied to the data line DL can be supplied to the sub-pixel SP according to the gate driving signal. The data driving device 120 can be referred to as a source driver.

[0046] The data driving device 120 may include at least one integrated circuit, which may be of the tape-on-bond (TAB) type or the glass-on-chip (COG) type. According to an embodiment, the at least one integrated circuit may be connected to a bonding pad of the panel 110 or formed directly on the panel 110, or may be integrated onto the panel 110. Furthermore, the data driving device 120 may be implemented as a thin-film-on-chip (COF) type. The data processing device 140 may supply control signals to the gate driving device 130 and the data driving device 120. For example, the data processing device 140 may send a gate control signal GCS to the gate driving device 130 for starting scanning. Furthermore, the data processing device 140 may output image data to the data driving device 120. And, the data processing device 140 may send a data control signal for controlling the data driving device 120 to supply a data voltage Vp to each sub-pixel SP. The data processing device 140 may be referred to as a timing controller.

[0047] Figure 2 This is a block diagram illustrating a system according to an embodiment.

[0048] refer to Figure 2 The system 200 may include at least one data processing device 140 and a plurality of data driving devices 120a, 120b, 120c and 120d.

[0049] The data processing device 140 can be disposed on the first printed circuit board (PCB1). In addition, the data processing device 140 can be connected to a plurality of data driving devices 120a, 120b, 120c and 120d via the first communication line LN1 and the second communication line LN2.

[0050] The first communication line LN1 and the second communication line LN2 can reach multiple data drive devices 120a, 120b, 120c and 120d via the first PCB PCB1 and the second PCB PCB2.

[0051] The first PCB PCB1 and the second PCB PCB2 can be connected by a first membrane FL1 made of flexible material, and the first communication line LN1 and the second communication line LN2 can extend from the first PCB PCB1 to the second PCB PCB2 via the first membrane FL1.

[0052] Each of the data drive devices 120a, 120b, 120c, and 120d can be arranged on the second film FL2 in the form of a chip-on-film (COF). The second film FL2 can be a support substrate made of flexible material connecting the second PCB PCB2 and the panel 110, and the first communication line LN1 and the second communication line LN2 can extend from the second PCB PCB2 to each of the data drive devices 120a, 120b, 120c, and 120d via the second film FL2.

[0053] The first communication line LN1 can be connected one-to-one between the data processing device 140 and the data driving devices 120a, 120b, 120c, and 120d. Furthermore, the second communication line LN2 can be connected to each of the data driving devices 120a, 120b, 120c, and 120d, or connected between the fourth data driving device 120d and the data processing device 140, without overlapping with the first communication line LN1 in the plan view. For example, the first data driving device 120a can be connected to the second data driving device 120b via the second communication line LN2, and the second data driving device 120b can be connected to the third data driving device 120c via the second communication line LN2.

[0054] Here, the second data drive device 120b and the third data drive device 120c can be connected to different second PCBs PCB2. Therefore, the second communication line LN2 arranged between the second data drive device 120b and the third data drive device 120c can connect the second data drive device 120b and the third data drive device 120c via the second PCB PCB2, the first film FL1, and the first PCB PCB1. The third data drive device 120c can be connected to the fourth data drive device 120d via the second communication line LN2, and the fourth data drive device 120d can be connected to the data processing device 140 via the second communication line LN2. As described above, the data processing device 140 can communicate with the data drive devices 120a, 120b, 120c, and 120d via the first communication line LN1 and the second communication line LN2.

[0055] Here, the communication frequency between the data processing device 140 and the data driving devices 120a, 120b, 120c, and 120d may not have been predetermined. In other words, the communication circuits of the data driving devices 120a, 120b, 120c, and 120d may not have been tuned to the communication frequency of the data processing device 140.

[0056] In this embodiment, the data driving devices 120a, 120b, 120c, and 120d can be configured to adjust the configuration values ​​of the communication circuit according to the communication frequency of the data processing device 140. The communication frequency can also be referred to as the clock frequency. The characteristics of the communication circuits of the data driving devices 120a, 120b, 120c, and 120d can be changed according to the communication frequency.

[0057] Figure 3 This is a diagram illustrating a coupling capacitor disposed in a first communication line according to an embodiment.

[0058] refer to Figure 3 The first communication line LN1 may include one or more AC coupling capacitors 301 and 302. Specifically, as Figure 3 As shown in (A), the first communication line LN1 may include a first line 310 having a first AC coupling capacitor 301 and a second line 320 having a second AC coupling capacitor 302.

[0059] like Figure 3 As shown in (B), the first line 310 may also include a third AC coupling capacitor 303, and the second line 320 may also include a fourth AC coupling capacitor 304.

[0060] In the case where the first line 310 also includes a third AC coupling capacitor 303, the first AC coupling capacitor 301 may be arranged in the first line 310 adjacent to the data processing device 140, and the third AC coupling capacitor 303 may be arranged in the first line 310 adjacent to the data driving device 120.

[0061] When the second line 320 also includes a fourth AC coupling capacitor 304, the second AC coupling capacitor 302 can be arranged in the second line 320 adjacent to the data processing device 140, and the fourth AC coupling capacitor 304 can be arranged in the second line 320 adjacent to the data driving device 120. By adding the third coupling capacitor 303 and the fourth coupling capacitor 304 to the first line 310 and the second line 320, the receiving performance of the data driving device 120 for low-speed communication can be further improved.

[0062] Figure 4This is an example diagram illustrating a signal sequence for pre-clock training between a data processing apparatus and a data driving apparatus according to an embodiment.

[0063] Reference Figure 4 The display device can operate in command mode, automatic training mode, and display mode. Command mode and automatic training mode are preparation modes, and the display device can prepare to send and receive image data.

[0064] In command mode, the display device can transmit configuration data for high-speed data communication during low-speed data communication. In automatic training mode, the display device can configure the communication circuitry of the data drive device to operate at a frequency enabling high-speed data communication between the data processing device and the data drive device. Additionally, in automatic training mode, the display device can configure an equalizer to improve signal quality.

[0065] When the drive voltage VCC is supplied to the data processing device and the data driving device, in command mode, the data processing device can send a second protocol signal PS2 to the data driving device. Next, the data processing device can send a first protocol signal PS1 in automatic training mode and display mode. The first protocol signal PS1 and the second protocol signal PS2 can be transmitted through the first communication line (…). Figure 3 The LN1 signal is transmitted. Here, the second protocol signal PS2 is a signal based on a second protocol established between the data processing device and the data driving device, and may be a signal according to a low-speed data communication protocol. The first protocol signal PS1 is a signal based on a first protocol established between the data processing device and the data driving device, and may be a signal according to a high-speed data communication protocol.

[0066] The communication frequency of the first protocol signal PS1 can be 10 times the communication frequency of the second protocol signal PS2. Based on these characteristics, the first protocol signal PS1 can be classified as a high-speed data communication protocol, and the second protocol signal PS2 can be classified as a low-speed data communication protocol. In the following text, to distinguish the communication frequencies of the first protocol signal PS1 and the second protocol signal PS2, the communication frequency of the first protocol signal PS1 will be referred to as the first communication frequency, and the communication frequency of the second protocol signal PS2 will be referred to as the second communication frequency.

[0067] In high-speed data communication, such as in automatic training mode or display mode, the data loss rate can vary significantly depending on the configuration of the receiving circuit. Alternatively, in high-speed data communication, communication may not be performed smoothly depending on the configuration of the receiving circuit. Therefore, the display device according to the embodiment can send configuration data from the transmitting side to the receiving side for smooth execution of high-speed data communication before performing the high-speed data communication. Such configuration data can be sent / received via low-speed data communication, such as in command mode. In low-speed data communication, since the data loss rate does not vary significantly depending on the configuration of the receiving circuit, configuration values ​​can be sent to the receiving circuit with relatively high precision.

[0068] Before sending the first protocol signal PS1 corresponding to high-speed data communication, the data processing device can send the configuration data required for high-speed data communication by sending the second protocol signal PS2 corresponding to low-speed data communication.

[0069] On the other hand, when the display device is in command mode, the preamble segment, CFG data segment, and CFG completion segment included in the second protocol signal PS2 can be used.

[0070] In the preamble section, the second protocol signal PS2 may include a low-speed data communication clock. The data driving device can use the low-speed data communication clock to train a corresponding clock, and can use the trained clock to receive low-speed data.

[0071] In the CFG data segment, the second protocol signal PS2 may include low-speed data. The data driver can receive low-speed data using the aforementioned clock (low-speed data communication clock). The low-speed data may include configuration data for the data driver performing high-speed data communication, such as equalizer gain settings, scrambling information, and line polarity information. The data driver can use the configuration data to configure the communication circuit for high-speed data communication.

[0072] Here, scrambling information may include information relating to whether the data is transmitted as is or scrambled when the data processing device sends data to the data driving device, and line polarity information may include information indicating the polarity of a first line of a pixel.

[0073] In the CFG completion segment, the second protocol signal PS2 may include a message indicating communication termination. The data driver can acknowledge this message and terminate communication according to the second protocol signal PS2. The auxiliary communication signal ALP can be held low after operation and can be changed to high upon completion of training of the low-speed data communication clock. After the drive voltage VCC is supplied, the data driver can hold the auxiliary communication signal ALP low and change it to high upon completion of training of the low-speed data communication clock in the preamble segment. After the auxiliary communication signal ALP changes to high, the data processing device can send low-speed data via the second protocol signal PS2. Here, the auxiliary communication signal ALP can be referred to as a lock signal, and the data driver can transmit low-speed data via the second communication line (…). Figure 2 The LN2 in the middle sends low-speed data to the data processing device.

[0074] If an error occurs in the internal state or an unplanned communication error occurs after the data driver has changed the auxiliary communication signal ALP to a high level (e.g., unlocking in the clock recovery circuit), the auxiliary communication signal ALP can be changed to a low level. For example, if low-speed data cannot be received or the clock is interrupted in the CFG data segment or CFG completion segment, the data driver can change the auxiliary communication signal ALP to a low level.

[0075] On the other hand, if the display device is in automatic training mode, the pre-clock training segment included in the second protocol signal PS2 can be used.

[0076] The second communication frequency (e.g., a frequency for low-speed data communication) can be predetermined. In other words, regardless of the specifications of the display device, the second communication frequency can be a commonly used frequency, and the data driving device can perform low-speed data communication with the data processing device after configuring the communication circuit to the predetermined second communication frequency.

[0077] On the other hand, the first communication frequency (e.g., the frequency used for high-speed data communication) may not be predetermined. When the data processing device transmits a signal with a frequency, the data driving device may need to configure the communication circuitry to suit that frequency. Therefore, the data processing device and the data driving device may also include a pre-clock training segment in the first protocol signal PS1 to configure the communication circuitry to suit the first communication frequency.

[0078] Specifically, the data processing device can send the first protocol signal PS1, which includes the training clock mode TR_CLK, to the data driving device in the pre-clock training segment.

[0079] The data driver can train the training clock pattern TR_CLK, which is included in the first protocol signal PS1, while changing the configuration value of the clock recovery circuit. Furthermore, the data driver can select the optimal configuration value for the clock recovery circuit based on the training result of the training clock pattern TR_CLK, and can use the optimal configuration value to configure the clock recovery circuit.

[0080] On the other hand, when the display device is in automatic training mode, the EQ training segment included in the second protocol signal PS2 can be used.

[0081] The signal sent by the data processing device may be distorted during its journey to the data processing device. The data driving device may include an equalizer to compensate for the distortion and may configure the characteristics of the equalizer. Specifically, the data driving device may perform clock training and determine whether there are anomalies in the data recovered using the generated clock in order to configure the characteristics of the equalizer.

[0082] On the other hand, when the display device is in display mode, the clock training segment, link training segment, VB segment, and frame segment included in the second protocol signal PS2 can be used. Specifically, the data driving device can recover the clock by performing clock training on the clock training segment. The data driving device can determine whether to process data by expressing meaning or by the link by performing link training on the link training segment. The data driving device can output the image data included in the frame segment and can wait for the output of the image data in the VB segment.

[0083] Figure 5 This is an example diagram illustrating a signal sequence for illustrating EQ training between a data processing apparatus and a data driving apparatus according to an embodiment.

[0084] refer to Figure 5 The diagram shows a signal sequence including the EQ training section for configuring the equalizer.

[0085] The data processing device can store multiple equalizer (EQ) configuration information entries and can send these entries to the data driving device. Multiple EQ configuration information entries can be sent to the data driving device via low-speed data communication. The data driving device can then transmit these entries via a frequently changing first communication line (…). Figure 3 Multiple experiments on signal distortion (LN1) are conducted to determine the optimal EQ configuration value from multiple EQ configuration information. The data processing device can generate a second protocol signal PS2 that includes multiple EQ configuration information. The data processing device can include multiple EQ configuration information in the CFG data segment of the second protocol signal PS2.

[0086] Multiple EQ configuration messages can each include the gain levels of different equalizers. For example, if the multiple EQ configuration messages are a first EQ configuration message and a second EQ configuration message, the first EQ configuration message can include a first gain level, and the second EQ configuration message can include a second gain level different from the first gain level. Each of the multiple EQ configuration messages can also include the tap coefficients of the equalizer.

[0087] The data driver can receive a second protocol signal PS2 that includes multiple EQ configuration information. The data driver can store the multiple EQ configuration information in an auxiliary storage medium, such as a register.

[0088] Here, in addition to multiple EQ configuration information, the second protocol signal PS2 may also include information related to the number of multiple EQ configuration information. For example, if there are eight EQ configuration information, the quantity information can be "8". Furthermore, the second protocol signal PS2 may also include basic EQ configuration information, scrambling information, line polarity information, etc. The basic EQ configuration information may include the basic gain level of the equalizer used for high-speed data communication, and the scrambling information may include information related to whether the data is transmitted as is or scrambled when the data processing device sends data to the data driving device. Additionally, the line polarity information may include information indicating the polarity of the first line of a pixel.

[0089] In the case of terminating low-speed data communication as described above, the data processing device can include the signal used for EQ training in the first protocol signal PS1, and can transmit this signal to the data driving device through the first communication line. Here, the data processing device can transmit signals for EQ training over multiple time periods. Figure 5 In this context, multiple time periods can be represented by dashed lines representing EQ training segments.

[0090] The data-driven device can receive signals for EQ training over multiple time periods and configure the equalizer based on multiple EQ configuration information over those time periods. Here, the data-driven device can evaluate its reception performance for the signals used for EQ training in each time period by changing the equalizer configuration in each time period. Therefore, the data-driven device can select the optimal configuration information from multiple EQ configuration information based on the evaluation results for each time period.

[0091] Specifically, the signals used for EQ training may include, for example: Figure 5The diagram shows a repeating sequence for each time period. This sequence may include a first mode signal TRP1, a second mode signal TRP2, and PRBS. The data driving device can perform clock training on the first mode signal TRP1. The data driving device can recover the data using the clock recovered through clock training. Furthermore, the data driving device can verify whether the PRBS included in the recovered data matches a pre-stored bit string, and can verify the bit error rate (BER) of the PRBS.

[0092] When the signal used for EQ training is encoded with DC balanced code, the data driving device can determine the number of "0"s and "1"s in the recovered data, and thereby determine whether there are data errors in the EQ test signal (EQTP). Here, the DC balanced code method can include an 8B10B encoding / decoding method. Figure 6 This is an example diagram illustrating the signal sequence between the data processing device and the data driving device in an automatic training mode according to an embodiment.

[0093] Reference Figure 6 In automatic training mode, the signal sequence between the data processing device and the data driving device may include a first mode signal TRP1 and a second mode signal TRP2 following the first mode signal TRP1. Optionally, the signal sequence between the data processing device and the data driving device may also include PRBS between the first mode signal TRP1 and the second mode signal TRP2.

[0094] When the display device is operating in automatic training mode to prepare for the transmission and reception of image data, the display device can perform bandwidth optimization steps and automatic EQ steps.

[0095] When the display device performs the bandwidth optimization step, the data driver can configure its communication circuitry to a frequency suitable for high-speed data communication with the data processing device, such as a first communication frequency. The data processing device can then send a first mode signal TRP1 to the data driver. Next, the data driver can recover the clock by performing clock training on the first mode signal TRP1 via a clock recovery circuit.

[0096] Subsequently, the data processing device can send a second mode signal TRP2 to the data driving device. Upon receiving the second mode signal TRP2, the data driving device can terminate the bandwidth optimization step and enter the automatic EQ step. Therefore, the second mode signal TRP2 of the bandwidth optimization step can include termination information of the bandwidth optimization step.

[0097] Therefore, the first mode signal TRP1 of the bandwidth optimization step can correspond to Figure 4The pre-clock training section. The second mode signal TRP2 can also be included in the pre-clock training section.

[0098] When the display device performs an automatic EQ step, the data driver can configure the equalizer to evaluate the reception performance of the signal transmitted by the data processing device and improve signal quality. The data processing device can send a first mode signal TRP1 to the data driver. Next, the data driver can recover the clock by performing clock training on the first mode signal TRP1 via a clock recovery circuit. The data driver can use the recovered clock to recover the PRBS and can calculate the bit error rate of the recovered PRBS. The data driver can then evaluate the reception performance of the signal transmitted by the data processing device based on the bit error rate.

[0099] Subsequently, the data processing device can send a second mode signal TRP2 to the data driving device. Upon receiving the second mode signal TRP2, the data driving device can terminate the automatic EQ step and enter the display mode. Therefore, the second mode signal TRP2 of the automatic EQ step can include the termination information of the automatic EQ step.

[0100] Therefore, the first mode signal TRP1, PRBS, and the second mode signal TRP2 of the automatic EQ step can correspond to Figure 5 The EQ training section.

[0101] On the other hand, an automatic EQ process can include multiple automatic EQ steps. The data-driven device can configure an equalizer for each step.

[0102] For example, the data driving device can configure the equalizer in eight automatic EQ steps (automatic EQ steps 1-8). In these eight automatic EQ steps (automatic EQ steps 1-8), the data processing device can send data packets including a first mode signal TRP1, PRBS, and a second mode signal TRP2. In each step, upon receiving the first mode signal TRP1, the data driving device can configure the equalizer and terminate the equalizer configuration.

[0103] Here, upon receiving the second mode signal TRP2, the data driving device can terminate the first automatic EQ step (automatic EQ step 1) and enter the second automatic EQ step. Optionally, if the equalizer configuration terminates in the eighth automatic EQ step (automatic EQ step 8), the data driving device can enter the display mode. The data driving device can find the optimal equalizer configuration state by repeating the above equalizer configuration eight times.

[0104] Figure 7 This is an example diagram illustrating signals including a first mode signal and a second mode signal according to an embodiment. (Refer to...) Figure 7 Examples are illustrated for signals including a first mode signal TRP1 and a second mode signal TRP2. According to an embodiment, the first mode signal TRP1 and the second mode signal TRP2 may be included in a first protocol signal for high-speed data communication between a data processing device and a data driving device.

[0105] As described above, the first mode signal TRP1 can be used for clock training in the bandwidth optimization step or the automatic EQ step. Therefore, the data drive device can generate the optimal configuration values ​​for the clock recovery circuit through the first mode signal TRP1. The second mode signal TRP2 can be used to notify the end of each step.

[0106] The second-mode signal TRP2 can have a frequency approximately four times slower than the first-mode signal TRP1. For example, when the first-mode signal TRP1 is 4 Gbps, the second-mode signal TRP2 can have a frequency of 1 Gbps. Therefore, when the first-mode signal TRP1 has two unit intervals (UI) per cycle, the second-mode signal TRP2 can include eight UIs per cycle.

[0107] Here, the second-mode signal TRP2 can be transmitted at a frequency approximately four times slower, and this difference can vary depending on the transmission environment or configuration, but is not necessarily four times slower. There must be a difference sufficient to allow the data drive device to clearly identify the difference in the second-mode signal TRP2.

[0108] Furthermore, the first mode signal TRP1 and the second mode signal TRP2 can have a mode that maintains DC balance. Therefore, the first mode signal TRP1 and the second mode signal TRP2 can be encoded into DC balance code, such as 8B10B code, in the data processing device, and can have the form "10101010…". Therefore, even when the first mode signal TRP1 and the second mode signal TRP2 are transmitted between the data processing device and the data driving device… Figure 3 The coupling capacitors 301 to 304 may also not cause distortion.

[0109] Figure 8 This is a block diagram illustrating a data processing apparatus and a data driving apparatus according to an embodiment.

[0110] Reference Figure 8 The data drive device 120 may include a low-speed communication module 810 involving low-speed data communication and a high-speed communication module 820 involving high-speed data communication.

[0111] The low-speed communication module 810 can be activated in command mode and deactivated in automatic training mode and display mode. The low-speed communication module 810 can receive and process second protocol signals from the data processing device 140 via the first communication line LN1. The low-speed communication module 810 may include a receiving circuit 812 and a decoder 814 (LS mode).

[0112] The receiving circuit 812 can be connected to a first communication line LN1, which includes one or more coupling capacitors 301 and 302. The receiving circuit 812 can receive a second protocol signal encoded with DC balanced code via the first communication line LN1. Here, Manchester code can be used as the DC balanced code.

[0113] Furthermore, the receiving circuit 812 may include a buffer for temporarily storing the received signal for use as a buffer for signal reception. The receiving circuit 812 may send the signal temporarily stored in the buffer to the decoder 814. The decoder 814 may receive a second protocol signal (e.g., a preamble segment) and may recover the clock used for low-speed data communication through clock training. Here, the decoder 814 may receive a basic clock OSC_CLK generated by the oscillator OSC and may synchronize the basic clock OSC_CLK with the second protocol signal (e.g., a preamble segment) through clock training.

[0114] Furthermore, decoder 814 can receive data for configuring data drive device 120 from receiving circuit 812, and can decode the received data into DC balanced code. Decoder 814 can send the decoded data to receiving control circuit 830. Here, Manchester code can be used as DC balanced code.

[0115] On the other hand, the high-speed communication module 820 can be activated in automatic training mode and display mode, and can be deactivated in command mode. The high-speed communication module 820 can receive and process a first protocol signal from the data processing device 140 via the first communication line LN1. The high-speed communication module 820 may include an equalizer 822, a clock recovery circuit 824, a parallelization circuit 826, and an identification circuit 828 (HS mode). The equalizer 822 can adjust the signal received from the data processing device 140 via the first communication line LN1. Furthermore, the equalizer 822 can send the signal via the first communication line LN1 to the clock recovery circuit 824 or the identification circuit 828.

[0116] For example, equalizer 822 can adjust the first protocol signal PS1 received through the first communication line LN1. The first protocol signal PS1 may include image data and may be based on high-speed data communication.

[0117] Specifically, distortion may occur in the signal passing through the first communication line LN1, and high-frequency component attenuation (or pulse spread) and inter-symbol interference (ISI) may occur in the signal passing through the first communication line LN1. The equalizer 822 can reproduce the high-frequency components (or remove the pulse spread of the high-frequency components), thereby reducing inter-symbol interference.

[0118] The clock recovery circuit 824 can handle training modes (e.g., Figure 4 The clock training is performed using the signal of the training clock mode (TR_CLK). The clock recovery circuit 824 can recover the clock through the clock training. The clock recovery circuit 824 can use the recovered clock to recover data, and if the recovered data matches the reference data, the recovered clock can be used for communication with the data processing device 140. Here, the clock recovery circuit 824 can generate different clocks according to configuration values. In the following text, the configuration value required for the clock recovery circuit 824 to generate the clock can be referred to as the CDR configuration value. When the clock recovery circuit 824 receives the optimal CDR configuration value, clock training for the training mode can be completed, and a clock based on the training mode can be recovered.

[0119] Parallelization circuit 826 can convert serial data into parallel data. The parallel data can be data included in a first protocol signal or data included in a second protocol signal. Parallelization circuit 826 can receive a clock recovered from clock recovery circuit 824 and can parallelize data received from data processing device 140 using the recovered clock.

[0120] The identification circuit 828 can Figure 6 The first mode signal TRP1 and Figure 6 The second mode signal TRP2 is distinguished from the signal received from the data processing device 140. The identification circuit 828 can generate an identification value (e.g., a count value CNT) as a result. The receive control circuit 830 can determine whether the first mode signal or the second mode signal has been received based on the identification value.

[0121] On the other hand, the data drive device 120 may also include a receive control circuit 830, a lock control circuit 840, and an oscillator OSC.

[0122] The receiving control circuit 830 can receive an identification value from the identification circuit 828, and can perform configuration for receiving image data on the communication circuit upon receiving a first mode signal, and can control the communication circuit to terminate the configuration upon receiving a second mode signal. For example, if the identification value indicates a first mode signal, the receiving control circuit 830 can determine that the data driving device 120 has received a first mode signal. Next, the receiving control circuit 830 can configure the communication circuit of the data driving device 120 to operate in automatic training mode. The receiving control circuit 830 can configure the communication frequency for receiving image data in the bandwidth optimization step, and can configure the equalizer 822 in the automatic EQ step.

[0123] To distinguish Figure 6 The first mode signal TRP1 and Figure 6 The second mode signal TRP2 in the signal can be identified by the identification circuit 828, which includes a frequency divider (not shown) and a counter (not shown). The identification circuit 828 can identify signals including... Figure 6 The first mode signal TRP1 and Figure 6 The second mode signal TRP2 is frequency-divided to generate a divided clock, and the divided clock can be counted to generate a count value CNT. The receive control circuit 830 can receive the count value CNT and determine from the count value CNT that the data drive device 120 has received the data. Figure 6 The first mode signal TRP1 and Figure 6 Which one of the second mode signals TRP2 in the signal?

[0124] The oscillator OSC is an oscillator that generates arbitrary clocks and can generate a counting clock for counting clocks. Furthermore, the oscillator OSC can generate the base clock OSC_CLK used to recover the clock used for low-speed data communication in the decoder 814. Additionally, the oscillator OSC can generate the base clock OSC_CLK used in the communication circuitry of the data drive device 120.

[0125] The lock control circuit 840 can generate a low-level lock signal before completing clock training in the decoder 814 or clock recovery circuit 824, and can send the generated lock signal to the lock monitoring circuit 890 of the data processing device 140 via the second communication line LN2.

[0126] Furthermore, after the decoder 814 or clock recovery circuit 824 completes clock training, the lock control circuit 840 can generate a high-level lock signal and send the generated lock signal to the lock monitoring circuit 890.

[0127] Furthermore, in the event of an internal state malfunction of the lock control circuit 840 or an unplanned communication error after clock training is complete (e.g., decoder 814 or clock recovery circuit 824 unlocks), the lock control circuit 840 can change the lock signal to a low level (L). For example, in the event of data failure or clock interruption, the lock control circuit 840 can change the lock signal to a low level.

[0128] In the event of unlocking after clock training is completed in high-speed data communication, the receiver control circuit 830 can configure the communication circuit to perform low-speed data communication. For example, if unlocking occurs while the display device is operating in automatic training mode based on high-speed data communication, the receiver control circuit 830 can configure the communication circuit to cause the display device to operate in command mode.

[0129] On the other hand, the data processing device 140 may include a transmitting circuit 850, a serialization circuit 860, a transmitting control circuit 880, and a locking monitoring circuit 890.

[0130] The transmitting circuit 850 can be connected to a first communication line LN1 including one or more coupling capacitors 301 and 302. The transmitting circuit 850 can receive a first protocol signal or a second protocol signal in serial form from the serialization circuit 860. The second protocol signal may include... Figure 6 The first mode signal TRP1 and Figure 6 The second mode signal is TRP2. Optionally, the second protocol signal may also include PRBS.

[0131] The serialization circuit 860 can convert parallel data into serial data. The serial data can be data included in a first protocol signal or data included in a second protocol signal.

[0132] The transmit control circuit 880 can generate a second protocol signal based on low-speed data communication from an external source. Here, the second protocol signal may include a preamble segment, a CFG data segment, and a CFG completion segment, and may be encoded using Manchester code to have DC balance. The transmit control circuit 880 can generate the second protocol signal in parallel and can send the generated protocol signal to the serialization circuit 860. Alternatively, the transmit control circuit 880 can generate a first protocol signal based on high-speed data communication from an external source. Here, the first protocol signal may include a pre-clock training segment and an EQ training segment, and may be encoded using 8B10B code to have DC balance. The transmit control circuit 880 can generate the first protocol signal in parallel and send the generated first protocol signal to the serialization circuit 860. Additionally, the first protocol signal may include image data.

[0133] The lock monitoring circuit 890 can receive a lock signal from the lock control circuit 840 of the data drive device 120. In low-speed data communication, when the lock signal received by the lock monitoring circuit 890 changes from a low level to a high level, the transmit control circuit 880 can generate a second protocol signal for high-speed data communication.

[0134] Next, when the lock signal received by the lock monitoring circuit 890 changes from low to high level during high-speed data communication, the transmit control circuit 880 can generate a second protocol signal including image data. The oscillator OSC of the data processing device 140 is an oscillator that generates an arbitrary clock and can generate an internal clock used in the communication circuit of the data processing device 140. For example, the internal clock can be sent to the serialization circuit 860 and can be used to convert parallel data into serial data.

[0135] Figure 9 This is a diagram illustrating the identification of a first mode signal and a second mode signal by a counter according to an embodiment. (Refer to...) Figure 9 The identification circuit 828 can identify the first mode signal TRP1 and the second mode signal TRP2 through the frequency divider 901 and the counter 902. Here, the first mode signal TRP1 can have a first frequency, and the second mode signal TRP2 can have a second frequency lower than the first frequency.

[0136] The first mode signal TRP1 and the second mode signal TRP2 can be sent to the clock recovery circuit 824 and the identification circuit 828 via the equalizer 822. In the clock recovery circuit 824, clock training can be performed for the first mode signal TRP1, and identification values ​​for the first mode signal TRP1 and the second mode signal TRP2 can be generated in the identification circuit 828.

[0137] The identification circuit 828 can receive the first mode signal TRP1 and the second mode signal TRP2 to generate a frequency-divided clock DIV_CLK. The frequency divider 901 can divide the first frequency of the first mode signal TRP1 to generate a first frequency-divided clock DIV_CLK1, and can divide the second frequency of the second mode signal TRP2 to generate a second frequency-divided clock DIV_CLK2.

[0138] The frequency of the first divided clock DIV_CLK1 can be lower than the first frequency, and the frequency of the second divided clock DIV_CLK2 can be lower than the second frequency. Based on the first mode signal TRP1 and the second mode signal TRP2, the frequency of the second divided clock DIV_CLK2 can be lower than the frequency of the first divided clock DIV_CLK1.

[0139] Subsequently, counter 902 can generate a count value CNT by counting the divided clock DIV_CLK as a counting clock. Counter 902 can count the first divided clock DIV_CLK1 as a counting clock to generate a first count value CNT1, and can count the second divided clock DIV_CLK2 as a counting clock to generate a second count value CNT2.

[0140] Here, since the frequency of the second divided clock DIV_CLK2 is lower than the frequency of the first divided clock DIV_CLK1, the first count value CNT1-20- can be lower than the second count value CNT2-82-.

[0141] In practice, when the first mode signal TRP1 with a first frequency of 6Gbps is divided by 2048, a count value of 17.1 can be calculated. When the first mode signal TRP1 with a first frequency of 5Gbps is divided by 2048, a count value of 20.5 can be calculated. Similarly, when the second mode signal TRP2 with a second frequency of 6Gbps is divided by 2048, a count value of 68.2 can be calculated. When the second mode signal TRP2 with a second frequency of 5Gbps is divided by 2048, a count value of 81.9 can be calculated. Here, the count value is generated by the oscillator of the data drive device. Figure 8 The basic clock OSC_CLK in the system can be used as a counting clock, and the frequency of the counting clock can be 50MHz.

[0142] The receiving control circuit 830 can receive identification values ​​such as count values, and can identify either the first mode signal TRP1 or the second mode signal TRP2 based on the identification values. For example, the receiving control circuit 830 can receive a first count value CNT1 for the first mode signal TRP1 and a second count value CNT2 for the second mode signal TRP2. The receiving control circuit 830 can determine that the first mode signal TRP1 has been received by the data driving device when the first count value CNT1 is relatively smaller of the two count values. The receiving control circuit 830 can determine that the second mode signal TRP2 has been received by the data driving device when the second count value CNT2 is relatively larger of the two count values.

[0143] Additionally, the receiving control circuit 830 can determine a count value belonging to a predetermined range as an identification value. For example, the receiving control circuit 830 can receive an identification value including a count value generated from a counter, and if the count value falls within a predetermined range consisting of multiple values, the count value can be determined as a first count value CNT1 for the first mode signal TRP1 or a second count value CNT2 for the second mode signal TRP2. Here, the predetermined range can be a range predicted based on the frequency of the first mode signal TRP1 or the second mode signal TRP2.

[0144] Furthermore, the receiving control circuit 830 can determine the count value generated repeatedly in the same manner as the identification value. For example, in Figure 9 Since the first count value CNT1 corresponding to "20" is generated repeatedly and identically relative to the first mode signal TRP1, the receiving control circuit 830 can ultimately determine the first count value CNT1 as "20". Furthermore, since the second count value CNT2 corresponding to "82" is generated repeatedly and identically relative to the second mode signal TRP2, the receiving control circuit 830 can ultimately determine the second count value CNT2 as "82".

[0145] Figure 10 This is a diagram illustrating the operation of a clock recovery circuit based on a signal sequence between a data processing device and a data driving device according to an embodiment.

[0146] Reference Figure 10 In the bandwidth optimization step, the data drive device can begin to identify the first mode signal TRP1.

[0147] At time I, the data driver can detect the CDR configuration value for the clock recovery circuit, and then generate and store the first count value CNT1. The data driver circuit can stop driving the clock recovery circuit by configuring the reset signal CDRreset used to drive the clock recovery circuit to a low level.

[0148] In time II, the data driver can identify the second mode signal TRP2 by generating a second count value CNT2 and comparing it with the first count value CNT1. The data driver can then terminate the bandwidth optimization step. Simultaneously, the data driver can apply the optimal CDR configuration value to the clock recovery circuit.

[0149] Next, in the automatic EQ step, the data driver can begin to recognize the first mode signal TRP1. At time III, the data driver can begin driving the clock recovery circuit by configuring the reset signal CDR reset, used to drive the clock recovery circuit, to a high level.

[0150] At time IV, the data-driven device can evaluate the equalizer's reception performance and discover the equalizer's EQ configuration value. Here, the data-driven device can recover the PRBS and check the bit error rate of the recovered PRBS.

[0151] At time V, the data driver can terminate the bit error rate check. Furthermore, the data driver can stop driving the clock recovery circuit by configuring the reset signal CDR reset used to drive the clock recovery circuit to a low level.

[0152] At time VI, the data driver can generate a second count value CNT2 and compare it with a first count value CNT1 to identify the second mode signal TRP2. The data driver can terminate the automatic EQ step or a time period during the automatic EQ step (one of automatic EQ steps 1-8). Simultaneously, the data driver can apply the optimal EQ configuration to the equalizer.

[0153] When the automatic EQ step comprises multiple time periods, the data-driven device can determine the number of times the equalizer has been configured by the number of second-mode signals TRP2 identified during the automatic EQ step. The data-driven device can receive information in advance, either regarding the number of times the equalizer has been configured or the number of second-mode signals TRP2 during the automatic EQ step, via low-speed data communication. The data-driven device can repeat the equalizer configuration the same number of times as specified and can operate in display mode.

[0154] Figure 11 This is a flowchart illustrating the operation of a data driving device based on a signal sequence between a data processing device and a data driving device according to an embodiment.

[0155] refer to Figure 11 In the bandwidth optimization step, in step S1101, the data driver can use the optimal CDR configuration value to configure the clock recovery circuit.

[0156] In step S1103, the data driving device can perform the first detection time period T. WD1 Internal detection of the second mode signal TRP2.

[0157] If the second mode signal TRP2 is not detected, the data driving device can enter the display mode for receiving image data and can send a lock signal indicating unlock (LOCK=L) to the data processing device. Optionally, the data driving device can send the lock signal indicating unlock directly to the data processing device without entering the display mode (No in step S1103 and in step S1105). Next, the data driving device can terminate or skip the automatic EQ step in step 1107.

[0158] Upon detection of the second mode signal TRP2, the data drive device may (in step S1103 "Yes" and step S1109) initiate the automatic EQ step.

[0159] In the automatic EQ step, the data driving device can stop driving the clock recovery circuit by configuring the reset signal CDR reset used to drive the clock recovery circuit to a low level. If the automatic EQ step includes multiple time periods, the data driving device can begin configuring the first equalizer in step S1111.

[0160] In step S1113, the data-driven device can determine whether an equalizer has been configured for all time periods. If the data-driven device has configured an equalizer for all time periods, (in step S1113 "Yes" and step S1115) the equalizer can be configured to the optimal EQ configuration value.

[0161] If the data-driven device has not yet configured the equalizer for all time periods, (in step S1113 "No" and step S1117) it can be done in the second detection time period T. WD2 The first mode signal TRP1 is detected internally. If the first mode signal TRP1 is not detected, the data driving device can enter a display mode for receiving image data and can send a lock signal (LOCK = L) indicating unlocking to the data processing device. Optionally, (in step S1117 "No" and step S1105) the data driving device can directly send a lock signal indicating unlocking to the data processing device without entering a display mode. Furthermore, the data driving device can terminate or skip the automatic EQ step in step S1107. As another additional method, if the first mode signal TRP1 is not detected, the data driving device can terminate the equalizer configuration for a corresponding time period and can begin detecting the second mode signal TRP2.

[0162] Upon detecting the first mode signal TRP1, the data driving device can start driving the clock recovery circuit by configuring the reset signal CDR reset used to drive the clock recovery circuit to a high level in step S1119.

[0163] Next, in step S1121, the data driving device can detect clock training during the third detection time period T. WD3 Whether it is completed.

[0164] If clock training is not complete, the data driving device can enter a display mode for receiving image data and can send a lock signal (LOCK=L) indicating unlocking to the data processing device. Optionally, (in step S1121 "No" and step S1105) the data driving device can directly send a lock signal indicating unlocking to the data processing device without entering a display mode. Furthermore, the data driving device can terminate or skip the automatic EQ step in step S1107.

[0165] As an additional method, if clock training is not completed, the data driver can start detecting the second mode signal TRP2, and if the second mode signal TRP2 is detected, the data driver can terminate the equalizer configuration in the corresponding time period and start configuring the equalizer in another time period.

[0166] Once clock training is complete, in step S1123, the data driving device can check the bit error rate with respect to the PRBS.

[0167] After checking the bit error rate, in step S1125, the data driving device can stop driving the clock recovery circuit by configuring the reset signal CDR reset used to drive the clock recovery circuit to a low level.

[0168] In step S1127, the data driving device can perform the fourth detection time period T. WD4 Internal detection of the second mode signal TRP2.

[0169] If the second mode signal TRP2 is not detected, the data driving device can enter the display mode for receiving image data and can send a lock signal indicating unlock (LOCK=L) to the data processing device. Optionally, (in step S1127 "No" and step S1105) the data driving device can directly send the lock signal indicating unlock to the data processing device without entering the display mode. Furthermore, the data driving device can terminate or skip the automatic EQ step in step S1107.

[0170] Upon detection of the second mode signal TRP2, (in step S1127 "Yes" and step S1113) the data driving device may begin configuring the equalizer in another time period.

[0171] Cross-references to related applications

[0172] This application claims priority to Korean Patent Application 10-2020-0091581, filed on July 23, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A display driving device, the display driving device comprising: An identification circuit is configured to receive a first signal having a first mode during a first time period of the preparation mode and to receive a second signal having a second mode different from the first mode during a second time period of the preparation mode. as well as A control circuit, configured to set up a communication circuit for receiving image data based on the first signal, and configured to terminate the setting up of the communication circuit based on the second signal, and Wherein, the first signal corresponds to a first frequency, and the second signal corresponds to a second frequency that is different from the first frequency.

2. The display driving device according to claim 1, wherein The control circuit sets up the communication circuit based on the first signal before receiving the image data.

3. The display driving device according to claim 1, wherein The control circuit is configured to set the communication frequency of the communication circuit based on the first signal.

4. The display driving device according to claim 1, wherein The recognition circuit performs clock training on the first signal.

5. The display driving device according to claim 4, wherein, The recognition circuit uses a clock recovered through training with the clock to recover data.

6. The display driving device according to claim 5, wherein, The identification circuit identifies whether the sequence data included in the recovered data matches the pre-stored bit string.

7. The display driving device according to claim 6, wherein, The identification circuit identifies the bit error rate (BER) of the sequence data included in the recovered data.

8. The display driving device according to claim 6, wherein, The sequence data included in the recovered data includes pseudo-random binary sequence (PRBS) data.

9. The display driving device according to claim 1, wherein, The first signal includes a signal used to train the equalizer included in the recognition circuit.

10. A method for transmitting image data in a display device, the method comprising the steps of: Send a first signal with the first mode during the first time period of the preparation mode; During the second time period of the preparation mode, a second signal having a second mode different from the first mode is sent; as well as The image data is transmitted via a communication circuit. The communication circuit is configured based on the first signal and terminated based on the second signal. Wherein, the first signal corresponds to a first frequency, and the second signal corresponds to a second frequency that is different from the first frequency.

11. The method according to claim 10, wherein, The communication circuit is configured based on the first signal before the image data is transmitted.

12. The method according to claim 10, wherein, The communication frequency of the communication circuit is set based on the first signal.

13. The method according to claim 10, wherein, Clock training is performed on the first signal by the display data receiving device.

14. The method according to claim 13, wherein, The display data receiving device uses a clock recovered through clock training to recover data.

15. The method according to claim 14, wherein, The display data receiving device identifies whether the sequence data included in the recovered data matches the pre-stored bit string.

16. The method according to claim 15, wherein, The display data receiving device identifies the bit error rate (BER) of the sequence data included in the recovered data.

17. The method according to claim 15, wherein, The sequence data included in the recovered data includes pseudo-random binary sequence (PRBS) data.

18. The method according to claim 13, wherein, The first signal includes a signal for training the equalizer included in the display data receiving device.

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