Memory device and operating method thereof

Abstract

The present application relates to a memory device and an operating method thereof. A memory device may include: a first sub-block and a second sub-block, each including a plurality of select transistors and a plurality of memory cells; a peripheral circuit that performs a read operation on data stored in the first sub-block; and control logic that controls the peripheral circuit to turn on the plurality of select transistors included in each of the first sub-block and the second sub-block and apply a read voltage to a selected word line among a plurality of word lines.

Description

Technical Field

[0001] Various embodiments relate generally to electronic devices, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0002] A storage device is configured to store data in response to control by a host device (e.g., a computer or smartphone). A storage device may include a memory device that stores data and a storage controller that controls the memory device. Generally, there are two types of memory devices: volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices retain data as long as power is supplied, but lose the stored data when power is not supplied. Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0004] Nonvolatile memory devices do not lose data even when power is not supplied. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.

[0005] Three-dimensional memory devices have been developed to increase the integration density of memory devices. Due to the structural differences between three-dimensional memory devices and two-dimensional memory devices, various driving methods for driving three-dimensional memory devices have been studied. Summary of the Invention

[0006] Various embodiments of the present disclosure are directed to a memory device having improved read operation characteristics and a method of operating the memory device.

[0007] According to an embodiment, a memory device may include: a first sub-block, which includes a plurality of first selection transistors and a plurality of first memory cells; a second sub-block, which is connected to the first sub-block through a plurality of word lines and includes a plurality of second selection transistors and a plurality of second memory cells; a peripheral circuit, which performs a read operation on data stored in the first sub-block or the second sub-block; and control logic, which controls the peripheral circuit to apply a read voltage to a selected word line among the plurality of word lines, wherein, when the read operation is performed on the first sub-block, the control logic controls the peripheral circuit to: turn on the plurality of first selection transistors and the plurality of second selection transistors, and increase the voltage levels of the plurality of word lines from the first level to the second level, and when the voltage levels of the plurality of word lines reach the second level, turn off the plurality of second selection transistors, and increase the voltage levels of the plurality of word lines from the second level to the third level.

[0008] According to an embodiment, a method for operating a memory device is proposed, which includes a first sub-block and a second sub-block, the first sub-block including a plurality of first selection transistors and a plurality of first memory cells, the second sub-block being connected to the first sub-block via a plurality of word lines and including a plurality of second selection transistors and a plurality of second memory cells, the memory device performing a read operation on the first sub-block, the method may include the following steps: turning on the plurality of first selection transistors and the plurality of second selection transistors; increasing the voltage level of the plurality of word lines from the first level to the second level; turning off the plurality of second selection transistors; and increasing the voltage level of the plurality of word lines from the second level to a third level.

[0009] According to an embodiment, a memory device may include: a first sub-block, which includes a plurality of first selection transistors and a plurality of first memory cells; a second sub-block, which is connected to the first sub-block through a plurality of word lines and includes a plurality of second selection transistors and a plurality of second memory cells; and a peripheral circuit, which performs a read operation on data stored in the first sub-block or the second sub-block, wherein, when performing the read operation, the peripheral circuit turns on the plurality of first selection transistors and the plurality of second selection transistors, increases the voltage levels of the plurality of word lines in a step-by-step increment including at least two step increases, and turns off the plurality of second selection transistors when the voltage levels of the plurality of word lines reach a target voltage level.

[0010] According to an embodiment, a memory device may include: at least one first selection transistor connected to a first memory cell string in a first sub-block; at least one second selection transistor connected to a second memory cell string in a second sub-block; a plurality of word lines connected to the memory cells of the first string and the second string, respectively; and a control circuit configured to sequentially turn on the first transistor and the second transistor, gradually increase the voltage level of the word line to a target level, turn off the at least one second transistor, and gradually increase the voltage level to a set level for reading data from the first string. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the present disclosure;

[0012] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present disclosure;

[0013] Figure 3 is a diagram showing a memory cell array according to an embodiment of the present disclosure;

[0014] Figure 4 is a block diagram illustrating a storage block according to an embodiment of the present disclosure;

[0015] Figure 5is a diagram illustrating a memory block according to another embodiment of the present disclosure;

[0016] Figure 6 is a flowchart illustrating a read operation according to an embodiment of the present disclosure;

[0017] Figure 7 is a timing diagram illustrating a read operation according to an embodiment of the present disclosure;

[0018] Figure 8 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure;

[0019] Figure 9 is a diagram illustrating a card system according to an embodiment of the present disclosure;

[0020] Figure 10 is a diagram illustrating a solid-state drive (SSD) system according to an embodiment of the present disclosure;

[0021] Figure 11 is a diagram illustrating a user system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The specific structural and functional descriptions provided herein relate to embodiments of the present disclosure. However, the present disclosure may be configured in various other forms and / or implemented in various other ways. Therefore, the present disclosure is not limited to any of the embodiments disclosed, nor to any specific details herein. In addition, throughout this specification, references to "an embodiment," "another embodiment," etc. do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment.

[0023] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0024] Figure 1 A host 300 and a storage device 1000 are shown. The storage device 1000 may include a memory device 100 and a storage controller 200.

[0025] The storage device 1000 may be configured to store data in response to control of the host 300. Examples of the storage device 1000 include cellular phones, smart phones, MP3 players, laptop computers, desktop computers, game consoles, display devices, tablet PCs, and in-vehicle infotainment systems.

[0026] The storage device 1000 may be manufactured or configured as any of various types of storage devices according to a host interface corresponding to a communication method with the host 300. For example, the storage device 1000 may be configured as a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of SD, mini-SD, and micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI-Express (PCI-E) card-type storage device, a compact flash (CF) card, a smart media card, and / or a memory stick.

[0027] The memory device 1000 may be manufactured into any of various types of packages. For example, the memory device 1000 may be manufactured into a package-on-package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabricated package (WFP), and / or a wafer-level stacked package (WSP).

[0028] The memory device 100 may store data or utilize stored data. More specifically, the memory device 100 may operate in response to the control of the memory controller 200. In addition, the memory device 100 may include a plurality of memory dies, each of which may include a memory cell array including a plurality of memory cells storing data.

[0029] Each memory cell may be a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0030] The memory cell array 110 may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may include a plurality of pages. A page may be a unit for storing data in the memory device 100 or a unit for reading data stored in the memory device 100.

[0031] Examples of the memory device 100 include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphic double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, perpendicular NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin transfer torque random access memory (STT-RAM). In the context of the following description, the memory device 100 is, by way of example, a NAND flash memory.

[0032] The memory device 100 may receive a command and an address from the memory controller 200. The memory device 100 may be configured to access an area selected in response to the received address in the memory cell array. When the memory device 100 accesses the selected area, the memory device 100 may perform an operation corresponding to the received command on the selected area. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. In a programming operation, the memory device 100 writes data to an area selected by an address. In a read operation, the memory device 100 reads data from an area selected by an address. In an erase operation, the memory device 100 erases data stored in an area selected by an address.

[0033] When power is applied to the memory device 1000, the memory controller 200 may execute the firmware FW. The firmware FW may include: a host interface layer (HIL) that receives a request input from the host 300 or outputs a response to the host 300; a flash translation layer (FTL) that manages operations between an interface of the host 300 and an interface of the memory device 100; and a flash interface layer (FIL) that provides a command to the memory device 100 or receives a response from the memory device 100.

[0034] The memory controller 200 may receive data and a logical address LA from the host 300 and convert the logical address LA into a physical address PA indicating an address of a memory cell storing data in the memory device 100. The logical address LA may be a logical block address LBA and the physical address PA may be a physical block address PBA.

[0035] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a program operation, the memory controller 200 may provide a program command, a physical block address, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a physical block address to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a physical block address to the memory device 100.

[0036] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation without a request from the host 300. For example, the memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation for performing background operations such as wear leveling, garbage collection, and read reclamation.

[0037] The memory controller 200 may provide a cache program command to the memory device 100. When the memory device 100 receives the cache program command, the control logic 130 may control the page buffer group 123 so that data to be programmed to the next page can be stored in the page buffer group 123 while the current page is being programmed with data.

[0038] The host 300 may communicate with the storage device 1000 using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a serial attached SCSI (SAS), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a peripheral component interconnect (PCI), PCI express (PCIe), a non-volatile memory express (NVMe), a universal flash storage (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM) and / or a load reduced DIMM (LRDIMM) communication method.

[0039] Figure 2 is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0040] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0041] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz, which may be coupled to the row decoder 121 through row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0042] In addition, a plurality of memory blocks BLK1 to BLKz may be connected to the page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. Depending on the embodiment, the plurality of memory cells may be nonvolatile memory cells. A single cell for reading stored data among the memory cells connected to the same word line may be defined as a page. Therefore, each memory block may include a plurality of pages.

[0043] Each memory cell included in the memory cell array 110 may include a single-level cell (SLC) storing a single data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0044] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 in response to the control of the control logic 130. In other words, the peripheral circuit 120 may drive the memory cell array 110 in response to the control logic 130. For example, the control logic 130 may control the peripheral circuit 120 to apply various operating voltages to the row lines RL and the bit lines BL1 to BLn, or to discharge the applied operating voltages.

[0045] More specifically, the peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , and an input / output circuit 125 .

[0046] The row decoder 121 may be coupled to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. Depending on the embodiment, the plurality of word lines may include selected word lines coupled to a plurality of memory cells subjected to a read operation and unselected word lines coupled to a plurality of memory cells not subjected to a read operation. Furthermore, the row lines RL may further include a pipe select line.

[0047] The row decoder 121 may be configured to operate in response to the control of the control logic 130. The row decoder 121 may receive a row address RADD from the control logic 130. More specifically, the row decoder 121 may be configured to decode the row address RADD. The row decoder 121 may select at least one memory block from among the memory blocks BLK1 to BLKz based on the decoded address. The row decoder 121 may select at least one word line of the selected memory block based on the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0048] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and apply a program pass voltage lower than the program voltage to unselected word lines.

[0049] The program verification operation and the read operation of the memory cell array 110 can be performed in units of pages. During the program verification operation, the row decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage greater than the verification voltage to the unselected word lines. During the read operation, the row decoder 121 can apply a read voltage to the selected word line and a read pass voltage greater than the read voltage to the unselected word lines.

[0050] The erase operation of the memory cell array 110 may be performed in units of memory blocks. During the erase operation, the row decoder 121 may select one of the memory blocks according to the decoded address and apply a ground voltage to a word line coupled to the selected memory block.

[0051] The voltage generator 122 may operate in response to the control of the control logic 130. More specifically, the voltage generator 122 may be configured to generate a plurality of voltages using an external power supply voltage supplied to the memory device 100 in response to the control of the control logic 130. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage in response to the control of the control logic 130. In other words, the voltage generator 122 may generate various operation voltages Vop for program operations, read operations, and erase operations in response to the operation signal OPSIG.

[0052] For example, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory cell array 110.

[0053] However, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal power supply voltage and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors in response to the control of the control logic 130. The generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121.

[0054] The page buffer group 123 may include first to n-th page buffers PB1 to PBn, which may be coupled to the memory cell array 110 via first to n-th bit lines BL1 to BLn, respectively. The first to n-th page buffers PB1 to PBn may operate in response to control of the control logic 130. More specifically, the first to n-th page buffers PB1 to PBn may operate in response to a page buffer control signal PBSIGNALS. For example, the first to n-th page buffers PB1 to PBn may temporarily store data received via the first to n-th bit lines BL1 to BLn, or may sense a voltage or current in the first to n-th bit lines BL1 to BLn during a read operation or a verify operation.

[0055] More specifically, during a programming operation, when a programming pulse is applied to a selected word line, the first to nth page buffers PB1 to PBn can transmit data DATA received through the input / output circuit 125 to the selected memory cells through the first to nth bit lines BL1 to BLn. The memory cells of the selected page can be programmed according to the transmitted data DATA. Memory cells connected to bit lines to which a program enable voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to bit lines to which a program inhibit voltage (e.g., a power supply voltage) is applied can be maintained.

[0056] For example, during a program verification operation, the first to nth page buffers PB1 to PBn can read page data from selected memory cells through the first to nth bit lines BL1 to BLn, respectively. During a read operation, in response to control of the column decoder 124, the first to nth page buffers PB1 to PBn can read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn, and can output the read data DATA to the input / output circuit 125. During an erase operation, the first to nth page buffers PB1 to PBn can float the first to nth bit lines BL1 to BLn, respectively.

[0057] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0058] The input / output circuit 125 may transfer a command CMD and an address ADDR from the memory controller 200 to the control logic 130 , or may exchange data DATA with the column decoder 124 .

[0059] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit signal VRYBIT and compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0060] The control logic 130 may control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit signal VRYBIT in response to a command CMD and an address ADDR. Furthermore, the control logic 130 may determine whether a verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL. According to an embodiment of the present disclosure, verification information including the pass signal PASS or the fail signal FAIL may be temporarily stored in the page buffer group 123.

[0061] Figure 3 is a block diagram illustrating a memory cell array 110 according to an embodiment of the present disclosure.

[0062] Reference Figure 3 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure and include a plurality of memory cells stacked above a substrate. The plurality of memory cells may be arranged in the +X direction, the +Y direction, and the +Z direction. The structure of each memory block is described below with reference to Figure 4 and Figure 5 Describe in more detail.

[0063] Figure 4 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0064] Reference Figure 4 , shows a representative memory (BLKa) in the memory blocks BLK1 to BLKz. The memory block BLKa may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings may be arranged in a row direction (e.g., an X direction).

[0065] According to an embodiment, a memory block BLKa may include a plurality of sub-blocks, each of which may include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. For example, a first sub-block may include a plurality of first cell strings CS11 to CS1m, and a second sub-block may include a plurality of second cell strings CS21 to CS2m.

[0066] For clarity, Figure 4Two cell strings arranged in a column direction (ie, +Y direction) are shown. However, three or more cell strings may be arranged in the column direction.

[0067] Depending on the embodiment, each sub-block may include multiple selection transistors and multiple memory cells. More specifically, each sub-block may include multiple cell strings. For example, the first sub-block may include multiple first cell strings CS11 to CS1m. Each of the first cell strings CS11 to CS1m may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0068] Each of the selection transistors SST and DST and each of the memory cells MC1 to MCn may have a similar structure. Depending on the embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. Depending on the embodiment, a pillar for providing a channel layer may be provided in each cell string. Depending on the embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating layer, the charge storage layer, and the blocking insulating layer may be provided in each cell string.

[0069] The source select transistors SST of each cell string may be coupled between a common source line CSL and the first to p-th memory cells MC1 to MCp. Furthermore, the source select transistors of cell strings arranged in the same row may be coupled to a source select line extending in the row direction, while the source select transistors of cell strings arranged in different rows may be coupled to different source select lines.

[0070] According to an embodiment of the present disclosure, the source select transistors SST of the first cell strings CS11 to CS1m of the first sub-block may be coupled to a first source select line SSL1. Additionally, the source select transistors SST of the second cell strings CS21 to CS2m of the second sub-block may be coupled to a second source select line SSL2. In other words, the first sub-block and the second sub-block may be coupled to different source select lines (e.g., a first source select line SSL1 and a second source select line SSL2).

[0071] In addition, the first to nth memory cells MC1 to MCn of each cell string may be coupled between the source select transistor SST and the drain select transistor DST.

[0072] The first to nth memory cells MC1 to MCn can be divided into first to pth memory cells MCp and (p+1)th to nth memory cells MCp+1. The first to pth memory cells MCp can be sequentially arranged in the -Z direction and connected in series between the source select transistor SST and the tubular transistor PT. The (p+1)th to nth memory cells MCp+1 can be sequentially arranged in the +Z direction and connected in series between the tubular transistor PT and the drain select transistor DST. The first to pth memory cells MCp and (p+1)th to nth memory cells MCp+1 can be connected to each other via the tubular transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string can be connected to the first to nth word lines WL1 to WLn, respectively.

[0073] The gate of the tube transistor PT of each cell string may be coupled to the pipeline PL.

[0074] Drain select transistors DST of respective cell strings may be coupled between corresponding bit lines and (p+1)th to nth memory cells MCp+1 and MCn. Cell strings arranged in a row direction may be coupled to drain select lines extending in the row direction.

[0075] According to an embodiment, the drain select transistors DST of the first cell strings CS11 to CS1m of the first sub-block may be coupled to the first drain select line DSL1. Additionally, the drain select transistors DST of the second cell strings CS21 to CS2m of the second sub-block may be coupled to the second drain select line DSL2. In other words, the first sub-block and the second sub-block may be coupled to different drain select lines (e.g., the first drain select line DSL1 and the second drain select line DSL2).

[0076] The cell strings arranged in the column direction may be connected to the bit lines extending in the column direction. Figure 4 As shown, the cell strings CS11 and CS21 in the first column may be coupled to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column may be coupled to the m-th bit line BLm.

[0077] Memory cells connected to the same word line among the cell strings arranged in the row direction can form a single page. For example, the memory cells connected to the first word line WL1 in the first cell strings CS11 to CS1m of the first sub-block can constitute a page. The memory cells connected to the first word line WL1 in the second cell strings CS21 to CS2m of the second sub-block can constitute a page. When one of the drain select lines DSL1 and DSL2 is selected, one of the first sub-block and the second sub-block can be selected. In addition, when one of the first sub-block and the second sub-block is selected, multiple first cell strings CS11 to CS1m or multiple second cell strings CS21 to CS2m can be selected. In addition, by selecting one of the word lines WL1 to WLn, a page can be selected from the selected cell string.

[0078] According to another embodiment, even bit lines and odd bit lines may replace the first to m-th bit lines BL1 to BLm. In addition, even cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in a row direction may be respectively connected to even bit lines, and odd cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in a row direction may be respectively connected to odd bit lines.

[0079] According to an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the first to pth memory cells MCp. Alternatively, one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When more dummy memory cells are provided, the operational reliability of the memory block BLKa may be improved, while the size of the memory block BLKa may be increased. On the other hand, when fewer dummy memory cells are provided, the size of the memory block BLKa may be reduced, while the operational reliability of the memory block BLKa may be reduced.

[0080] To effectively control the dummy memory cells, each dummy memory cell can have a desired threshold voltage. Before or after an erase operation on the memory block BLKa, a programming operation can be performed on some or all of the dummy memory cells. When an erase operation is performed after the programming operation, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the dummy memory cells.

[0081] Figure 5 is a block diagram illustrating a memory block BLKb according to an embodiment of the present disclosure.

[0082] Reference Figure 5 , as shown in Figure 3A memory block (BLKb) among the memory blocks BLK1 to BLKz shown. According to an embodiment, the memory block BLKb may include a plurality of sub-blocks. Each sub-block may include a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. More specifically, a first sub-block may include a plurality of first cell strings CS11' to CS1m' among the plurality of cell strings, and a second sub-block may include a plurality of second cell strings CS21' to CS2m' among the plurality of cell strings.

[0083] In addition, each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' may extend in the +Z direction. Each of the first and second sub-blocks may include at least one source select transistor SST, first to n-th memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0084] The source select transistors SST of each cell string may be coupled between a common source line CSL and the first to nth memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row may be coupled to the same source select line. The source select transistors SST of the first cell strings CS11' to CS1m' included in the first sub-block may be coupled to the first source select line SSL1. The source select transistors SST of the second cell strings CS21' to CS2m' included in the second sub-block may be coupled to the second source select line SSL2. According to another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' may be coupled in common to a single source select line.

[0085] First to nth memory cells MC1 to MCn of each cell string may be coupled between source select transistors SST and drain select transistors DST, and gates of first to nth memory cells MC1 to MCn may be coupled to first to nth word lines WL1 to WLn, respectively.

[0086] The drain select transistors DST of each cell string can be coupled between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction can be coupled to a drain select line extending in the row direction. The drain select transistors DST of the first cell strings CS11' to CS1m' of the first sub-block can be coupled to a first drain select line DSL1. The drain select transistors DST of the second cell strings CS21' to CS2m' of the second sub-block can be coupled to a second drain select line DSL2.

[0087] As a result, in addition to removing the pipe transistor PT from each cell string of the memory block BLKb, Figure 5The memory block BLKb shown may have Figure 4 The storage block BLKa shown is equivalent or similar to the circuit.

[0088] According to another embodiment, even bit lines and odd bit lines may replace the first to m-th bit lines BL1 to BLm. In addition, even cell strings of the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be respectively connected to the even bit lines, and odd cell strings of the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be respectively connected to the odd bit lines.

[0089] According to an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, one or more dummy memory cells may be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, one or more dummy memory cells may be provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. When more dummy memory cells are provided, the operational reliability of the memory block BLKb may be improved, while the size of the memory block BLKb may be increased. On the other hand, when fewer memory cells are provided, the size of the memory block BLKb may be reduced, while the operational reliability of the memory block BLKb may be degraded.

[0090] To effectively control the dummy memory cells, each dummy memory cell can have a desired threshold voltage. Before or after an erase operation on memory block BLKb, a programming operation can be performed on some or all of the dummy memory cells. When an erase operation is performed after the programming operation, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the dummy memory cells.

[0091] Figure 6 is a flowchart illustrating a read operation according to an embodiment of the present disclosure. Figure 7 is a timing diagram illustrating a read operation according to an embodiment of the present disclosure.

[0092] According to embodiments, a memory device may include a plurality of sub-blocks, each of which may be coupled to a common source line CSL and a bit line BL. A plurality of memory cells included in each sub-block may be coupled through a plurality of word lines.

[0093] In operation S610, the memory device may set a plurality of word lines. More specifically, the memory device may control peripheral circuits to set voltage levels of the plurality of word lines. In operation S620, the memory device may precharge the bit lines BL and perform a sensing operation to sense stored data based on the threshold voltage of the memory cells.

[0094] Reference Figure 7 The read operation may include a word line setup phase from a first time t1 to a sixth time t6 and a sensing phase after the sixth time t6. The word line setup phase may include setting voltage levels of a plurality of word lines. Each of times t1 to t7 represents a discrete time point.

[0095] First, at a first time t1, when a plurality of word lines have a first voltage level V1, the memory device may apply a turn-on voltage Von to select lines included in each sub-block to turn on transistors associated with those word lines. The select lines may include a first select line (selected DSL / SSL) coupled to a sub-block subject to a read operation and a second select line (unselected DSL / SSL) coupled to a sub-block not subject to a read operation.

[0096] At a second time t2, the memory device may increase the voltage level of the plurality of word lines from the first voltage level V1 to the second voltage level V2. The respective distances between the plurality of word lines and the point where the voltage is supplied may be different. Furthermore, even when the memory device supplies the same word line voltage, a word line (WL_far) farther from the point where the voltage is supplied and a word line (WL_near) closer to the point where the voltage is supplied may take different times to reach the same voltage level. More specifically, between the second time t2 and the third time t3, the word line WL_far and the word line WL_near may have different voltage levels. Therefore, the memory device may supply the word line voltage to the plurality of word lines until the voltage level of the word line furthest from the point where the voltage is supplied reaches the second voltage level V2.

[0097] At a third time t3, when a set condition is satisfied, the memory device may apply a cutoff voltage (e.g., ground voltage) to the second select line (unselected DSL / SSL). This condition may be related to the voltage level of the word line furthest from the supply voltage point, and may be satisfied when the voltage level of the furthest word line reaches the second voltage level V2. Alternatively, this condition may be related to the number of word lines having the second voltage level V2, and in this case, the condition may be satisfied when a threshold number or more of word lines have the second voltage level V2. The memory device may turn off a plurality of select transistors not undergoing a read operation by applying a cutoff voltage (e.g., ground voltage) to the second select line (i.e., unselected DSL / SSL).

[0098] At a fourth time t4, the memory device may increase the voltage level of the plurality of word lines from the second voltage level V2 to a third voltage level V3. The third voltage level V3 may be a pass voltage that turns on memory cells in the memory device regardless of the threshold voltage.

[0099] When the voltage levels of the plurality of word lines increase to the third voltage level V3, the channels corresponding to the sub-blocks not subjected to the read operation can be boosted by turning off the select transistors. When the plurality of select transistors coupled to the second select line (i.e., unselected DSL / SSL) are turned off, the memory device can boost the channels corresponding to the sub-blocks not subjected to the read operation by increasing the voltage levels of the plurality of word lines to the third voltage level V3.

[0100] At the fifth time t5, the memory device may reduce the voltage level of the selected word line from the third voltage level V3 to the first voltage level V1. Alternatively, the memory device may reduce the voltage level of the selected word line to any voltage level (Va) between the ground voltage level GND and the read voltage level Vread.

[0101] In addition, at the sixth time t6, the memory device may precharge the bit line BL to the precharge voltage level Vpre and increase the voltage level of the selected word line to the read voltage level Vread. In other words, the memory device may perform a sensing phase by controlling the bit line BL and multiple word lines after the sixth time t6.

[0102] Figure 8 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0103] According to an embodiment, a memory device may include a first sub-block and a second sub-block. In addition, the first sub-block may include a plurality of first selection transistors and a plurality of first memory cells. The second sub-block may be coupled to the first sub-block via a plurality of word lines and include a plurality of second selection transistors and a plurality of second memory cells.

[0104] As mentioned above Figure 6 As described, a method of operating a memory device to perform a read operation on a first sub-block may include performing a set phase on a plurality of word lines and performing a sense phase on stored data.

[0105] First, in operation S810, the memory device may turn on a plurality of select transistors included in a first sub-block and a second sub-block. The first sub-block may include a plurality of first select transistors (e.g., at least one first source select transistor and at least one first drain select transistor). The second sub-block may include a plurality of second select transistors (e.g., at least one second source select transistor and at least one second drain select transistor). More specifically, the memory device may turn on the plurality of first select transistors and the plurality of second select transistors by applying a turn-on voltage to a first source select line, a second drain select line, a second source select line, and a second drain select line.

[0106] In operation S820, the memory device may increase the voltage level of the plurality of word lines from the first level to the second level. More specifically, the memory device may apply voltage to the plurality of word lines so that the voltage level of the word line farthest from the supply voltage among the plurality of word lines can reach the second level.

[0107] In operation S830, the memory device may turn off a plurality of select transistors included in the second sub-block. More specifically, the memory device may turn off a plurality of second select transistors (e.g., at least one second source select transistor and at least one second drain select transistor) by applying a cutoff voltage to a second source select line and a second drain select line. The memory device may place a channel corresponding to the second sub-block in a floating state by turning off the plurality of second select transistors.

[0108] In operation S840, the memory device may increase the voltage levels of the plurality of word lines from the second level to the third level. In the memory device, when the voltage levels of the plurality of word lines increase from the second level to the third level in a state where the channel corresponding to the second sub-block is floated, the channel corresponding to the second sub-block may be boosted by coupling with the channel corresponding to the first sub-block.

[0109] The memory device may then apply a read voltage to a selected word line from among the plurality of word lines. More specifically, the memory device may increase the voltage levels of the plurality of word lines to a third level, and then may decrease the voltage level of the selected word line to the read voltage level. Alternatively, the memory device may increase the voltage levels of the plurality of word lines to a third level, decrease the voltage level of the selected word line from the third level to the first level, and then increase the voltage level of the selected word line from the first level to the read voltage level.

[0110] After performing operations S810 to S840 , the memory device may perform a sensing operation of applying a precharge voltage to a plurality of bit lines coupled to the first subblock and sensing stored data based on threshold voltages of memory cells.

[0111] Figure 9 is a diagram illustrating a memory card system 2000 according to an embodiment of the present disclosure.

[0112] Reference Figure 9 , the memory card system 2000 may include a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0113] The memory controller 2100 may be electrically coupled to the memory device 2200. The memory controller 2100 may be configured to access the memory device 2200. For example, the memory controller 2100 may control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 may be configured to provide an interface between the memory device 2200 and a host. In addition, the memory controller 2100 may be configured to drive firmware for controlling the memory device 2200.

[0114] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC block.

[0115] The storage controller 2100 can communicate with an external device through the connector 2300. The storage controller 2100 can communicate with an external device (e.g., a host) based on a specific communication protocol. For example, the storage controller 2100 can communicate with an external device through at least one of various communication protocols such as Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced MiniDisk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and / or Non-Volatile Memory Express (NVMe) protocols. For example, the connector 2300 can be defined by at least one of the various communication protocols described above.

[0116] In an embodiment, the memory device 2200 may be specifically implemented as any of various non-volatile memory devices such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-torque magnetic RAM (STT-MRAM).

[0117] The storage controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC or MMCmicro), an SD card (SD, miniSD, microSD or SDHC) and / or a Universal Flash Storage (UFS).

[0118] Figure 10 is a diagram illustrating a solid-state drive (SSD) system 3000 according to an embodiment of the present disclosure.

[0119] Reference Figure 10 , the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange signals SIG with the host 3100 through a signal connector 3001 and may receive power PWR through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0120] According to an embodiment, the SSD controller 3210 may perform the above-mentioned Figure 1 The functions of the storage controller 200 described above are described. The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG may be based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be defined by at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and / or a non-volatile memory express (NVMe) interface.

[0121] The auxiliary power supply 3230 can be connected to the host 3100 via the power connector 3002. The auxiliary power supply 3230 can be supplied with power PWR from the host 3100 and charged. When power is not supplied smoothly from the host 3100, the auxiliary power supply 3230 can supply power to the SSD 3200. Depending on the embodiment, the auxiliary power supply 3230 can be provided inside or outside the SSD 3200. For example, the auxiliary power supply 3230 can be provided on the motherboard and can supply auxiliary power to the SSD 3200.

[0122] The buffer memory 3240 can be used as a buffer memory for the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and / or GRAM, or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, and / or PRAM.

[0123] Figure 11 is a diagram illustrating a user system 4000 according to an embodiment of the present disclosure.

[0124] Reference Figure 11 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0125] The application processor 4100 may execute components, an operating system (OS), or a user program included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling the components included in the user system 4000. The application processor 4100 may be provided as a system-on-chip (SoC).

[0126] The memory module 4200 can be used as a main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 can include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and / or LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and / or FRAM. For example, the application processor 4100 and the memory module 4200 can be packaged based on a package-on-package (PoP) and then provided as a single semiconductor package.

[0127] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communications. For example, the network module 4300 can be included in the application processor 4100.

[0128] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. The storage module 4400 can also transmit the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be embodied as a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory with a three-dimensional (3D) structure. For example, the storage module 4400 can be provided as a removable storage medium (i.e., a removable drive) such as an external drive or a memory card of the user system 4000.

[0129] For example, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above with reference to FIG. Figures 1 to 8 The memory module 4400 can be operated in the same manner as described above with reference to Figure 1 The storage device 1000 operates in the same manner as described.

[0130] The user interface 4500 may include any of various interfaces for inputting data or instructions to the application processor 4100 or outputting data to an external device. Depending on the embodiment, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric device. The user interface 4500 may also include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and / or a monitor.

[0131] According to an embodiment of the present disclosure, a memory device having improved read operation characteristics and a method of operating the memory device may be provided.

[0132] In the embodiments discussed above, it is not necessary to perform all operations. In some cases, one or more operations may be omitted. In some cases, one or more operations may be performed in an order different from the disclosed order. Generally, the disclosed embodiments are intended to help those skilled in the art understand the present disclosure more clearly, rather than to limit the scope of the present invention. In other words, those skilled in the art will be able to easily understand that, in view of the teachings herein, various modifications may be made without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to encompass all such modifications that fall within the scope of the appended claims and their equivalents.

[0133] CROSS-REFERENCE TO RELATED APPLICATIONS

[0134] This application claims the benefit of Korean Patent Application No. 10-2020-0092330, filed on July 24, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A memory device, comprising: a first sub-block including a plurality of first selection transistors and a plurality of first memory cells; a second sub-block coupled to the first sub-block through a plurality of word lines and comprising a plurality of second selection transistors and a plurality of second memory cells; a peripheral circuit configured to perform a read operation on data stored in the first sub-block or the second sub-block; as well as a control logic that controls the peripheral circuit to apply a read voltage to a selected word line among the plurality of word lines, wherein the plurality of first selection transistors include at least one first source selection transistor and at least one first drain selection transistor, and the plurality of second selection transistors include at least one second source selection transistor and at least one second drain selection transistor, When the read operation is performed on the first sub-block, the control logic controls the peripheral circuit: turning on the at least one first source select transistor and the at least one first drain select transistor included in the plurality of first select transistors and the at least one second source select transistor and the at least one second drain select transistor included in the plurality of second select transistors, increasing the voltage levels of the plurality of word lines from a first level to a second level, When the voltage levels of the plurality of word lines reach the second level, the at least one second source select transistor and the at least one second drain select transistor included in the plurality of second select transistors are turned off, and The voltage levels of the plurality of word lines are increased from the second level to a third level.

2. The memory device according to claim 1, wherein After increasing the voltage levels of the plurality of word lines to the third level, the control logic controls the peripheral circuit to decrease the voltage level of the selected word line to a read voltage level.

3. The memory device according to claim 1, wherein After increasing the voltage levels of the plurality of word lines to the third level, the control logic controls the peripheral circuits: reducing the voltage level of the selected word line from the third level to the first level, and The voltage level of the selected word line is increased to a read voltage level.

4. The memory device according to claim 1, wherein After increasing the voltage levels of the plurality of word lines to the third level, the control logic controls the peripheral circuit to apply a precharge voltage to a plurality of bit lines coupled to the first sub-block.

5. The memory device according to claim 1, wherein The first level is a voltage level greater than 0V. The memory device according to claim 1 , wherein: The third level is a voltage level for turning on a plurality of memory cells.

7. The memory device according to claim 1, wherein When a voltage level of a word line farthest from a point of a supply voltage among the plurality of word lines reaches the second level, the control logic controls the peripheral circuit to turn off the second selection transistor included in the second sub-block.

8. A method of operating a memory device, the memory device comprising a first sub-block and a second sub-block, the first sub-block comprising a plurality of first selection transistors and a plurality of first memory cells, the second sub-block being coupled to the first sub-block via a plurality of word lines and comprising a plurality of second selection transistors and a plurality of second memory cells, wherein: The plurality of first selection transistors include at least one first source selection transistor and at least one first drain selection transistor, and the plurality of second selection transistors include at least one second source selection transistor and at least one second drain selection transistor, the memory device performs a read operation on the first sub-block, and the method includes the following steps: turning on the at least one first source select transistor and the at least one first drain select transistor included in the plurality of first select transistors and the at least one second source select transistor and the at least one second drain select transistor included in the plurality of second select transistors; increasing the voltage levels of the plurality of word lines from a first level to a second level; turning off the at least one second source select transistor and the at least one second drain select transistor included in the plurality of second select transistors; and The voltage levels of the plurality of word lines are increased from the second level to a third level.

9. The method according to claim 8, further comprising the steps of: A read voltage is applied to a selected word line among the plurality of word lines.

10. The method according to claim 9, wherein: The step of applying the read voltage includes the step of decreasing the voltage level of the selected word line to a read voltage level after increasing the voltage levels of the plurality of word lines to the third level.

11. The method according to claim 9, wherein: The step of applying the read voltage comprises the following steps: After increasing the voltage levels of the plurality of word lines to the third level, decreasing the voltage level of the selected word line to the first level; and After the voltage level of the selected word line is decreased to the first level, the voltage level of the selected word line is increased to a read voltage level.

12. The method according to claim 8, further comprising the steps of: After the voltage levels of the plurality of word lines are increased to the third level, a precharge voltage is applied to a plurality of bit lines coupled to the first sub-block.

13. The method according to claim 8, wherein The first level is a voltage level greater than 0V.

14. The method according to claim 8, wherein The third level is a voltage level for turning on the plurality of first memory cells and the plurality of second memory cells.

15. A memory device, comprising: a first sub-block including a plurality of first selection transistors and a plurality of first memory cells; a second sub-block coupled to the first sub-block through a plurality of word lines and comprising a plurality of second selection transistors and a plurality of second memory cells; as well as a peripheral circuit that performs a read operation on data stored in the first sub-block or the second sub-block, wherein the plurality of first selection transistors include at least one first source selection transistor and at least one first drain selection transistor, and the plurality of second selection transistors include at least one second source selection transistor and at least one second drain selection transistor, Wherein, when performing the read operation, the peripheral circuit turns on the at least one first source selection transistor and the at least one first drain selection transistor included in the multiple first selection transistors and the at least one second source selection transistor and the at least one second drain selection transistor included in the multiple second selection transistors, so that the voltage levels of the multiple word lines increase in a step-by-step increment including at least two step increases, and when the voltage levels of the multiple word lines reach the target voltage level, the at least one second source selection transistor and the at least one second drain selection transistor included in the multiple second selection transistors are turned off.

16. The memory device according to claim 15, wherein When performing the read operation, the peripheral circuit reduces the voltage level of a selected word line to a read voltage level after increasing the voltage levels of the plurality of word lines in stepwise increments.

17. The memory device according to claim 15, wherein: When performing the read operation, after increasing the voltage levels of the plurality of word lines in stepwise increments, the peripheral circuit decreases the voltage level of a selected word line to a ground voltage level and increases the voltage level of the selected word line from the ground voltage level to a read voltage level.

18. The memory device according to claim 15, wherein When performing the read operation, the peripheral circuit applies a precharge voltage to a plurality of bit lines coupled to the first sub-block after increasing the voltage levels of the plurality of word lines in stepwise increments.

19. The memory device according to claim 15, wherein: When performing the read operation, the peripheral circuit increases the voltage levels of the plurality of word lines by one of the plurality of step increments to a pass voltage level for turning on the plurality of first memory cells and the plurality of second memory cells.

20. The memory device of claim 15, wherein: The peripheral circuit turns off the plurality of second selection transistors when a voltage level of a word line farthest from a point of a supply voltage among the plurality of word lines reaches the target voltage level.

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