Page buffer, operation method and circuit thereof

Abstract

The present application relates to a page buffer, an operating method thereof, and a circuit therefor. An electronic device is provided. A page buffer includes at least one data latch, a sense latch, and a bit line voltage controller. The at least one data latch stores a program verification result of a previous program loop among multiple program loops and program data to be stored in a memory cell. The sense latch stores a program verification result of a current program loop among the multiple program loops. During a program operation in a program loop subsequent to the current program loop among the multiple program loops, the bit line voltage controller updates the program verification result of the previous program loop stored in the at least one data latch to the sense latch.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to a page buffer and an operating method thereof. Background Art

[0002] A storage device can store data in response to control by a host device such as a computer or smartphone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. Generally, there are two types of memory devices: volatile memory devices and non-volatile memory devices.

[0003] A volatile memory device can store data only when power is supplied to it, and loses the data stored therein when power is not supplied. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0004] Nonvolatile memory devices can retain stored data even when power is interrupted or blocked. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0005] Various embodiments of the present disclosure relate to a page buffer having improved program verification operation performance and a method of operating the page buffer.

[0006] According to one embodiment, a method of operating a page buffer that performs multiple programming loops, each programming loop including a programming operation and a programming verification operation, the method may include: storing a programming verification result of a previous programming loop among the multiple programming loops in a data latch; storing a programming verification result of a current programming loop among the multiple programming loops in a sensing latch; and updating the programming verification result of the previous programming loop stored in the data latch to the sensing latch during a programming operation of a next programming loop among the multiple programming loops.

[0007] According to one embodiment, a page buffer may include at least one data latch, a sense latch, and a bit line voltage controller. The at least one data latch may store a program verification result of a previous program loop among multiple program loops and program data to be stored in a memory cell. The sense latch may store a program verification result of a current program loop following the previous program loop among the multiple program loops. The bit line voltage controller may update the program verification result of the previous program loop stored in the at least one data latch to the sense latch during a program operation of a next program loop following the current program loop among the multiple program loops.

[0008] According to one embodiment, a page buffer may include at least one data latch, a sense latch, and a bit line voltage controller. The at least one data latch may store a program verification result of a first programming loop among first, second, and third programming loops executed sequentially, as well as program data to be stored in a memory cell. The sense latch may store a program verification result of the second programming loop. The bit line voltage controller may update the program verification result of the first programming loop stored in the at least one data latch to the sense latch during a programming operation of the third programming loop.

[0009] According to one embodiment, a circuit may include a first latch and a second latch coupled to a bit line, and control logic. The control logic sequentially executes a first programming loop, a second programming loop, and a third programming loop to store data latched in the second latch in a memory cell coupled to the bit line. The control logic controls the second latch to further latch a first program verification result of the first programming loop, and controls the first latch to latch a second program verification result of the second programming loop. During the third programming loop, the control logic controls the first latch to further latch the first program verification result from the second latch, sets the bit line based on the first program verification result and the second program verification result from the first latch, and controls the second latch to further latch the second program verification result from the first latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure;

[0011] Figure 2 This is an example of Figure 1 A diagram showing the structure of a memory device;

[0012] Figure 3 This is an example of Figure 2 A diagram of a memory cell array is shown;

[0013] Figure 4This is an example of Figure 2 A diagram illustrating a programming operation of a memory device;

[0014] Figure 5 is a diagram illustrating a page buffer according to an embodiment of the present disclosure;

[0015] Figure 6 is a diagram illustrating an operation of updating a program verification result in a program loop;

[0016] Figure 7 is an example of Figure 6 Detailed diagram of the operation of updating the programming verification result obtained in;

[0017] Figure 8 is a diagram illustrating data values of a data latch according to an embodiment of the present disclosure;

[0018] Figure 9 is a diagram illustrating changes in data values of data latches as a program operation is performed;

[0019] Figure 10 is a diagram illustrating a bit line voltage controller according to an embodiment of the present disclosure;

[0020] Figure 11 is a diagram illustrating a sense latch and a data latch according to an embodiment of the present disclosure;

[0021] Figure 12 is a timing diagram illustrating the operation of a page buffer according to an embodiment of the present disclosure;

[0022] Figure 13 is a flowchart illustrating an operation of updating a verification result of a previous program loop to a sense latch according to an embodiment of the present disclosure; and

[0023] Figure 14 is a flowchart illustrating an operation of updating a verification result of a current program loop to a data latch according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Specific structure and function description is provided herein only for describing the embodiments of the present invention. However, the present invention can be configured, arranged or performed differently from what is disclosed herein. Therefore, the present invention is not limited to any particular embodiment nor to any specific details. In addition, throughout the specification, references to "embodiment", "another embodiment" etc. are not necessarily only to one embodiment, and different references to any such phrases are not necessarily to the same embodiment. In addition, indefinite articles (i.e. "one" or "a kind of") are used to represent one or more, unless explicitly intended to mean only one. Similarly, when the terms "comprise", "comprising", "having" etc. are used in this article, it is not excluded that one or more other elements may be present or added in addition to the elements mentioned.

[0025] Figure 1 is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

[0026] Reference Figure 1 The storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device 100. The storage device 50 may store data in response to the control of a host (not shown). Examples of the host include cellular phones, smart phones, MP3 players, laptop computers, desktop computers, game players, TVs, tablet PCs, and in-vehicle infotainment systems.

[0027] The storage device 50 may be configured as any of various types of storage devices according to a host interface corresponding to a communication method with the host. For example, the storage device 50 may be configured as any of the following types of storage devices: a solid-state drive (SSD), a multimedia card (MMC) in the form of a multimedia card (e.g., eMMC, RS-MMC, or micro MMC), a secure digital card in the form of an SD (e.g., mini SD or micro SD), a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card-type storage device, a peripheral component interconnect (PCI) card-type storage device, a PCI express (PCI-e) card-type storage device, a compact flash (CF) card, a smart media card, and / or a memory stick.

[0028] The storage device 50 may be manufactured as any of various types of packages. For example, the storage device 50 may be manufactured as any of the following types of packages: package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabricated package (WFP), and / or wafer-level stacked package (WSP).

[0029] The memory device 100 may store data and may operate in response to control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data.

[0030] Each memory cell may be configured as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data.

[0031] The memory cell array may include multiple memory blocks. Each of the memory blocks may include multiple memory cells. Each memory block may include multiple pages. Depending on the embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100.

[0032] A memory block may be a unit for erasing data. Depending on the embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a perpendicular NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM). As an example, in the context of the following description, it is assumed that the memory device 100 is a NAND flash memory.

[0033] The memory device 100 can receive a command and an address from the memory controller 200 and access the area selected by the address in the memory cell array. That is, the memory device 100 can perform the operation indicated by the command on the area selected by the address. For example, the memory device 100 can perform a write operation (or programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 can program the area selected by the address with data. During the read operation, the memory device 100 can read data from the area selected by the address. During the erase operation, the memory device 100 can erase the data stored in the area selected by the address.

[0034] The memory controller 200 may control general operations of the storage device 50 .

[0035] The memory controller 200 may execute firmware when power is applied to the storage device 50. When the memory device 100 is a flash memory device, the memory controller 200 may execute firmware such as a flash translation layer (FTL) for controlling communication between the host and the memory device 100.

[0036] According to an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host and convert the LBA into a physical block address (PBA) indicating an address of a memory cell in which data is to be stored in the memory device 100 .

[0037] The memory controller 200 can control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host. During a program operation, the memory controller 200 can provide a write command, a physical block address, and data to the memory device 100. During a read operation, the memory controller 200 can provide a read command and a physical block address to the memory device 100. During an erase operation, the memory controller 200 can provide an erase command and a physical block address to the memory device 100.

[0038] According to an embodiment, the memory controller 200 may generate commands, addresses, and data independently of a request from the host and transmit them to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0039] According to an embodiment, the memory controller 200 may control at least two memory devices 100. The memory controller 200 may control the memory devices 100 according to an interleaving scheme to improve operating performance. In the interleaving scheme, the operating periods of two or more memory devices 100 may at least partially overlap.

[0040] The host may communicate with the storage device 50 using at least one of various communication methods such as: Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMediaCard (MMC) embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM) and / or Load Reduced DIMM (LRDIMM).

[0041] Figure 2 It is an example Figure 1 FIG. 1 is a diagram showing the structure of the memory device 100 .

[0042] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0043] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz, which may be coupled to an address decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz may be coupled to a read / write circuit 123 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. Depending on the embodiment, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, memory cells coupled to the same word line may be defined as a physical page. In other words, the memory cell array 110 may include a plurality of physical pages. Depending on the embodiment, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one dummy cell may be coupled in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0044] Each of the memory cells of the memory device 100 may be a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data.

[0045] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a read and write circuit 123 , a data input / output circuit 124 , and a sensing circuit 125 .

[0046] The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

[0047] The address decoder 121 may be coupled to the memory cell array 110 via row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to an embodiment of the present disclosure, the word lines may include normal word lines and dummy word lines. According to an embodiment of the present disclosure, the row lines RL may further include pipe select lines.

[0048] The address decoder 121 may be configured to operate in response to the control of the control logic 130. The address decoder 121 may receive an address ADDR from the control logic 130.

[0049] The address decoder 121 may be configured to decode the block address of the received address ADDR. The address decoder 121 may select at least one memory block among the memory blocks BLK1 to BLKz based on the decoded block address. The address decoder 121 may be configured to decode the row address of the received address ADDR. The address decoder 121 may select at least one word line among the word lines of the selected memory block based on the decoded row address. The address decoder 121 may apply the operating voltage Vop provided by the voltage generator 122 to the selected word line.

[0050] During a program operation, the address decoder 121 may apply a program voltage to a selected word line and a pass voltage lower than the program voltage to unselected word lines. During a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage higher than the verification voltage to unselected word lines.

[0051] During a read operation, the address decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage higher than the read voltage to unselected word lines.

[0052] According to an embodiment of the present disclosure, the memory device 100 can perform an erase operation on each memory block. During the erase operation, the address ADDR input to the memory device 100 may include a block address. The address decoder 121 can decode the block address and select at least one memory block in response to the decoded block address. During the erase operation, the address decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0053] According to an embodiment of the present disclosure, the address decoder 121 may be configured to decode the column address of the transmitted address ADDR. The decoded column address may be transmitted to the read / write circuit 123. For example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0054] The voltage generator 122 may be configured to generate a plurality of operating voltages Vop by using an external power supply voltage supplied to the memory device 100. The voltage generator 122 may operate in response to the control of the control logic 130.

[0055] According to an embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory device 100.

[0056] According to an embodiment, the voltage generator 122 may generate a plurality of voltages Vop by using an external power supply voltage or an internal power supply voltage. The voltage generator 122 may be configured to generate various voltages used by the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of selected read voltages, and a plurality of unselected read voltages.

[0057] The voltage generator 122 may include a plurality of pumping capacitors receiving an internal power supply voltage to generate a plurality of operating voltages Vop having various voltage levels, and may generate the plurality of operating voltages Vop by selectively activating the plurality of pumping capacitors in response to control of the control logic 130 .

[0058] A plurality of operating voltages Vop may be provided to the memory cell array 110 through the address decoder 121 .

[0059] The read / write circuit 123 may include first to mth page buffers PB1 to PBm respectively coupled to the memory cell array 110 through first to mth bit lines BL1 to BLm. The first to mth page buffers PB1 to PBm may operate in response to control of the control logic 130 .

[0060] The first to mth page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 124. During a program operation, the first to mth page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

[0061] During a programming operation, when a programming voltage is applied to a selected word line, the first page buffer PB1 to the mth page buffer PBm can transmit the data DATA to be stored received through the data input / output circuit 124 to the selected memory cell through the bit lines BL1 to BLm. The memory cells of the selected page can be programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a program permission voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a program inhibition voltage (e.g., a power supply voltage) is applied can be maintained. During a program verification operation, the first page buffer PB1 to the mth page buffer PBm can read the data DATA stored in the memory cells from the selected memory cells through the bit lines BL1 to BLm.

[0062] During a read operation, the read and write circuit 123 may read data DATA from memory cells of a selected page through the bit lines BL1 to BLm and may store the read data DATA in the first to mth page buffers PB1 to PBm.

[0063] During an erase operation, the read / write circuit 123 may float the bit lines BL1 to BLm. According to an embodiment, the read / write circuit 123 may include a column selection circuit.

[0064] The data input / output circuit 124 may be coupled to the first to mth page buffers PB1 to PBm through the data lines DL. The data input / output circuit 124 may operate in response to the control of the control logic 130.

[0065] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive input data DATA. During a program operation, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During a read operation, the data input / output circuit 124 may output data DATA transmitted from the first page buffer PB1 to the mth page buffer PBm included in the read / write circuit 123 to the external controller.

[0066] During a read operation or a verification operation, the sensing circuit 125 can generate a reference current in response to an enable bit VRYBIT signal generated by the control logic 130, and can output a pass signal or a fail signal to the control logic 130 by comparing the sensing voltage VPB received from the read / write circuit 123 with a reference voltage generated by the reference current.

[0067] The control logic 130 may be coupled to the address decoder 121, the voltage generator 122, the read / write circuit 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may be configured to control general operations of the memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device.

[0068] The control logic 130 can control the peripheral circuit 120 by generating various signals in response to a command CMD and an address ADDR. For example, the control logic 130 can output an operation signal OPSIG, an address ADDR, a read / write circuit control signal PBSIGNALS, and an enable bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 can output the operation signal OPSIG to the voltage generator 122, the address ADDR to the address decoder 121, the read / write circuit control signal PBSIGNALS to the read / write circuit 123, and the enable bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 can determine whether the verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL output from the sensing circuit 125.

[0069] Figure 3 It is an example Figure 2 A diagram of a memory cell array 110 is shown.

[0070] Reference Figure 3 , the first to z-th memory blocks BLK1 to BLKz may be commonly coupled to the first to m-th bit lines BL1 to BLm. Figure 3 , as an example, components included in the first memory block BLK1 among the plurality of memory blocks BLK1 to BLKz are illustrated. However, it should be understood that each of the remaining memory blocks BLK2 to BLKz may be configured in substantially the same manner as the first memory block BLK1.

[0071] The memory block BLK1 may include a plurality of cell strings CS1_1 to CS1_m, where m is a positive integer of 2 or greater. The first to mth cell strings CS1_1 to CS1_m may be coupled to first to mth bit lines BL1 to BLm, respectively. Each of the first to mth cell strings CS1_1 to CS1_m may include a drain select transistor DST, a plurality of memory cells MC1 to MCn coupled in series, and a source select transistor SST, where n is a positive integer of 2 or greater.

[0072] A gate terminal of the drain select transistor DST included in each of the first to m-th cell strings CS1_1 to CS1_m may be coupled to a drain select line DSL1. Gate terminals of the first to n-th memory cells MC1 to MCn included in each of the first to m-th cell strings CS1_1 to CS1_m may be coupled to first to n-th word lines WL1 to WLn, respectively. A gate terminal of the source select transistor SST included in each of the first to m-th cell strings CS1_1 to CS1_m may be coupled to a source select line SSL1.

[0073] As an example, the structure of the first cell string CS1_1 among the plurality of cell strings CS1_1 to CS1_m is described, however, it should be understood that each of the remaining cell strings CS1_2 to CS1_m may be configured in substantially the same manner as the first cell string CS1_1.

[0074] A drain terminal of the drain select transistor DST included in the first cell string CS1_1 may be coupled to a first bit line BL1. A source terminal of the drain select transistor DST included in the first cell string CS1_1 may be coupled to a drain terminal of a first memory cell MC1 included in the first cell string CS1_1. The first to nth memory cells MC1 to MCn may be coupled in series with one another. A drain terminal of the source select transistor SST included in the first cell string CS1_1 may be coupled to a source terminal of an nth memory cell MCn included in the first cell string CS1_1. A source terminal of the source select transistor SST included in the first cell string CS1_1 may be coupled to a common source line CSL. Depending on the embodiment, the common source line CSL may be commonly coupled to the first to zth memory blocks BLK1 to BLKz.

[0075] A drain select line DSL1, first to n-th word lines WL1 to WLn, and a source select line SSL1 may be included in Figure 2 The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 may be controlled by the address decoder 121. The common source line CSL may be controlled by the control logic 130. The first to mth bit lines BL1 to BLm may be controlled by the read / write circuit 123.

[0076] Figure 4 This is an example of Figure 2 A diagram illustrating a programming operation of a memory device is shown.

[0077] exist Figure 4 In the embodiment of the present invention, it is assumed that each memory cell is a multi-level cell (MLC) storing two bits of data. However, the present invention is not limited thereto, and each memory cell may be a triple-level cell (TLC) storing three bits of data or a quad-level cell (QLC) storing four bits of data. More generally, the number of bits of data stored in a memory cell may be one or more bits.

[0078] The memory device may perform a plurality of program loops PL1 to PLn so that each selected memory cell may be programmed to have a threshold voltage corresponding to one of a plurality of program states P1, P2, and P3.

[0079] Each of the plurality of program loops PL1 to PLn may include a program step (PGM Step) in which a program voltage is applied to a selected word line connected to a selected memory cell, and a program verification step (Verify Step) in which a verification voltage is applied to determine whether the selected memory cell is programmed.

[0080] For example, when performing the first program loop PL1, first to third verification voltages V_vfy1 to V_vfy3 may be sequentially applied after applying the first program pulse Vpgm1 to verify the program states of the selected memory cells. Memory cells each having the first program state P1 as a target program state may be verified by the first verification voltage V_vfy1. Memory cells each having the second program state P2 as a target program state may be verified by the second verification voltage V_vfy2. Memory cells each having the third program state P3 as a target program state may be verified by the third verification voltage V_vfy3.

[0081] Memory cells that have been determined to have passed verification by applying the first to third verification voltages V_vfy1 to V_vfy3 may be determined to have a target program state. These memory cells may be program-inhibited in all subsequent programming loops starting from the second programming loop PL2. In other words, starting from the second programming loop PL2, a program-inhibit voltage may be applied to the bit lines connected to the memory cells that have been determined to have passed verification.

[0082] To program the remaining non-program-inhibited memory cells in the second programming loop PL2, a second programming pulse Vpgm2 that is a unit voltage ΔVpgm higher than the first programming pulse Vpgm1 can be applied to the selected word line. Subsequently, a verification operation can be performed in the same manner as the verification operation of the first programming loop PL1. For example, a verification pass can indicate that the memory cell has been read as an off-cell by the corresponding verification voltage.

[0083] As described above, when the memory device 100 programs a multi-level cell (MLC) storing two bits of data, the memory device 100 may respectively verify each memory cell having a program state as a target program state by using the first to third verification voltages V_vfy1 to V_vfy3 .

[0084] A verification voltage may be applied to a selected word line, ie, a word line coupled to a selected memory cell, and Figure 2 The illustrated page buffer may determine verification pass of each memory cell based on a current or a voltage flowing through a bit line coupled to the selected memory cell, respectively.

[0085] Figure 5 This is an example based on Figure 2 Diagram of a page buffer of the illustrated embodiment.

[0086] Reference Figure 5, the page buffer 500 may include a bit line voltage controller 510, a sense latch 520, a first data latch 530, a second data latch 540, and a third data latch 550. However, the number of data latches included in the page buffer 500 is not limited to three; the page buffer 500 may include any suitable number of data latches.

[0087] The number of data latches included is based on the number of bits stored in the memory cell. Figure 5 In the embodiment, it is assumed that each memory cell is a triple-level cell (TLC) storing three bits. However, the number of bits stored in a single memory cell is not limited to three; a page buffer 500 that accommodates memory cells of different storage capacities is consistent with the teachings herein.

[0088] The bit line voltage controller 510 can be coupled to the memory cell via the bit line BL. The bit line voltage controller 510 can store data sensed from the memory cell in the sense latch 520 during a read operation or a verify operation. The bit line voltage controller 510 can control the voltage of the bit line BL based on the data stored in the sense latch 520 during a program operation. When the memory cell is being programmed, the bit line voltage controller 510 can apply a program enable voltage to the bit line BL. When the memory cell is fully programmed, the bit line voltage controller 510 can apply a program inhibit voltage to the bit line BL.

[0089] Sense latch 520 may store a program verification result of a currently executed program loop among a plurality of program loops. Depending on the embodiment, when program verification has passed, sense latch 520 may store a first logic value. When program verification has failed, sense latch 520 may store an inverted first logic value.

[0090] The first data latch 530, the second data latch 540, and the third data latch 550 may store program data to be stored in the memory cell. According to the program data stored in the first data latch 530, the second data latch 540, and the third data latch 550, the memory cell coupled to the bit line BL may be programmed to have a threshold voltage corresponding to one of a plurality of program states.

[0091] According to an embodiment, the first data latch 530 may store LSB data. The second data latch 540 may store CSB data. The third data latch 550 may store MSB data. However, the type of data stored in each data latch is not limited to this configuration.

[0092] The first data latch 530 , the second data latch 540 , and the third data latch 550 may store program data and a program verification result of a previous program loop among a plurality of program loops.

[0093] As mentioned above Figure 4 As described, each of the plurality of program loops may include a program operation and a program verification operation.

[0094] The programming operation may include a bit line setting operation and a program pulse application operation. The bit line setting operation may set the voltage of the bit line to a program inhibit voltage or a program enable voltage depending on whether the memory cell is fully programmed. After the voltage of the bit line is set, the program pulse application operation may apply a program voltage to the word line connected to the memory cell.

[0095] The program verification operation can determine whether the memory cell is fully programmed. When the threshold voltage of the memory cell is higher than or equal to the verification voltage, the memory cell is fully programmed and program verification can pass. When the threshold voltage of the memory cell is lower than the verification voltage, the memory cell is not fully programmed and program verification will fail.

[0096] According to an embodiment, in a program loop (next program loop) after the current program loop, the bit line voltage controller 510 may update the program verification result of the previous program loop stored in the first data latch 530, the second data latch 540, and the third data latch 550 to the sense latch 520. According to an embodiment, the previous program loop may be the program loop immediately before the current program loop. According to an embodiment, the previous program loop may be all program loops before the current program loop.

[0097] According to an embodiment, the bit line voltage controller 510 may update the program verification result of the previous program loop stored in the first, second, and third data latches 530, 540, and 550 to the sense latch 520 during a program operation of the next program loop.

[0098] According to an embodiment, the bit line voltage controller 510 may update the program verification results of the previous program loop stored in the first data latch 530, the second data latch 540, and the third data latch 550 to the sense latch 520 during a bit line setting operation in a program operation of a next program loop.

[0099] According to an embodiment, the bit line voltage controller 510 may update the program verification results of the previous program loop stored in the first, second, and third data latches 530, 540, and 550 to the sense latch 520 after the current program loop is completed.

[0100] The bit line voltage controller 510 may set the voltage of the bit line BL based on the data value of the sense latch 520. The data value of the sense latch 520 may include a program verification result of a current program loop and a program verification result of a previous program loop updated to the sense latch 520.

[0101] The bit line voltage controller 510 may update the program verification result of the current program loop stored in the sense latch 520 to the first data latch 530, the second data latch 540, and the third data latch 550 during the bit line set operation in the next program loop. According to an embodiment, the bit line voltage controller 510 may update the program verification result of the current program loop to at least one of the first data latch 530, the second data latch 540, and the third data latch 550 during the bit line set operation in the next program loop.

[0102] According to an embodiment, the first data latch 530, the second data latch 540, and the third data latch 550 may store a program verification result of a first program loop among first, second, and third program loops sequentially performed and program data to be stored in a memory cell.

[0103] The sense latch 520 may store a program verification result of the second program loop.

[0104] The bit line voltage controller 510 may update the program verification result of the first programming loop stored in the first data latch 530, the second data latch 540, and the third data latch 550 to the sense latch 520 during the program operation of the third programming loop. The bit line voltage controller 510 may set the voltage of the bit line BL coupled to the memory cell based on the program verification result of the first programming loop and the program verification result of the second programming loop updated to the sense latch 520. During the program operation of the third programming loop, the bit line voltage controller 510 may update the program verification result of the second programming loop stored in the sense latch 520 to the first data latch 530, the second data latch 540, and the third data latch 550.

[0105] Figure 6 is a diagram illustrating an operation of updating a program verification result in a program loop.

[0106] Reference Figure 6 , multiple programming loops can be performed. Each of the multiple programming loops can be performed as described above with reference to Figure 4 The described Incremental Step Pulse Programming (ISPP) scheme is performed.

[0107] A program verification operation for each of one or more program states among a plurality of program states may be performed in each program loop.

[0108] exist Figure 6 In the embodiment, among the plurality of program loops, a first program loop PL1, a second program loop PL2, and a third program loop PL3 may be sequentially performed. A program verification operation may be performed for a first program state PV1 among the plurality of program states in the first program loop PL1, the second program loop PL2, and the third program loop PL3. However, the number of program states for which the program verification operation is performed in each program loop is not limited to this embodiment.

[0109] After the second programming loop PL2 is completed, the above reference Figure 5 The described sense latch may store a program verification result Verify_2 of the second program loop PL2. The first, second, and third data latches may store a program verification result Verify_1 of the first program loop PL1, which is a program loop immediately before the second program loop PL2.

[0110] After the third program loop PL3 is completed, the sense latch may store a program verification result Verify_3 of the third program loop PL3. The first, second, and third data latches may store program verification results Verify_1 and Verify_2 of the first and second program loops PL1 and PL2, which are previous program loops of the third program loop PL3.

[0111] Figure 7 It is an example Figure 6 Detailed diagram of the operation of updating program verification results is shown.

[0112] Reference Figure 7 , the first data latch, the second data latch, and the third data latch may store program data DATA1, DATA2, and DATA3 to be stored in the memory cells.

[0113] Times t1, t2, and t3 occur after the second program loop PL2 is completed. Times t1, t2, and t3 may be included in a period in which a bit line setup operation BL Setup of a third program loop PL3 is performed.

[0114] At time t1, the sense latch may store a program verification result Verify_2 of the second program loop PL2. The first, second, and third data latches may store a program verification result Verify_1 of the first program loop PL1 which is a program loop immediately before the second program loop PL2.

[0115] At time t2, the program verification result Verify_1 of the first program loop PL1 stored in the first data latch, the second data latch, and the third data latch can be updated to the sense latch (Verify_1 update). The voltage of the bit line connected to the memory cell can be set based on the program verification result Verify_1 of the first program loop PL1 updated to the sense latch and the program verification result Verify_2 of the second program loop PL2.

[0116] At time t3 , the program verification result Verify_2 of the second program loop PL2 stored in the sense latch may be updated to the first, second, and third data latches (Verify_2 Update).

[0117] After the third program loop PL3 is completed, the first, second, and third data latches may store program data DATA1, DATA2, and DATA3 and program verification results Verify_1 and Verify_2 of the previous first and second program loops PL1 and PL2.

[0118] Figure 8 is a diagram illustrating data values of a data latch according to an embodiment.

[0119] Reference Figure 8 , the memory cell may be a triple-level cell (TLC) that stores three bits.

[0120] The first data latch L1 may store the least significant bit (LSB) data, the second data latch L2 may store the center significant bit (CSB) data, and the third data latch L3 may store the most significant bit (MSB) data.

[0121] According to program data stored in the first, second, and third data latches L1, L2, and L3, the memory cell may be programmed into an erased state ERA and one of a plurality of program states PV1 to PV7.

[0122] The data bits corresponding to the erase state ERA may be “000”. The data bits corresponding to the first program state PV1 may be “100”. The data bits corresponding to the second program state PV2 may be “110”. The data bits corresponding to the third program state PV3 may be “111”. The data bits corresponding to the fourth program state PV4 may be “101”. The data bits corresponding to the fifth program state PV5 may be “001”. The data bits corresponding to the sixth program state PV6 may be “011”. The data bits corresponding to the seventh program state PV7 may be “010”. However, the data bits corresponding to each state are not limited to this embodiment.

[0123] Figure 9 is a diagram illustrating that data values of data latches change as a program operation is performed.

[0124] Reference Figure 9 According to the program data stored in the data latch, the memory cell can be programmed into an erase state ERA and one of a plurality of program states PV1 to PV7. The program operation on the memory cells can be sequentially performed in order from the first program state PV1 to the seventh program state PV7.

[0125] exist Figure 9 In the embodiment of the present invention, the data bits corresponding to the memory cells to be programmed to the first program state PV1 may be "100". The first data latch L1 of the page buffer coupled to the corresponding memory cells may store 0 as the LSB data. The second data latch L2 may store 0 as the CSB data. The third data latch L3 may store 1 as the MSB data.

[0126] According to an embodiment, when a memory cell is completely programmed to a target program state, a data latch of a page buffer coupled to the memory cell may be set to store a data bit having a set pattern. Figure 9 , the setting mode may be “000.” However, the setting mode is not limited to this embodiment.

[0127] For example, when a program operation for the first program state PV1 is completed, a data value of the third data latch L3 of the page buffer coupled to the memory cells programmed to the first program state PV1 may be changed from 1 to 0.

[0128] Figure 10 This is an example based on Figure 5 Diagram of the bit line voltage controller of the illustrated embodiment.

[0129] Reference Figure 10The bit line voltage controller 510 may be coupled to the bit line BL. The bit line BL may be coupled to the sensing node SO according to the page buffer control signal PB_SENSE and the sense amplifier sensing signal SA_SENSE.

[0130] The potential of the bit line BL can be determined according to the following reference Figure 11 The data value of the node QS of the sense latch 520 to be described is precharged to a program inhibit voltage or can be discharged to a program enable voltage. Depending on the embodiment, the program inhibit voltage can be a power supply voltage VCORE. The program enable voltage can be a ground voltage. During the bit line set operation for setting the bit line voltage, the first precharge signal SA_PRECH_N, the sense amplifier sense signal SA_SENSE, the page buffer control signal PB_SENSE, and the sense amplifier discharge signal SA_DISCH can be activated. The period during which the corresponding signals are activated can be set in various ways.

[0131] For example, when the data value of the node QS of the sense latch 520 is the first logic value, the bit line may be precharged. When the data value of the node QS of the sense latch 520 is the inverted first logic value, the bit line may be discharged. Figure 10 In the embodiment, the first logic value may be 0. According to another embodiment, the first logic value may be 1 depending on the type of transistor.

[0132] When stored in the following reference Figure 11 When program verification results of a previous program loop in the first, second, and third data latches 530, 540, and 550 to be described are updated to the sense latch 520, the second precharge signal PRECHSO_N may be activated.

[0133] Figure 11 This is an example based on Figure 5 Diagram of the sense latch and data latch of the illustrated embodiment.

[0134] Reference Figure 11 , the sense latch 520 , the first data latch 530 , the second data latch 540 , and the third data latch 550 may be coupled to one another through the sense node SO.

[0135] During the bit line set operation, the program verification result of the previous program loop stored in the first data latch 530, the second data latch 540, and the third data latch 550 can be updated to the sense latch 520. The voltage of the bit line coupled to the memory cell can be set based on the data value of the node QS of the sense latch 520. The program verification result of the current program loop stored in the sense latch 520 can be updated to the first data latch 530, the second data latch 540, and the third data latch 550.

[0136] Reference Figure 12 An update operation of the program verification result between the sense latch 520 and each data latch is described in detail.

[0137] Figure 12 is a timing diagram illustrating an operation of a page buffer according to an embodiment.

[0138] Reference Figures 10 to 12 A program verification operation may be performed at a program verification step (Verify Step) in the current program loop. The program verification operation may be used to determine whether a memory cell is completely programmed in the current program loop.

[0139] exist Figure 12 In the embodiment, when the potential of a node is high, the data value of the corresponding node may be 1, and when the potential of the node is low, the data value of the corresponding node may be 0. According to another embodiment, when the potential of a node is high, the data value of the corresponding node may be 0, and when the potential of the node is low, the data value of the corresponding node may be 1.

[0140] When the second precharge signal PRECHSO_N is activated during a program verification operation, the sense node SO may be precharged to a high level, and a data value may be 1.

[0141] When the set signal SSET of the sense latch 520 is activated, the data value of the node QS of the sense latch 520 can be set to 1. For example, because the sense node SO has a high level, when the set signal SSET is activated, the inverting node QS_N of the sense latch 520 can be connected to the ground voltage node. Therefore, the inverting node QS_N of the sense latch 520 can be discharged to a low level. Because the data value of the inverting node QS_N of the sense latch 520 is 0, the data value of the node QS of the sense latch 520 can be set to 1.

[0142] After the sense node SO is precharged to a high level, the sense amplifier sense signal SA_SENSE and the page buffer control signal PB_SENSE may be activated. When the sense amplifier sense signal SA_SENSE and the page buffer control signal PB_SENSE are activated, the bit line BL and the sense node SO may be connected.

[0143] When the threshold voltage of the memory cell is higher than or equal to the verification voltage, the bit line current does not flow, so the potential of the sensing node SO can be maintained at a high level. In other words, when the program verification operation passes, the sensing node SO can store 1 as a data value.

[0144] When the threshold voltage of the memory cell is lower than the verification voltage, the bit line current flows, and thus the potential of the sensing node SO may be discharged to a low level. In other words, when the program verification operation fails, the sensing node SO may store 0 as a data value.

[0145] When the reset signal SRST of the sense latch 520 is activated, the data value of the sense node SO may be inverted and stored in the node QS of the sense latch 520 .

[0146] For example, when the data value of the sense node SO is 0, when the reset signal SRST of the sense latch 520 is activated, the data value of the node QS of the sense latch 520 may be maintained at 1, which is the previous data value. When the data value of the sense node SO is 1, when the reset signal SRST of the sense latch 520 is activated, the data value of the node QS of the sense latch 520 may change from 1 to 0.

[0147] The program operation may be performed during a program step in a next program loop after a program verification step (Verify Step) in a current program loop. The program operation may include a bit line setting operation and a program pulse applying operation. Figure 12 In FIG. 5 , as an example, only the bit line setting operation BL Setup in the next program loop is illustrated.

[0148] In the period between tb and tc in the bit line setting operation of the next programming loop, the value of the program verification result of the previous programming loop stored in each of the corresponding nodes Q1, Q2 and Q3 of the first data latch 530, the second data latch 540 and the third data latch 550 can be updated to the data value of the node QS of the sensing latch 520.

[0149] The respective transmission signals TRAN_Q1 , TRAN_Q2 , and TRAN_Q3 of the first, second, and third data latches 530 , 540 , and 550 may be activated.

[0150] When the first data value stored in node Q1 of the first data latch 530, the second data value stored in node Q2 of the second data latch 540, and the third data value stored in node Q3 of the third data latch 550 are all 0, the sense node SO may maintain a previous data value.

[0151] When at least one of the first data value, the second data value, and the third data value is not 0, the data value of the sensing node SO may be set to 0.

[0152] As mentioned above Figure 9As described, when a program operation for a target program state is completed, a program verification operation may pass, and the first data value, the second data value, and the third data value may all be set to 0.

[0153] In other words, when the program operation for the target program state is completed and the program verification operation is passed in the program verification step of the current program loop, the first data value, the second data value, and the third data value may all be set to 0, and the sense node SO may maintain the previous data value. When the program operation for the target program state is not completed and the program verification operation is failed in the program verification step of the current program loop, at least one of the first data value, the second data value, and the third data value is not 0. Therefore, the data value of the sense node SO may be set to 0.

[0154] When the reset signal SRST of the sense latch 520 is activated, when the data value of the sense node SO is 1, the data value of the node QS of the sense latch 520 may be set to 0. When the reset signal SRST of the sense latch 520 is activated, when the data value of the sense node SO is 0, the data value of the node QS of the sense latch 520 may maintain the previous data value.

[0155] In the period between tc and td in the bit line setup operation BL Setup of the next programming loop, the value of the program verification result of the current programming loop stored in the node QS of the sense latch 520 can be updated to the data value of each of the corresponding nodes Q1, Q2 and Q3 of the first data latch 530, the second data latch 540 and the third data latch 550.

[0156] The first precharge signal SA_PRECH_N, the sense amplifier sensing signal SA_SENSE, the page buffer control signal PB_SENSE, and the sense amplifier discharge signal SA_DISCH may be activated.

[0157] The data value of the node QS of the sense latch 520 may be inverted and stored in the sense node SO. When the data value of the node QS of the sense latch 520 is 0, the sense node SO is precharged to a high level, and thus the data value of the sense node SO may be 1. When the data value of the node QS of the sense latch 520 is 1, the sense node SO is discharged to a low level, and thus the data value of the sense node SO may be 0.

[0158] When the data value of the sensing node SO is 1, when the reset signal Q1RST of the first data latch 530 is activated, the data value of the node Q1 of the first data latch 530 may be set to 0. When the reset signal Q2RST of the second data latch 540 is activated, the data value of the node Q2 of the second data latch 540 may be set to 0. When the reset signal Q3RST of the third data latch 550 is activated, the data value of the node Q3 of the third data latch 550 may be set to 0.

[0159] That is, when the data value of the sense node SO is 1, the data value of the sense node SO may be inverted and stored in each of the corresponding nodes Q1, Q2, and Q3 of the first data latch 530, the second data latch 540, and the third data latch 550. According to another embodiment, the reset signal of the data latch may be activated by each data latch separately. According to this embodiment, the value of the current program verification result may be updated only to the data latch whose reset signal is activated.

[0160] When the data value of the sensing node SO is 0, when the reset signal Q1RST of the first data latch 530 is activated, the node Q1 of the first data latch 530 may maintain the previous data value. When the reset signal Q2RST of the second data latch 540 is activated, the node Q2 of the second data latch 540 may maintain the previous data value. When the reset signal Q3RST of the third data latch 550 is activated, the node Q3 of the third data latch 550 may maintain the previous data value.

[0161] Reference Figure 9 , it can be assumed that a program verification operation for the first program state PV1 is performed in a period between ta and tb of the program verification step in the current program loop. In the page buffer connected to the memory cell, the node Q1 of the first data latch 530 may store 0. The node Q2 of the second data latch 540 may store 0. The node Q3 of the third data latch 550 may store 1.

[0162] According to an embodiment, it is assumed that a program verification operation of the current program loop fails in a period between ta and tb of a program verification step in the current program loop.

[0163] In a period between ta and tb of the program verification step in the current program loop, the data value of the node QS of the sense latch 520 may currently be set to 1. Since the program verification operation fails, the data value of the sense node SO may be set to 0. The data value of the node QS of the sense latch 520 may remain 1 as the previous data value.

[0164] In the period between tb and tc in the bit line setting operation of the next program loop, since the first data value, the second data value, and the third data value do not correspond to the case where the first data value stored in the node Q1 of the first data latch 530, the second data value stored in the node Q2 of the second data latch 540, and the third data value stored in the node Q3 of the third data latch 550 are all 0 (for example, Figure 9 As shown, when the first program state PV1 is “100”), the data value of the sense node SO may be set to 0. Since the data value of the sense node SO is 0, the data value of the node QS of the sense latch 520 may be maintained at 1.

[0165] In a period between tc and td of a bit line setting operation in the next program loop, since the data value of the node QS of the sense latch 520 is 1, the sense node SO is discharged to a low level, and the data value of the sense node SO may be set to 0. A program permission voltage having a ground voltage level may be applied to the bit line BL.

[0166] Because the data value of the sensing node SO is 0, the first data value stored in the node Q1 of the first data latch 530 may remain 0. The second data value stored in the node Q2 of the second data latch 540 may remain 0. The third data value stored in the node Q3 of the third data latch 550 may remain 1.

[0167] According to an embodiment, it is assumed that in a period between ta and tb of a program verification step in a current program loop, a program verification operation of the current program loop passes.

[0168] In a period between ta and tb of the program verification step in the current program loop, the data value of the node QS of the sense latch 520 may currently be set to 1. Since the program verification operation passes, the data value of the sense node SO may be set to 1. The data value of the node QS of the sense latch 520 may be set from 1 to 0.

[0169] In the period between tb and tc of the bit line set operation in the next program loop, since the first data value, the second data value, and the third data value do not correspond to the case where the first data value stored in the node Q1 of the first data latch 530, the second data value stored in the node Q2 of the second data latch 540, and the third data value stored in the node Q3 of the third data latch 550 are all 0 (for example, as shown in FIG. Figure 9 As shown, when the first program state PV1 is “100”), the data value of the sensing node SO may be set to 0. Since the data value of the sensing node SO is 0, the data value of the node QS of the sensing latch 520 may be maintained at 0.

[0170] In a period between tc and td of the bit line setup operation BL Setup in the next program loop, since the data value of the node QS of the sense latch 520 is 0, the sense node SO is precharged to a high level, and the data value of the sense node SO may be set to 1. A program inhibit voltage having a power supply voltage level may be applied to the bit line BL.

[0171] Because the data value of the sensing node SO is 1, the first data value stored in the node Q1 of the first data latch 530 may be set to 0. The second data value stored in the node Q2 of the second data latch 540 may be set to 0. The third data value stored in the node Q3 of the third data latch 550 may be set from 1 to 0.

[0172] When all data values stored in the data latches are 0, the data values may indicate that a program verification operation for the first program state PV1 is passed.

[0173] Therefore, a program operation and a program verification operation for the second program state PV2 may be performed in a next program loop after the current program loop.

[0174] Figure 13 is a flowchart illustrating an operation of updating a verification result of a previous program loop to a sense latch according to an embodiment.

[0175] Reference Figure 13 In operation S1301, the page buffer may store a program verification result of a previous program loop among a plurality of program loops in the data latch. The number of data latches included in the page buffer may be one or more.

[0176] In operation S1303 , the page buffer may store a program verification result of a current program loop among a plurality of program loops to a sense latch.

[0177] In operation S1305 , during a program operation of a next program loop among a plurality of program loops, the page buffer may update a program verification result of a previous program loop stored in the data latch to the sense latch.

[0178] Figure 14 is a flowchart illustrating an operation of updating a verification result of a current program loop to a data latch according to an embodiment.

[0179] Reference Figure 14In operation S1401, the page buffer may perform a bit line setting operation of a next program loop based on a program verification result of a previous program loop updated to the sense latch and a program verification result of a current program loop stored in the sense latch.

[0180] In operation S1403 , during a bit line set operation of a next program loop, the page buffer may update a program verification result of a current program loop stored in the sense latch to the data latch.

[0181] According to an embodiment of the present disclosure, a page buffer having improved program verification operation performance and a method of operating the page buffer are provided.

[0182] Although the present invention has been illustrated and described in conjunction with various embodiments, those skilled in the art will appreciate in light of this disclosure that various modifications may be made within the scope of the present invention. Therefore, the present invention encompasses all modifications that fall within the scope of the claims.

[0183] CROSS-REFERENCE TO RELATED APPLICATIONS

[0184] This application claims the benefit of Korean Patent Application No. 10-2020-0092619 filed on July 24, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A method of operating a page buffer, the page buffer performing a plurality of program loops, each program loop including a program operation and a program verification operation, the method comprising the following steps: storing a program verification result of a previous program loop among the plurality of program loops in a data latch; storing a program verification result of a current program loop among the plurality of program loops in a sense latch; as well as During a program operation of a next program loop among the plurality of program loops, a program verification result of the previous program loop stored in the data latch is updated to the sense latch.

2. The method according to claim 1, further comprising the steps of: A bit line setting operation of a program operation of the next program loop is performed based on a program verification result of the previous program loop and a program verification result of the current program loop updated to the sense latch.

3. The method according to claim 2, wherein: The step of performing the bit line setting operation includes applying a program permission voltage or a program inhibition voltage to a bit line coupled to a memory cell based on a program verification result of the previous program loop and a program verification result of the current program loop.

4. The method according to claim 1, further comprising the steps of: During a program operation of the next program loop, a program verification result of the current program loop stored in the sense latch is updated to the data latch.

5. The method according to claim 4, wherein After the program verification result of the previous program loop is updated to the sense latch, updating the program verification result of the current program loop to the data latch is performed.

6. The method according to claim 1, wherein The plurality of programming loops are performed by an incremental step pulse programming scheme.

7. A page buffer, comprising: at least one data latch storing a program verification result of a previous program loop among a plurality of program loops and program data to be stored in a memory cell; a sense latch storing a program verification result of a current program loop following the previous program loop among the plurality of program loops; as well as A bit line voltage controller updates a program verification result of the previous program loop stored in the at least one data latch to the sense latch during a program operation of a next program loop after the current program loop among the plurality of program loops.

8. The page buffer according to claim 7, wherein: The bit line voltage controller controls a voltage of a bit line coupled to the memory cell based on a program verification result of the previous program loop and the program verification result of the current program loop updated to the sense latch.

9. The page buffer according to claim 8, wherein: The bit line voltage controller controls the voltage of the bit line by applying a program permission voltage or a program inhibition voltage to the bit line based on a program verification result of the previous program loop and a program verification result of the current program loop.

10. The page buffer according to claim 7, wherein: The bit line voltage controller updates the program verification result of the current program loop stored in the sense latch to the at least one data latch during a program operation of the next program loop.

11. The page buffer according to claim 7, wherein: The bit line voltage controller stores data sensed from the memory cell in the sense latch or controls a voltage of a bit line coupled to the memory cell based on the data stored in the sense latch.

12. A page buffer, comprising: at least one data latch storing a program verification result of a first program loop among a first program loop, a second program loop, and a third program loop that are sequentially performed and program data to be stored in a memory cell; a sense latch storing a program verification result of the second programming loop; as well as A bit line voltage controller updates a program verification result of the first program loop stored in the at least one data latch to the sense latch during a program operation of the third program loop.

13. The page buffer according to claim 12, wherein: The bit line voltage controller sets a voltage of a bit line coupled to the memory cell based on a program verification result of the first program loop and a program verification result of the second program loop updated to the sense latch.

14. The page buffer according to claim 13, wherein: The bit line voltage controller sets a voltage of the bit line by applying a program permission voltage or a program inhibition voltage to the bit line based on program verification results of the first and second program loops.

15. The page buffer according to claim 12, wherein The bit line voltage controller updates the program verification result of the second program loop stored in the sense latch to the at least one data latch during a program operation of the third program loop.

16. The page buffer according to claim 12, wherein: The bit line voltage controller stores data sensed from the memory cell in the sense latch or controls a voltage of a bit line coupled to the memory cell based on the data stored in the sense latch.

17. The page buffer according to claim 12, wherein: The first program loop, the second program loop, and the third program loop are performed by an incremental step pulse programming scheme.

18. A circuit comprising: a first latch and a second latch, the first latch and the second latch coupled to a bit line; as well as a control logic configured to sequentially execute a first programming loop, a second programming loop, and a third programming loop to store the data latched in the second latch in a memory cell coupled to the bit line, wherein the control logic is configured to control the second latch to further latch a first program verification result of the first programming loop, and to control the first latch to latch a second program verification result of the second programming loop, and Wherein, in the third programming loop, the control logic is configured as follows: controlling the first latch to further latch a first program verification result from the second latch; Based on the first program verify result and the second program verify result from the first latch, setting the bit line, and The second latch is controlled to further latch the second program verification result from the first latch.

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