Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate with an underlying dielectric layer therein; forming a first groove in the underlying dielectric layer; forming a first metal layer in the first groove, the top surface of the first metal layer being lower than the top surface of the underlying dielectric layer; forming a first dielectric layer on the first metal layer, on a part of the sidewalls of the first groove, and on the substrate, with an etching selectivity between the first dielectric layer and the underlying dielectric layer; forming a second dielectric layer on the first dielectric layer, with an etching selectivity between the second dielectric layer and the first dielectric layer; etching the second dielectric layer until the first dielectric layer is exposed to form an opening; etching and removing the first dielectric layer exposed by the opening until the surface of the first metal layer is exposed to form a via hole. The method for forming a semiconductor structure provided by the embodiments of the present invention can form a via hole in self-alignment, reduce the resistance of the interconnect structure, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the development of integrated circuits towards ultra-large scale integrated circuits (ULSI), the circuit density inside them is getting higher and higher, and the number of components contained is increasing continuously, making it impossible for the surface of the wafer to provide enough area to fabricate the required interconnects. In order to meet the increasing demand for interconnects after component miniaturization, the design of multi-layer metal interconnects using vias has become an essential method in ultra-large scale integrated circuit technology.

[0003] However, with the continuous reduction of semiconductor process nodes, the metal interconnects in semiconductor devices are becoming more and more dense, and the critical dimension (CD) of the interconnect structure is also getting smaller and smaller; correspondingly, the process difficulty of forming the interconnect structure is getting greater and greater, and the formation quality of the interconnect structure has a great impact on the performance of the back-end (Back End Of Line, BEOL) circuit, and in severe cases, it will affect the normal operation of the semiconductor structure.

[0004] The existing process technologies for forming interconnect structures can no longer meet the requirements of semiconductor manufacturing, and the electrical performance of the semiconductor structures formed by the existing technologies needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can form vias in self-alignment, reduce the resistance of the vias, and thus improve the performance of the semiconductor structure.

[0006] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a bottom dielectric layer is provided in the substrate; forming a first groove in the bottom dielectric layer; forming a first metal layer in the first groove, the top surface of the first metal layer being lower than the top surface of the bottom dielectric layer; forming a first dielectric layer on the first metal layer, on a part of the sidewalls of the first groove, and on the substrate, the first dielectric layer having an etching selectivity with respect to the bottom dielectric layer; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having an etching selectivity with respect to the first dielectric layer; etching the second dielectric layer until the first dielectric layer is exposed to form an opening; etching and removing the first dielectric layer exposed by the opening until the surface of the first metal layer is exposed to form a via.

[0007] Optionally, the material of the underlying dielectric layer is different from that of the first dielectric layer, and the material of the underlying dielectric layer includes one or more of SiO2, Si3N4, SiOC, SiON, SiCN, SiC, and SiCOH; the material of the first dielectric layer includes one or more of SiO2, Si3N4, SiOC, SiON, SiCN, SiC, SiCOH, Al2O3, AlN, WC, HfO2, Ta2O5, and AlNO.

[0008] Optionally, the material of the second dielectric layer is different from that of the first dielectric layer, and the material of the second dielectric layer includes one or more of SiO2, Si3N4, SiOC, SiON, SiCN, SiC, and SiCOH.

[0009] Optionally, the method for forming the first metal layer in the first groove includes: forming a first metal material film on the sidewalls and bottom of the first groove and on the substrate; performing a reflow process on the first metal material film to form the first metal layer filling the first groove, and the top surface of the first metal layer is lower than the top surface of the substrate.

[0010] Optionally, the material of the first metal layer includes one or more of Cu, Co, Ru, Al, and Ag.

[0011] Optionally, the process parameters of the reflow process include: annealing the first metal material film at a temperature of 200 - 500 °C for an annealing time of 10 - 20 s, and the annealing atmosphere includes one or more of Ar, He, H2, Ne, and Ke.

[0012] Optionally, after forming the first metal layer in the first groove and before forming the first dielectric layer, it further includes: forming a second metal layer on the first metal layer, and the top surface of the second metal layer is flush with the top surface of the substrate.

[0013] Optionally, the method for forming the second metal layer includes: forming a second metal material film on the first metal layer, on the sidewalls of part of the first groove, and on the substrate; performing a reflow process on the second metal material film; performing an electroplating process on the second metal material film after the reflow process, and the second metal material film after the electroplating process covers the substrate surface; performing a planarization process on the second metal material film after the electroplating process until the top surface of the substrate is exposed to form the second metal layer.

[0014] Optionally, after forming the second metal layer and before forming the first dielectric layer, it further includes: removing the second metal layer.

[0015] Optionally, the material of the second metal layer includes Cu, Co, Ru, Al, or Ag, and the material of the second metal layer is different from that of the first metal layer.

[0016] Optionally, after forming the through hole, the method further includes: forming a trench in the second dielectric layer, where the bottom of the trench communicates with the top of the through hole.

[0017] Optionally, before forming the first metal layer in the first groove, the method further includes: forming a diffusion barrier layer on the bottom and side walls of the first groove and on the substrate, where the diffusion barrier layer covers the top surface of the substrate; forming an adhesion layer on the diffusion barrier layer.

[0018] Optionally, the material of the diffusion barrier layer includes one or more of TiN, TaN, WC, Ru, Ta, and Ti.

[0019] Optionally, the material of the adhesion layer includes one or more of Co, Ru, Ta, and Ti.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] A first groove is formed in the underlying dielectric layer, and a first metal layer is formed in the first groove, and the top surface of the first metal layer is lower than the top surface of the substrate, which can increase the linear distance between the subsequently formed through hole and the adjacent first metal layer, thereby reducing leakage current; on the other hand, a first dielectric layer and a second dielectric layer are sequentially formed on the first metal layer, on part of the side walls of the first groove, and on the substrate, and there is an etching selectivity between the first dielectric layer and the underlying dielectric layer and between the first dielectric layer and the second dielectric layer. When etching the second dielectric layer to form a through hole, the etching will stop at the first dielectric layer first to avoid over-etching and damaging the underlying dielectric layer and the first metal layer, which may affect the performance of the semiconductor structure; when etching the first dielectric layer, the etching stops at the underlying dielectric layer, and the underlying dielectric layer on both sides of the first metal layer plays a positioning role, and the through hole can be self-aligned to be formed so that the bottom of the through hole just falls on the first metal layer, reducing the position deviation between the formed through hole and the first metal layer, thereby increasing the contact area between the through hole and the first metal layer, reducing the resistance of the through hole, and improving the performance of the semiconductor structure. Description of the Drawings

[0022] Figures 1 to 15 are schematic structural diagrams corresponding to each step in the process of forming a semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0023] As is known from the background art, vias are commonly used to achieve electrical connection between different metal layers or between a metal layer and a substrate. As the critical dimensions of semiconductor devices continue to shrink, the size of vias has also been continuously reduced. If the via size is too small, the resistance of the via will increase sharply, and at the same time, there will be a problem that the via cannot be aligned with the metal layer. The misalignment between the via and the metal layer will further increase the resistance of the interconnect structure. If the via size is enlarged, it is easy to cause the distance between the via and the adjacent first metal layer to be too close, resulting in a serious leakage current phenomenon, which has an adverse impact on the performance of the semiconductor structure.

[0024] To solve the above problems, the present invention provides a method for forming a semiconductor structure. A first groove is formed in the bottom dielectric layer, and a first metal layer is formed in the first groove. The top of the first metal layer is lower than the top of the bottom dielectric layer. After a via is formed subsequently, the distance between the via and the top of the first metal layer changes from a straight-line distance to an oblique-line distance, reducing the leakage current by increasing the distance between the via and the first metal layer. On the other hand, a first dielectric layer is formed on the first metal layer, on part of the sidewalls of the first groove, and on the substrate. A second dielectric layer is formed on the first dielectric layer. Since there is an etching selectivity between the first dielectric layer and the bottom dielectric layer and between the first dielectric layer and the second dielectric layer, when etching the second dielectric layer, the etching will stop at the first dielectric layer first, avoiding over-etching damage to the bottom dielectric layer and the first metal layer. When etching the first dielectric layer, the etching will stop at the bottom dielectric layer. The bottom metal layers on both sides of the first metal layer play a positioning role, thus achieving the purpose of self-aligning the formation of the via, reducing the alignment deviation between the via and the first metal layer, increasing the contact area between the via and the first metal layer, thereby reducing the resistance of the interconnect structure and improving the performance of the semiconductor structure.

[0025] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0026] Figures 1 to 15 is a schematic structural diagram corresponding to each step in the process of forming a semiconductor structure according to an embodiment of the present invention.

[0027] Refer to Figure 1 , a substrate is provided, and a bottom dielectric layer 110 is provided in the substrate.

[0028] The substrate provides a process operation basis for subsequent processes.

[0029] According to the actual process conditions, functional structures may be formed in the substrate. For example, semiconductor devices such as MOS field-effect transistors may be formed in the substrate, and bottom interconnect structures or resistor structures may also be formed.

[0030] In this embodiment, the substrate includes a substrate 100 and a bottom dielectric layer 110 located on the substrate 100.

[0031] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate 100 includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0032] The bottom dielectric layer 110 is used to insulate the subsequently formed first metal layers from each other. In this embodiment, the bottom dielectric layer 110 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), so as to effectively reduce the parasitic capacitance between the subsequently formed first metal layers, thereby reducing the back-end RC delay. In other embodiments, the material of the bottom dielectric layer may also be silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, aluminum nitride, or aluminum oxide, etc.

[0033] The material of the bottom dielectric layer 110 may be SiOH, SiOCH, or SiOC. In this embodiment, the material of the bottom dielectric layer 110 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing pores.

[0034] Continue to refer to Figure 1 , a first groove 111 is formed in the bottom dielectric layer 111.

[0035] In this embodiment, there are a plurality of first grooves 111 arranged in parallel in the bottom dielectric layer 110, and the first grooves 111 provide space for the subsequent formation of the first metal layer.

[0036] In this embodiment, the method for forming the first groove 111 in the bottom dielectric layer 110 includes: forming a mask layer (not shown) on the bottom dielectric layer 110; performing patterning on the mask layer to form a patterned mask layer; using the patterned mask layer as a mask to etch the bottom dielectric layer 110 to form the first groove 111 in the bottom dielectric layer 110.

[0037] The number and size of the first grooves 111 can be defined according to the requirements of the semiconductor structure.

[0038] In this embodiment, the number of the first grooves 111 is multiple, and the sizes of the first grooves 111 are not equal. The size of the first groove 111 refers to the width D of the first groove 111 along the arrangement direction of the first grooves 111. In other embodiments, the sizes of the first grooves 111 may also be equal.

[0039] In this embodiment, the first groove 111 includes a first type of groove 112 with a width less than or equal to 50 nm, and a second type of groove 113 with a width greater than 50 nm.

[0040] Reference Figure 2 , after forming the first groove 111, a diffusion barrier layer 120 is formed on the bottom and side walls of the first groove 111 and on the substrate, and the diffusion barrier layer 120 covers the top surface of the substrate.

[0041] In this embodiment, specifically, the diffusion barrier layer 120 is formed on the bottom and side walls of the first groove 111 and on the underlying dielectric layer 110.

[0042] The diffusion barrier layer 120 can prevent the conductive material in the first groove 111 from diffusing into the adjacent dielectric layer. The material of the diffusion barrier layer 120 includes one or more of TiN, Ti, TaN, Ta, WC, and Ru. In this embodiment, the material of the diffusion barrier layer 120 is titanium nitride.

[0043] The method for forming the diffusion barrier layer 120 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the method for forming the diffusion barrier layer 120 is atomic layer deposition.

[0044] Continue to refer to Figure 2 , and an adhesion layer 130 is formed on the diffusion barrier layer 120.

[0045] The function of the adhesion layer 130 is to improve the adhesion between the subsequently formed first metal layer and the underlying dielectric layer 110, thereby improving the quality of the first metal layer. The material of the adhesion layer 130 is one or more of Co, Ta, Ti, or Ru. In this embodiment, the material of the adhesion layer 130 is Ru.

[0046] The method for forming the adhesion layer 130 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the method for forming the adhesion layer 130 is chemical vapor substrate method.

[0047] After forming the adhesion layer 130, a first metal layer is formed in the first groove 111, and the top surface of the first metal layer is lower than the top surface of the substrate.

[0048] In this embodiment, the method for specifically forming the first metal layer includes:

[0049] Referring to Figure 3 , a first metal material film 200 is formed on the sidewalls and bottom of the first groove 111 and on the substrate.

[0050] In this embodiment, specifically, the first metal material film 200 is formed on the surface of the adhesion layer 130 and the surface of the bottom dielectric layer 110. The first metal material film 200 is used to form the first metal layer after reflow treatment.

[0051] In this embodiment, the process for forming the first metal material film 200 is a physical vapor deposition process.

[0052] In this embodiment, the material of the first metal material film 200 is Cu; in other embodiments, the material of the first metal material film 200 can also be one or more of Co, Ru, Al, and Ag.

[0053] In this embodiment, the thickness of the first metal material film 200 should neither be too large nor too small. If the thickness of the first metal material film 200 is too large, the subsequently formed first metal layer will completely fill the first groove 111 instead of being lower than the top of the substrate. After forming the through hole subsequently, the distance between the through hole and the adjacent first metal layer will be relatively close, resulting in a large leakage current. If the thickness of the first metal material film 200 is too small, the resistance of the formed first metal layer will be large, and the quality cannot meet the requirements of the semiconductor structure.

[0054] Referring to Figure 4 , the first metal material film 200 is subjected to reflow treatment to form a first metal layer 210 that fills the first groove 111, and the top surface of the first metal layer 210 is lower than the top surface of the substrate.

[0055] In this embodiment, specifically, the top surface of the first metal layer 210 is lower than the top surface of the bottom dielectric layer 110.

[0056] The height difference between the top surface of the first metal layer 200 and the top surface of the bottom dielectric layer 110 should neither be too large nor too small. If the height difference is too large, the height of the formed first metal layer 210 is too small and the resistance is large, unable to meet the requirements of the semiconductor structure. If the height difference is too small, when etching the second metal layer on the first metal layer 210 subsequently, it is easy to over-etch and cause damage to the first metal layer 210, affecting the quality of the first metal layer 210. Therefore, the range of the height difference between the top surface of the first metal layer 200 and the top surface of the bottom dielectric layer 110 is 2 - 10 nm.

[0057] In this embodiment, the process parameters for the reflow treatment of the first metal material film 200 include: annealing the first metal material film 200 at a temperature of 200-500°C for 10-20 s, and the annealing atmosphere includes one or more of Ar, He, H2, Ne, and Ke.

[0058] In this embodiment, since the first metal material film 200 is Cu, the specific reflow temperature is 250-300°C.

[0059] In this embodiment, the reflow treatment of the first metal material film 200 is to prevent the first metal material film 200 from agglomerating at the top corner position of the first groove 111, so that the first metal material film 200 after the reflow treatment will not remain at the top corner of the first groove 111. Therefore, when etching the second metal layer on the first metal layer subsequently, it will not be affected by the remaining first metal material film 200; on the other hand, the reflow treatment of the first metal material film 200 can improve the uniformity of the first metal material film, thereby improving the quality of the formed first metal layer.

[0060] After the reflow treatment, a part of the first metal material film 200 will remain on the bottom dielectric layer 110 far from the first groove 111. Therefore, planarization treatment is required after the reflow treatment.

[0061] Reference Figure 5 , a second metal material film 300 is formed on the first metal layer 210, on the sidewalls of some of the first grooves 111, and on the substrate.

[0062] In this embodiment, the second metal material film 300 is used to form the second metal layer subsequently.

[0063] In this embodiment, the process for forming the second metal material film 300 is a physical vapor deposition process.

[0064] In this embodiment, the material of the second metal material film 300 is Co; in other embodiments, the material of the first metal material film 200 can also be one or more of Cu, Ru, Al, and Ag.

[0065] Reference Figure 6 , the second metal material film 300 is subjected to a reflow treatment.

[0066] In this embodiment, the reflowed second metal material film 300 fills the first groove 111 exposed by the first metal layer 210 and also covers the top surface of the substrate.

[0067] In this embodiment, since the material of the second metal material film 300 is Co, the process parameters for the reflow treatment of Co include: annealing the second metal material film 300 at a temperature of 350-400°C for an annealing time of 10-20 s, and the annealing atmosphere includes one or more of Ar, He, H2, Ne, and Ke.

[0068] In this embodiment, since the first metal material film 200 and the second metal material film 300 are made of different metals and have different reflow temperatures, the reflow treatment of the second metal material film 300 will not affect the formed first metal layer 210, thus avoiding affecting the performance of the first metal layer 210.

[0069] Reference Figure 7 , the second metal material film 300 after the reflow treatment is subjected to electroplating treatment, and the second metal material film 300 after the electroplating treatment covers the surface of the substrate.

[0070] In this embodiment, the function of the electroplating treatment of the second metal material film 300 is to overfill the second metal material film 300 so that it can completely cover the surface of the substrate, as well as the second metal material film 300 and the first metal material film 200 remaining on the substrate surface after the reflow treatment, facilitating subsequent planarization treatment.

[0071] Reference Figure 8 , the second metal material film 300 after the electroplating treatment is subjected to planarization treatment until the top surface of the substrate is exposed, forming a second metal layer 310.

[0072] In this embodiment, the second metal material film 300 is subjected to planarization treatment to remove the second metal material film 300, the first metal material film 200, the adhesion layer 130, and the diffusion barrier layer 120 that are higher than the top of the bottom dielectric layer 110, forming a second metal layer 310, and the top surface of the second metal layer 310 is flush with the top surface of the bottom dielectric layer 110.

[0073] In this embodiment, the process for planarizing the second metal material film 300 is a chemical mechanical polishing process, and this chemical mechanical polishing process enables the second metal material film and the bottom dielectric layer 110 to obtain global planarization, improving the flatness of the top, which is thus beneficial for the subsequent formation of the first dielectric layer.

[0074] Reference Figure 9 , after the planarization treatment forms the second metal layer 310, the second metal layer 310 is removed.

[0075] In this embodiment, specifically, the second metal layer 310 located in the first type of groove 112 is removed. The reason is that the size of the first type of groove 112 is small. Correspondingly, the size of the first metal layer 210 formed in the first type of groove 112 is small. When forming a through hole subsequently, it is easy to have a problem that the through hole and the first metal layer cannot be aligned. Therefore, the underlying dielectric layer 110 on both sides of the first type of groove 112 needs to be used as a self-alignment mark subsequently; while the size of the second type of groove 113 is large, and the sizes of the first metal layer 210 and the second metal layer 310 formed in the second type of groove 113 are also large, and the possibility of alignment deviation when forming a through hole is small. Therefore, the second metal layer 310 in the second type of groove 113 can be not removed.

[0076] In this embodiment, the reasons for removing the second metal layer 310 also include: when forming a through hole on the first metal layer or the second metal layer subsequently, the top of the first metal layer adjacent to the through hole is lower than the top of the underlying dielectric layer, and the straight-line distance between the through hole and the first metal layer can be changed into an oblique-line distance, thereby increasing the distance between the first metal layer and the through hole, reducing the leakage current, and improving the semiconductor performance.

[0077] In other embodiments, the second metal layer 310 in the first groove 111 can also be removed without distinguishing the size of the first groove 111.

[0078] In this embodiment, the method for removing the second metal layer 310 in the first type of groove 112 includes: forming a first mask layer (not shown) on the substrate and the second metal layer 310, and the first mask layer covers the second metal layer 310 in the second type of groove 113; using the first mask layer as a mask, etching to remove the second metal layer 310 in the first type of groove 112; removing the first mask layer.

[0079] In this embodiment, since the materials of the second metal layer 310 and the first metal layer 210 are different, the first metal layer 210 will not be damaged when etching the second metal layer 310.

[0080] In this embodiment, the adhesion layer 130 and the diffusion barrier layer 120 on the sidewall of the first type of groove 112 exposed by the first metal layer 210 are also etched and removed.

[0081] Reference Figure 10 , a first dielectric layer 400 is formed on the first metal layer 210, on a part of the sidewall of the first groove 111, and on the substrate, and there is an etching selectivity between the first dielectric layer 400 and the underlying dielectric layer 110.

[0082] In this embodiment, since the second metal layer 310 in the second type of groove 113 is not removed, the first dielectric layer 400 is further formed on the second metal layer 310.

[0083] In this embodiment, the thickness of the first dielectric layer 400 should neither be too large nor too small. If the thickness of the first dielectric layer 400 is too large, the thickness of the subsequently formed second dielectric layer will be relatively thin, affecting the isolation performance of the second dielectric layer; if the thickness of the first dielectric layer 400 is too small, over-etching is likely to occur when etching the second dielectric layer subsequently, and it cannot stop on the first dielectric layer 400. Therefore, the thickness of the first dielectric layer 400 is 1 - 5 nm.

[0084] The materials of the first dielectric layer 400 and the bottom dielectric layer 110 are different. The material of the first dielectric layer 400 includes one or more of SiO2, Si3N4, SiOC, SiON, SiCN, SiC, SiCOH, Al2O3, AlN, WC, HfO2, Ta2O5, and AlNO. In this embodiment, the material of the first dielectric layer 400 is SiO2.

[0085] In this embodiment, the first dielectric layer 400 and the bottom dielectric layer 110 have a large etching selectivity. When etching the first dielectric layer 400 subsequently, the etching will stop on the bottom dielectric layer 110, avoiding damage to the bottom dielectric layer 110. Moreover, on one hand, the bottom dielectric layer 110 on both sides of the first metal layer 210 can serve as a self-alignment mark, enabling the through-hole to just land on the first metal layer, reducing the resistance of the interconnect structure; on the other hand, it can also limit the size of the bottom of the through-hole, preventing the bottom of the through-hole from expanding to the adjacent first metal layer.

[0086] The method for forming the first dielectric layer 400 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0087] Reference Figure 10 , after forming the first dielectric layer 400, a second dielectric layer 500 is formed on the first dielectric layer 400, and there is an etching selectivity between the second dielectric layer 500 and the first dielectric layer 400.

[0088] The second dielectric layer 500 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), so as to effectively reduce the parasitic capacitance between the subsequently formed first metal layers, thereby reducing the back-end RC delay. In other embodiments, the material of the bottom dielectric layer can also be materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, aluminum nitride, or aluminum oxide.

[0089] In this embodiment, the material of the second dielectric layer 500 is the same as that of the bottom dielectric layer 110, which is SiOCH.

[0090] In this embodiment, both the second dielectric layer 500 and the bottom dielectric layer 110 are made of low-k dielectric materials, which can reduce the parasitic capacitance and the RC delay, thereby improving the electrical performance of the semiconductor structure.

[0091] The method for forming the second dielectric layer 500 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0092] After forming the second dielectric layer 500, the second dielectric layer 500 and the first dielectric layer 400 are etched to form vias.

[0093] In this embodiment, trenches are also formed in the second dielectric layer 500, and the bottom of the trenches communicates with the top of the vias.

[0094] It should be noted that in this embodiment, vias are not formed simultaneously on adjacent first metal layers 210.

[0095] In this embodiment, the specific methods for forming vias and trenches include:

[0096] Refer to Figure 11 , and a second mask layer with a trench pattern is formed on the second dielectric layer 500.

[0097] Specifically, a second hard mask layer 501, a metal hard mask layer 502, a first anti-reflection layer (not shown), and a patterned first photoresist layer (not shown) are sequentially formed on the second dielectric layer 500; using the patterned first photoresist layer as a mask, the first anti-reflection layer and the metal hard mask layer 402 are etched to form trench openings, and the trench openings define the positions and sizes of the trenches to be formed; the patterned first photoresist layer and the first anti-reflection layer are removed.

[0098] In this embodiment, the material of the second hard mask layer 501 is silicon carbide.

[0099] In this embodiment, the method for forming the second hard mask layer 501 is chemical vapor deposition; in other embodiments, physical vapor deposition or atomic layer deposition can also be used to form the second hard mask layer.

[0100] In this embodiment, the material of the metal hard mask layer 502 is titanium nitride; in other embodiments, the material of the metal hard mask layer can also be one or a combination of tantalum nitride, titanium, and tantalum.

[0101] In this embodiment, the method for forming the metal hard mask layer 502 is chemical vapor deposition; in other embodiments, physical vapor deposition or atomic layer deposition may also be used to form the metal hard mask layer.

[0102] Continue to refer to Figure 11 , a third mask layer with a via pattern is formed on the second mask layer, and the via pattern is located in the pattern of the trench.

[0103] In this embodiment, the size d1 of the via pattern is greater than or equal to the width d2 of the first type of groove 112 and less than or equal to the sum of the width d2 of the first type of groove 112 and the distance d3 between the adjacent first groove 111.

[0104] Specifically, a third anti-reflection layer 503, a third hard mask layer 504, and a third photoresist layer (not shown) are sequentially deposited on the exposed second hard mask layer 501 and the metal hard mask layer 502; the third photoresist layer is patterned to form a patterned third photoresist layer 505, defining the position and size of the via.

[0105] Refer to Figure 12 , using the patterned third photoresist layer 505 as a mask, etching the third hard mask layer 504, the third anti-reflection layer 503, the second hard mask layer 501, and the second dielectric layer 500 until the first dielectric layer 400 is exposed, forming an opening 510.

[0106] In this embodiment, since the second dielectric layer 500 and the first dielectric layer 400 have a large etching selectivity ratio, during the etching of the second dielectric layer 500, the etching stops at the first dielectric layer 400, and the first dielectric layer 400 serves as an etching stop layer to avoid damage to the underlying dielectric layer 110 caused by over-etching.

[0107] Refer to Figure 13 , etching and removing the first dielectric layer 400 exposed by the opening 510 until the surface of the first metal layer 210 is exposed, forming a via 520.

[0108] In this embodiment, since the second metal layer 310 in the second type of groove 113 is not removed, the via 520 above the first type of groove 112 is in contact with the first metal layer 210, and the via 520 above the second type of groove 113 is in contact with the second metal layer 310.

[0109] In this embodiment, since the top of the first metal layer 210 is lower than the bottom of the underlying dielectric layer 110, the bottom of the via 520 above the first type of groove 112 is located in the first type of groove 112.

[0110] Reference Figure 14 In this embodiment, after forming the through hole 520, the third mask layer is removed, specifically, the patterned third photoresist layer 505, the third hard mask layer 504, and the third anti-reflection layer 503 are removed.

[0111] Continue to refer Figure 14 , using the second mask layer as a mask, etching the second dielectric layer 500 to form a trench 530 in the second dielectric layer 500.

[0112] In this embodiment, specifically, using the metal hard mask layer 502 as a mask, etching the second hard mask layer 501 and the second dielectric layer 500 to form a trench 530 in the second dielectric layer 500.

[0113] The bottom of the trench 530 is connected to the top of the through hole 520, and the bottom size of the trench 530 is larger than the top size of the through hole 520.

[0114] In other embodiments, the trench may not be formed, and a third mask layer with a through hole pattern may be directly formed on the second dielectric layer, and using the third mask layer as a mask, etching the second dielectric layer and the first dielectric layer in sequence to form a through hole.

[0115] Reference Figure 15 , removing the metal hard mask layer 502 and the second hard mask layer 501; forming a third metal layer 600 in the through hole 520.

[0116] In this embodiment, the third metal layer 600 is also formed in the trench 530, and the top surface of the third metal layer 600 is flush with the top surface of the second dielectric layer 500.

[0117] In this embodiment, the step of forming the third metal layer 600 includes: filling the through hole 520 and the trench 530 with a third metal material layer (not shown), and the third metal material layer also covers the surface of the second dielectric layer 500; performing chemical mechanical polishing on the third metal material layer until the surface of the second dielectric layer 500 is exposed to form the third metal layer 600.

[0118] The material of the third metal layer 600 includes one or more of Cu, Co, Ru, Al, Ag, Au, and W. In this embodiment, the material of the third metal layer 600 is Cu.

[0119] The method of forming the third metal layer 600 includes chemical vapor deposition method, physical vapor deposition method, or electroplating method. In this embodiment, the method of forming the third metal layer 600 is electroplating method.

[0120] In this embodiment, before filling the third metal material layer, the following steps are further included: forming a second barrier layer 521 on the bottom and sidewall surfaces of the through hole 520 and on the bottom and sidewall surfaces of the trench 530; forming a second adhesion layer 522 on the surface of the second barrier layer 521.

[0121] In this embodiment, the function, material, and formation method of the second barrier layer 521 can refer to the description of the foregoing diffusion barrier layer 120, and will not be elaborated herein; the function, material, and formation method of the second adhesion layer 522 can refer to the description of the foregoing adhesion layer 130, and will not be elaborated herein.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, within which there is an underlying dielectric layer; Forming a first groove within the underlying dielectric layer; Forming a first metal layer within the first groove, the top surface of the first metal layer being lower than the top surface of the underlying dielectric layer; Forming a second metal layer on the first metal layer, the top surface of the second metal layer being flush with the top surface of the substrate; Forming a first dielectric layer on the first metal layer, on a partial sidewall of the first groove, and on the substrate, there being an etching selectivity between the first dielectric layer and the underlying dielectric layer; Forming a second dielectric layer on the first dielectric layer, there being an etching selectivity between the second dielectric layer and the first dielectric layer; Etching the second dielectric layer until the first dielectric layer is exposed to form an opening; Etching and removing the first dielectric layer exposed by the opening until the surface of the first metal layer is exposed to form a via hole.

2. The method for forming a semiconductor structure according to claim 1, wherein The material of the underlying dielectric layer is different from the material of the first dielectric layer. The material of the underlying dielectric layer includes one or more of SiO2, Si3N4, SiOC, SiON, SiCN, SiC, and SiCOH; the material of the first dielectric layer includes one or more of SiO2, Si3N4, SiOC, SiON, SiCN, SiC, SiCOH, Al2O3, AlN, WC, HfO2, Ta2O5, and AlNO.

3. The method for forming a semiconductor structure according to claim 2, wherein, The material of the second dielectric layer is different from the material of the first dielectric layer. The material of the second dielectric layer includes one or more of SiO2, Si3N4, SiOC, SiON, SiCN, SiC, and SiCOH.

4. The method for forming a semiconductor structure according to claim 1, wherein, The method for forming the first metal layer within the first groove includes: Forming a first metal material film on the sidewall and bottom of the first groove and on the substrate; Performing a reflow process on the first metal material film to form a first metal layer filling the first groove, the top surface of the first metal layer being lower than the top surface of the substrate.

5. The method for forming a semiconductor structure according to claim 4, wherein, The material of the first metal layer includes one or more of Cu, Co, Ru, Al, and Ag.

6. The method for forming a semiconductor structure according to claim 5, wherein, The process parameters of the reflow process include: annealing the first metal material film at a temperature of 200 - 500°C for an annealing time of 10 - 20 s, and the annealing atmosphere includes one or more of Ar, He, H2, Ne, and Ke.

7. The method for forming a semiconductor structure according to claim 1, wherein, The method for forming the second metal layer includes: Forming a second metal material film on the first metal layer, on a partial sidewall of the first groove, and on the substrate; Performing a reflow process on the second metal material film; Performing an electroplating process on the second metal material film after the reflow process, and the second metal material film after the electroplating process covers the surface of the substrate; Performing a planarization process on the second metal material film after the electroplating process until the top surface of the substrate is exposed to form a second metal layer.

8. The method for forming a semiconductor structure according to claim 7, wherein After forming the second metal layer and before forming the first dielectric layer, it further includes: removing the second metal layer.

9. The method for forming a semiconductor structure according to claim 7, wherein, The material of the second metal layer includes Cu, Co, Ru, Al, or Ag, and the material of the second metal layer is different from that of the first metal layer.

10. The method for forming a semiconductor structure according to claim 1, wherein, After forming the through hole, it further includes: forming a trench in the second dielectric layer, and the bottom of the trench communicates with the top of the through hole.

11. The method for forming a semiconductor structure as claimed in claim 1, wherein, Before forming the first metal layer in the first groove, it further includes: forming a diffusion barrier layer on the bottom and side walls of the first groove and on the substrate, and the diffusion barrier layer covers the top surface of the substrate; forming an adhesion layer on the diffusion barrier layer.

12. The method for forming a semiconductor structure according to claim 11, wherein, The material of the diffusion barrier layer includes one or more of TiN, TaN, WC, Ru, Ta, and Ti.

13. The method for forming a semiconductor structure according to claim 11, wherein, The material of the adhesion layer includes one or more of Co, Ru, Ta, and Ti.

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