Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, wherein at least one surface layer of the substrate is a semiconductor material layer; removing a portion of the semiconductor material layer to form a plurality of parallel fins, wherein the plurality of parallel fins include at least one isolation fin and at least one active fin; forming a support structure above the isolation fin; forming a doping structure on the active fins on both sides of the support structure; forming an interlayer dielectric layer covering the doping structure, wherein the top surface of the interlayer dielectric layer exposes the support structure; removing at least the support structure between the interlayer dielectric layers to form an isolation trench; and forming an isolation structure filled in the isolation trench, thereby improving device performance.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to decrease. To accommodate these smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) has also been shortened. However, as the device channel length shortens, the distance between the source and drain of the device also decreases. As a result, the gate structure's ability to control the channel deteriorates, making it increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to more efficient three-dimensional transistors, such as fin field-effect transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. In addition, FinFETs are more compatible with existing integrated circuit manufacturing than other devices.

[0004] However, the performance of devices formed by current processes is poor. Summary of the Invention

[0005] The embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the device.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, wherein at least one surface layer of the substrate is a semiconductor material layer;

[0008] removing a portion of the semiconductor material layer to form a plurality of parallel fins, wherein the plurality of parallel fins include at least one isolation fin and at least one active fin;

[0009] forming a support structure above the isolation fin;

[0010] forming a doping structure on the active fins on both sides of the support structure;

[0011] forming an interlayer dielectric layer covering the doped structure, wherein a top surface of the interlayer dielectric layer exposes the support structure;

[0012] removing at least the support structure between the interlayer dielectric layers to form an isolation trench;

[0013] An isolation structure is formed to fill the isolation trench.

[0014] Accordingly, an embodiment of the present invention further provides a semiconductor structure, including:

[0015] a substrate having a plurality of parallel fins disposed thereon, wherein the plurality of parallel fins include at least one isolation fin and at least one active fin;

[0016] a support structure located above the isolation fin;

[0017] doping structures on the active fins on both sides of the support structure;

[0018] An interlayer dielectric layer covers the doping structure, wherein a top surface of the interlayer dielectric layer exposes the supporting structure.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0020] In the embodiment of the present invention, during the fin formation process, isolation fins and active fins are simultaneously formed, and a support structure is formed above the isolation fins. Furthermore, doping structures are formed on the active fins on both sides of the support structure. When forming an interlayer dielectric layer covering the doping structure, the top surface of the interlayer dielectric layer exposes the support structure. This allows at least the support structure between the interlayer dielectric layers to be removed at the location of the exposed support structure, forming an isolation trench, and further forming an isolation structure filling the isolation trench. It can be seen that the isolation trench in the embodiment of the present invention is formed based on the support structure on the isolation fin, thereby avoiding the patterning and etching of the interlayer dielectric layer, thereby preventing the impact of this process on the device and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0022] Figures 7 to 21 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0023] Figures 22 to 30 It is a structural schematic diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] As known from the background art, the performance of devices currently formed is poor. The reasons for the poor performance of devices are now analyzed in conjunction with a method for forming a semiconductor structure.

[0025] refer to Figures 1 to 3 ,in, Figure 1 is a top view of the initial semiconductor structure, Figure 2 yes Figure 1 The cross-section along the AA' direction, Figure 3 yes Figure 1 The cross-sectional view along the BB' direction provides an initial semiconductor structure, which includes a substrate 1, a fin 2 and a gate structure 3 spanning the fin, as well as a source-drain doping structure 4 located on both sides of the gate structure, and an interlayer dielectric layer 5 covering the gate structure 3.

[0026] However, in order to achieve isolation between different device regions 31 , an isolation structure for isolating the source / drain doping structure 4 needs to be formed in the isolation region 32 of the interlayer dielectric layer 5 .

[0027] refer to Figure 4 ,in, Figure 4 for Figure 3 Based on the cross-sectional view, a patterned mask layer 6 is formed, and the mask layer exposes a portion of the region 32 between the source and drain doping structures.

[0028] refer to Figure 5 ,in, Figure 5 for Figure 4 According to the cross-sectional view of the base, a portion of the interlayer dielectric layer 5 is removed by etching to form an isolation trench 7 for isolating the interlayer dielectric layer.

[0029] refer to Figure 6 ,in, Figure 6 for Figure 5 Based on the cross-sectional view, an isolation structure 8 is formed in the isolation trench.

[0030] Forming the isolation trenches requires precise patterning to determine their locations. This process is challenging, and even the slightest error can damage the source and drain doping structures during subsequent etching. Furthermore, the etching process can cause stress changes in the interlayer dielectric layer, leading to stress imbalances in the device structure after the isolation structure is formed, thus affecting device performance.

[0031] An embodiment of the present invention provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, wherein at least one surface layer of the substrate is a semiconductor material layer; removing part of the semiconductor material layer to form a plurality of parallel fins, wherein the plurality of parallel fins include at least one isolation fin and at least one active fin; forming a support structure above the isolation fin; forming a doping structure on the active fins on both sides of the support structure; forming an interlayer dielectric layer covering the doping structure, wherein the top surface of the interlayer dielectric layer exposes the support structure; removing at least the support structure between the interlayer dielectric layers to form an isolation trench; and forming an isolation structure filled in the isolation trench.

[0032] In the embodiment of the present invention, during the fin formation process, isolation fins and active fins are simultaneously formed, and a support structure is formed above the isolation fins. Furthermore, doping structures are formed on the active fins on both sides of the support structure. When forming an interlayer dielectric layer covering the doping structure, the top surface of the interlayer dielectric layer exposes the support structure. This allows at least the support structure between the interlayer dielectric layers to be removed at the location of the exposed support structure, forming an isolation trench, and further forming an isolation structure filling the isolation trench. It can be seen that the isolation trench in the embodiment of the present invention is formed based on the support structure on the isolation fin, thereby avoiding the patterning and etching of the interlayer dielectric layer, thereby preventing the impact of this process on the device and improving device performance.

[0033] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 7 to 21 It is a structural schematic diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0035] refer to Figure 7 , providing a substrate 100, wherein at least one surface layer of the substrate is a semiconductor material layer.

[0036] The substrate 100 is used to provide a process platform for the subsequent formation of a device structure. At least one surface layer of the substrate is a semiconductor material layer. The semiconductor material layer is used to subsequently remove a portion of the thickness of the semiconductor material layer 110 in a partial area ( Figure 7 The portion shown above the midpoint dashed line) is formed to form a substrate and a fin protruding from the substrate.

[0037] In this embodiment, the substrate 100 is made of silicon, and the corresponding semiconductor material layer can be a surface layer of the substrate. In other embodiments, the substrate can be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, and the corresponding semiconductor material layer can be the silicon-on-insulator substrate or the germanium substrate.

[0038] Moreover, in other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process basis for the subsequent formation of the substrate, and the second semiconductor layer can serve as the semiconductor material layer to provide a process basis for the subsequent formation of the fin.

[0039] It is understandable that before performing the corresponding process, the substrate may be pre-divided into an active region I and an isolation region II, wherein the active region I is used to form a device structure, and the isolation region II is used to form an isolation structure.

[0040] refer to Figures 8 to 10 ,in, Figure 9 For a three-dimensional image, Figure 10 yes Figure 9 In the cross-sectional view along the CC′ direction, a portion of the semiconductor material layer is removed to form a plurality of parallel fins, wherein the plurality of parallel fins include at least one isolation fin 111 and at least one active fin 112 .

[0041] Among them, among the multiple parallel fins, the active fin 112 is formed in the active area I of the substrate to form a corresponding device structure, and the isolation fin 111 can be formed in the isolation area II of the substrate to occupy a process position for the subsequent formation of an isolation structure, thereby forming a corresponding isolation structure at this position in the subsequent process.

[0042] Correspondingly, a partial thickness of the semiconductor material layer in a partial area may be removed through an etching process, thereby forming a plurality of parallel fins.

[0043] refer to Figures 8 to 10 A support structure 121 is formed above the isolation fin 111 .

[0044] The support structure 121 is used to occupy a process space for the subsequent formation of an isolation structure, so that a corresponding isolation structure is formed in the process space in a subsequent process.

[0045] Based on the isolation fin 111 and the support structure 121 formed above the isolation fin 111, a corresponding isolation structure is formed, thereby avoiding the precise patterning process for determining the isolation groove position and the direct etching of the interlayer dielectric layer in the process of forming the isolation structure, thereby avoiding the patterning and etching process of the interlayer dielectric layer, avoiding the impact of the process on the device, and improving the performance of the device.

[0046] When the support structure is only used to form an isolation structure for isolating a doping structure, it can be formed only at a position between preset doping structures; when the support structure is used to form an isolation structure for isolating the entire device, it can simultaneously extend along the extension direction of the isolation fin to other positions of the isolation fin. This embodiment is explained by taking the isolation of the entire device as an example.

[0047] In an embodiment of the present invention, the thickness of the support structure 121 should not be too large or too small. Specifically, if the thickness of the support structure 121 is too large, the process becomes more difficult, thereby increasing the process cost. If the thickness of the support structure 121 is too small, it will not form sufficient process space, and thus it will not be able to be exposed from the top of the subsequently formed device structure, and thus it will not be possible to mark the formation position of the isolation structure. In an embodiment of the present invention, the thickness of the support structure 121 can be 10nm to 50nm. Optionally, the thickness of the support structure 121 can be 20nm to 40nm.

[0048] The material of the support structure 121 can be one or more insulating materials such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonitride (SiOCN), etc., or it can be one or more semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. When multiple materials are used, it can be a stack of multiple material layers.

[0049] It should be noted that, in the embodiment of the present invention, the support structure 121 and the plurality of parallel fins are formed simultaneously. Accordingly, the process of simultaneously forming the support structure 121 and the plurality of parallel fins may include:

[0050] refer to Figure 8 , forming a support material layer 120 on the semiconductor material layer 110;

[0051] The support material layer 120 is used to form a support structure.

[0052] Correspondingly, the supporting material layer 120 corresponds to one or more insulating materials such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonitride (SiOCN), etc., and can also be one or more semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0053] Correspondingly, the support material layer 120 can be formed by a deposition or epitaxial growth process.

[0054] refer to Figure 9 and Figure 10 , remove the supporting material layer in the partial area and the partial thickness of the semiconductor material layer located in the partial area, use the remaining thickness of the base as the substrate 101, the semiconductor material layer protruding from the substrate as the fin, and the supporting material layer remaining on the fin as the supporting structure 121.

[0055] The support material layer in a partial area and a partial thickness of the semiconductor material layer located in the partial area are removed to achieve patterning of the support material layer and the semiconductor material layer, thereby forming a substrate 101 and fins protruding from the substrate (including isolation fins 111 and active fins 112), and a support structure 121 located on the fins.

[0056] In this embodiment, the substrate 101, the fin protruding from the substrate, and the support structure 121 located on the fin can be implemented in a single patterning process. Specifically, the process of patterning the substrate 101, the fin protruding from the substrate, and the support structure located on the fin includes: forming a patterned first mask layer on the support material layer, the first mask layer covering the area predetermined for forming the fin and exposing other areas except for the area; using the first mask layer as a mask, etching and removing the support material layer in the area exposed by the first mask layer and a portion of the thickness of the semiconductor material layer located in the partial area.

[0057] Among them, the first mask layer can be a photoresist layer or a hard mask layer. In this embodiment, it is preferably a hard mask layer. Correspondingly, the material of the hard mask layer can be one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), and silicon oxycarbonitride (SiOCN).

[0058] It should be noted that the support structure 121 formed in this step is located above the multiple parallel fins. In subsequent steps, it is also necessary to remove the support structure 121 above the active fins 112 among the multiple parallel fins, and only retain the support structure 121 above the isolation fins 111.

[0059] Specifically in this embodiment, refer to Figure 11 After forming the support structure, the step of removing the support structure 121 above the active fin 112 is directly performed to form a support structure 121 located only above the isolation fin 111.

[0060] It should be noted that, in the embodiment of the present invention, after forming the plurality of parallel fins, an isolation layer 102 is further formed on the surface of the substrate where the fins are exposed, so as to isolate the substrate from the device structure on the substrate.

[0061] Furthermore, while forming the isolation layer 102, an isolation film (not shown) may be formed on the surfaces of the isolation fin and the support structure. The isolation film may protect the support structure from being affected in subsequent processes and may also serve as an etch stop layer when etching away the support structure, preventing other structures from being etched. The isolation film may be made of oxide or nitride.

[0062] refer to Figure 12 , forming a dummy gate structure 130 intersecting the active fin 112 and sidewalls 131 located on both sides of the dummy gate structure, wherein the top surface of the dummy gate structure 130 is higher than the top surface of the active fin 112 .

[0063] In which, when the support structure is only formed at a position between preset doping structures, the pseudo gate structure simultaneously spans over the isolation fin; when the support structure extends to other positions of the isolation fin along the extension direction of the isolation fin, the pseudo gate structure can simultaneously span over the isolation fin, or it can intersect with the support structure and be separated by the support structure.

[0064] In an embodiment of the present invention, the dummy gate structure intersects with the support structure, and a top surface of the dummy gate structure is flush with a top surface of the support structure.

[0065] When the isolation layer 102 is formed in this embodiment, a dummy gate structure intersecting the support structure 121 and the active fin 112 and spacers 131 located on both sides of the dummy gate structure 130 are formed on the isolation layer 102 in this step.

[0066] In this embodiment, the dummy gate structure 130 occupies a spatial position for forming a conductive gate in a subsequent process, and the sidewall 131 is used to protect and isolate the sidewalls of the conductive gate formed subsequently, and to define the formation area of ​​the source and drain doping regions in the subsequent process.

[0067] The material of the dummy gate structure 130 is polysilicon. In other embodiments, the material of the dummy gate structure may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, or amorphous carbon.

[0068] The material of the sidewall spacer 131 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, silicon oxynitride, boron nitride or boron carbonitride. The sidewall spacer can be a single-layer structure or a stacked structure, and the material of the sidewall spacer is different from that of the dummy gate structure.

[0069] The steps of forming a dummy gate structure and a sidewall include: forming a dummy gate material layer (not shown) on the isolation layer, which completely covers the active fin and has a surface flush with the top surface of the support structure; forming a patterned gate mask layer on the dummy gate material layer; etching the dummy gate material layer using the gate mask layer as a mask to form a dummy gate structure; forming a sidewall material layer (not shown) conformally covering the dummy gate structure; removing the sidewall material layer on the top of the dummy gate structure and the top of the isolation layer, and retaining the sidewall material layer on the sidewall of the dummy gate structure as a sidewall.

[0070] In this embodiment, the dummy gate material layer may be formed by an epitaxial growth process, and the spacer material layer may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0071] refer to Figure 13 , forming a doping structure 132 on the active fins on both sides of the support structure 121;

[0072] The doped structures serve as the source / drain structures of the device, and together with the gate structure of the device, achieve control of the device. The doped structures are formed on both sides of the support structure, allowing the isolation structure subsequently formed at the support structure location to be located between the doped structures. This avoids the need to determine the location of the isolation trenches in the area between the doped structures through a patterning process, thus preventing possible damage to the doped structures.

[0073] In an embodiment of the present invention, the specific formation position of the doping structure is on the active fins on both sides of the dummy gate structure, and the specific formation process of the doping structure may include: after forming the side wall, etching part of the active fins on both sides of the dummy gate structure to form a doping groove, and forming a doping structure 132 on the doping groove.

[0074] The doping structure 132 may be made of silicon. In other embodiments, the doping structure may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0075] In this embodiment, the doping structure 132 is formed by an epitaxial process.

[0076] When the device is an NMOS device, the doping ions in the doping structure are N-type ions, and the N-type ions can be P ions, As ions or Sb ions; when the device is a PMOS device, the doping ions in the doping structure are P-type ions, and the P-type ions can be B ions, Ga ions or In ions.

[0077] refer to Figures 14 to 16 ,in, Figure 14 For a three-dimensional image, Figure 15 for Figure 14 Cross-section along the DD' direction, Figure 16 for Figure 14 In the cross-sectional view taken along the EE′ direction, an interlayer dielectric layer 140 is formed to cover the doping structure 132 , and a top surface of the interlayer dielectric layer 140 exposes the support structure 121 ;

[0078] Specifically, an interlayer dielectric layer 140 is formed on the substrate where the dummy gate structure 130 is exposed, and the interlayer dielectric layer 140 exposes the top of the support structure 121. The top surface of the interlayer dielectric layer exposes the support structure, which is used to indicate the location where the isolation trench is formed. This allows subsequent processes to directly process the support structure exposed by the interlayer dielectric layer without the need for a patterning process.

[0079] Interlayer dielectric layer 140 is used to electrically isolate adjacent devices. Interlayer dielectric layer 140 is made of an insulating material. In this embodiment, interlayer dielectric layer 140 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may be made of one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.

[0080] Specifically, the steps of forming the interlayer dielectric layer 140 include: forming an interlayer dielectric material layer (not shown) on the dummy gate structure and the exposed portion of the dummy gate structure, the interlayer dielectric material layer covering the top of the dummy gate structure; flattening the interlayer dielectric material layer, removing the interlayer dielectric material layer higher than the supporting structure, and the remaining interlayer dielectric material layer after the flattening process serves as the interlayer dielectric layer 140.

[0081] refer to Figure 17 , removing the dummy gate structure to form a gate trench 150;

[0082] The gate trench 150 is used to form a process space for filling a conductive gate, wherein a dummy gate structure is simultaneously filled on both sides of the isolation fin and the support structure. In this embodiment, the gate trench exposes the isolation fin and the support structure covered by the dummy gate structure.

[0083] The dummy gate structure can be removed by an etching process, such as a wet etching process, a dry etching process, or a combination of wet and dry etching processes. Specifically, when the wet etching process is used, HCl solution can be used.

[0084] refer to Figure 18 , forming a gate dielectric layer 152 and a conductive gate 151 in the gate trench;

[0085] Wherein, based on the gate trench exposing the isolation fin and the support structure, the gate dielectric layer 152 is correspondingly formed on the surfaces of the isolation fin and the support structure at the same time, and the gate dielectric layer 152, the conductive gate 151 and the sidewall 131 constitute a gate structure.

[0086] The conductive gate 151 is a metal gate structure. In this embodiment, the material of the metal gate structure is magnesium-tungsten alloy. In other embodiments, the material of the metal gate structure can also be W, Al, Cu, Ag, Au, Pt, Ni or Ti.

[0087] In an embodiment of the present invention, specifically, a gate dielectric material layer may be first deposited in the gate trench to conformally cover the gate trench and the interlayer dielectric layer. After the gate dielectric material layer is formed, a conductive gate material layer may be further deposited so that the conductive gate material layer completely covers the gate trench and the interlayer dielectric layer. Subsequently, the conductive gate material layer and the gate dielectric material layer on the interlayer dielectric layer are removed by grinding, leaving the remaining conductive gate material layer as the conductive gate and the remaining gate dielectric material layer as the gate dielectric layer. Since the gate trench simultaneously exposes the side surfaces of the isolation fin and the support structure, in this embodiment, the gate dielectric layer may be formed on the side surfaces of the isolation fin and the support structure at the same time.

[0088] In this embodiment, the gate dielectric layer may be made of a high-k dielectric layer. A high-k dielectric layer is a dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the gate dielectric layer may be made of one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0089] Next, refer to Figure 19 and Figure 20 ,in, Figure 20 for Figure 19 In the cross-sectional view along the EE′ direction, at least the support structure between the interlayer dielectric layers is removed to form an isolation trench 160 .

[0090] The isolation trench 160 is formed to provide a process space for subsequently forming an isolation structure.

[0091] In the embodiment of the present invention, the support structure between the interlayer dielectric layers is removed to form the isolation trench, thereby avoiding direct etching of the interlayer dielectric layer, thereby preventing the influence of the etching process on the interlayer dielectric layer.

[0092] It should be noted that, in this step, at least the support structure between the interlayer dielectric layers is removed. It is possible to remove only the support structure between the interlayer dielectric layers to form an isolation structure that only isolates the doped structure, or to completely remove the support structure above the isolation fin (e.g., Figure 18 As shown), an isolation structure is formed to isolate the entire device structure.

[0093] In the embodiment of the present invention, while removing the support structure, at least part of the isolation fins (such as Figure 19 and Figure 20 As shown), thereby improving the isolation effect of the device.

[0094] Specifically, the support structure may be removed by dry etching, wet etching, or a combination of dry etching and wet etching.

[0095] It should be noted that, in the process of removing the support structure by wet etching, the etching selectivity ratio of the support structure and the isolation film is greater than or equal to 10:1, so that the isolation film is used as an etching stop layer to avoid damage to the interlayer dielectric layer.

[0096] Next, refer to Figure 21 , forming an isolation structure 170 filled in the isolation trench.

[0097] The isolation structure 170 is used to isolate the doping structures of adjacent devices.

[0098] The material of the isolation structure 170 can be one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonitride (SiOCN), etc. When multiple materials are used, it can be a stack of multiple material layers.

[0099] Specifically, an isolation material layer can be formed to completely cover the isolation trench and the surface of the interlayer dielectric layer, and the isolation material layer on the surface of the interlayer dielectric layer can be further removed by grinding, so that the isolation material layer remaining in the isolation trench serves as an isolation structure.

[0100] Specifically, the isolation material layer may be formed by a deposition process, and the isolation material layer on the surface of the gate structure may be removed by grinding using a chemical mechanical polishing process.

[0101] It can be seen that the isolation trench in the embodiment of the present invention is formed based on the support structure on the isolation fin, thereby avoiding the patterning and etching of the interlayer dielectric layer, thereby avoiding the impact of this process on the device and improving the performance of the device.

[0102] In the above embodiment, only the surface layer of the fin is used as the channel layer to realize the control of the gate structure over the device. In another embodiment of the present invention, a method for forming a semiconductor structure is further proposed, in which a plurality of independent channel layers are formed inside the gate structure and suspended inside the gate structure to realize the control of the gate structure over the device. Specifically, refer to Figures 22 to 30 It is a structural schematic diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0103] refer to Figure 22 , providing a substrate 200 , wherein at least one surface layer of the substrate 200 is a semiconductor material layer 210 .

[0104] Among them, based on the fact that the semiconductor structure in this embodiment has an independent channel layer, the corresponding fin height can be lower. Correspondingly, in this step, the thickness of the semiconductor material layer is correspondingly lower. The description of this step can refer to the description in the aforementioned embodiment, and the present invention will not be repeated here.

[0105] Next, a portion of the semiconductor material layer is removed to form a plurality of parallel fins, wherein the plurality of parallel fins include at least one isolation fin and at least one active fin.

[0106] The description of this step can refer to the description in the above embodiment, and the present invention will not be repeated here.

[0107] It should be noted that, in this embodiment, after forming a plurality of parallel fins in this step, a channel stack is further formed on the plurality of parallel fins, and the subsequently formed support structure is located on the channel stack above the isolation fins.

[0108] Next, a channel stack is formed on the plurality of parallel fins.

[0109] The channel stack includes alternately stacked sacrificial layers and channel layers, wherein the sacrificial layers are used to be removed in subsequent steps, so that the channel layers are suspended in the conductive gate in subsequent steps, thereby achieving control of the device by the conductive gate.

[0110] In the channel stack, there may be one or more sacrificial layers and channel layers, and the number of sacrificial layers and channel layers alternately stacked in the channel stack may be the same or different. In an embodiment of the present invention, the channel stack includes multiple sacrificial layers and channel layers alternately stacked. The channel stack may include two sacrificial layers and one channel layer alternately stacked, or the channel stack may include three sacrificial layers and two channel layers alternately stacked. This embodiment is described by taking the example of a channel stack including three sacrificial layers and two channel layers alternately stacked.

[0111] Next, a support structure is formed above the isolation fin.

[0112] In order to save process flow and reduce process cost, in an embodiment of the present invention, the support structure is made of the same material as the sacrificial layer in the channel stack, so that a support structure made of the same material as the sacrificial layer can be further formed while forming the sacrificial layer.

[0113] In this embodiment, the support structure, the channel stack, and the fin are formed simultaneously. Specifically, the support structure, the channel stack, and the plurality of parallel fins are formed simultaneously, including:

[0114] refer to Figure 23 , forming a stacked material layer on the semiconductor material layer 210, wherein the stacked material layer includes a sacrificial material layer 220 and a channel material layer 221 that are alternately stacked, and the top layer of the stacked material layer is the sacrificial material layer 220, and the thickness of the sacrificial material layer 220 located on the top layer is greater than or equal to a preset thickness;

[0115] The stacked material layers are used to simultaneously form a channel stack and a support structure located on the channel stack, and a sacrificial material layer with a preset thickness on the top layer of the stacked material layers is used to form the support structure.

[0116] In this embodiment, the material of the sacrificial material layer 220 may be silicon germanium, and the material of the channel material layer 221 may be silicon.

[0117] The number of sacrificial material layers 220 and channel material layers 221 in the stacked material layers matches the number of sacrificial layers and channel layers to be formed. In this embodiment, when the channel stack includes 3 sacrificial layers and 2 channel layers stacked alternately, the stacked material layers correspondingly include 3 sacrificial material layers and 2 channel material layers.

[0118] In this embodiment, an epitaxial growth process is used to form a stacked material layer on the substrate. The epitaxial growth process is not likely to destroy the lattice structure itself, so that the subsequently formed semiconductor structure is not likely to leak electricity.

[0119] In this embodiment, the process of forming the stacked material layer using the epitaxial growth process may include a sacrificial material layer forming stage and a channel material layer forming stage. Different epitaxial gases are introduced in the sacrificial material layer forming stage and the channel material layer forming stage.

[0120] refer to Figure 24 , remove the stacked material layer in a partial area and the semiconductor material layer of partial thickness located in the partial area, use the remaining thickness of the base as the substrate 201, the semiconductor material layer protruding from the substrate as the fin (including the isolation fin 211 and the active fin 212), the sacrificial material layer of a preset thickness remaining below the top surface of the stacked material layer as the support structure 222, and the stacked material layer remaining between the fin and the support structure as the channel stack 223.

[0121] The stacked material layer in a partial area and a partial thickness of the semiconductor material layer located in the partial area are removed to achieve patterning of the stacked material layer and the semiconductor material layer.

[0122] In this embodiment, the substrate 201, the fin protruding from the substrate, and the channel stack 223 located on the fin can be implemented in a single patterning process. Specifically, the process of forming the substrate, the fin protruding from the substrate, and the channel stack located on the fin includes: forming a patterned second mask layer on the stacked material layer, the second mask layer covering the area predetermined for forming the fin and exposing other areas except for the area; using the second mask layer as a mask, etching away the stacked material layer in the area exposed by the second mask layer and a portion of the thickness of the semiconductor material layer located in the partial area. The second mask layer can be a photoresist layer or a hard mask layer, and in this embodiment, a hard mask layer is preferably used.

[0123] It should be noted that the support structure 222 formed in this step is located above the multiple parallel fins. In subsequent steps, it is necessary to remove the support structure above the active fins in the multiple parallel fins, and only retain the support structure above the isolation fins.

[0124] It should be noted that in this embodiment of the present invention, after forming the plurality of parallel fins, an isolation layer 202 is further formed on the substrate surface where the fins are exposed, to isolate the substrate from the device structure thereon. Furthermore, after forming the channel stack and support structure, in this embodiment of the present invention, an isolation film (not shown) is further formed on the surface of the fins, channel stack, and support structure protruding from the isolation layer to protect the fins, channel stack, and support structure protruding from the isolation layer.

[0125] refer to Figure 25, forming a dummy gate structure 230 intersecting the active fin 212 and sidewalls 231 located on both sides of the dummy gate structure 230 , wherein the top surface of the dummy gate structure 230 is higher than the top surface of the active fin 212 .

[0126] When the isolation layer 202 is formed in this embodiment, a dummy gate structure 230 intersecting the support structure 222 and the active fin and spacers 231 located on both sides of the dummy gate structure are formed on the isolation layer 202 in this step.

[0127] In this embodiment, when a channel stack is formed, the top surface of the dummy gate structure 230 in this step is higher than the top surface of the channel stack, so that the subsequently formed channel layer is located inside the dummy gate structure. Since the material of the support structure 222 is the same as the sacrificial layer of the channel stack, to avoid damaging the support structure during the subsequent etching of the channel stack (including the sacrificial layer and the channel layer) on both sides of the dummy gate structure, the top surface of the dummy gate structure 230 in this embodiment of the present invention is further higher than the top surface of the support structure 222 to protect the support structure 222.

[0128] The steps of forming a dummy gate structure and a sidewall include: forming a dummy gate material layer (not shown) on the isolation layer that completely covers the channel stack and the support structure; forming a patterned gate mask layer on the dummy gate material layer; etching the dummy gate material layer using the gate mask layer as a mask to form a dummy gate structure; forming a sidewall material layer (not shown) that conformally covers the dummy gate structure; removing the sidewall material layer on the top of the dummy gate structure and the top of the isolation layer, and retaining the sidewall material layer on the sidewall of the dummy gate structure as a sidewall.

[0129] In an embodiment of the present invention, after forming the sidewalls, a portion of the edge of the channel layer in the channel stack is further exposed, and a channel sidewall is formed on the side of the sacrificial layer, so that the channel layer in the channel stack is connected to the subsequently formed doping structure, and the channel sidewall isolates the doping structure and the conductive gate subsequently formed at the sacrificial layer position. Optionally, the process of exposing a portion of the edge of the channel layer in the channel stack and forming the channel sidewall on the side of the sacrificial layer includes: removing the channel stack and the support structure on both sides of the dummy gate structure on the active fin, and retaining the channel stack and the support structure above the isolation fin; removing a portion of the sidewalls of the sacrificial layer in the remaining channel stack on the active fin to form a first space protruding from the edge of the channel layer; and forming a channel sidewall filling the first space.

[0130] In the step of removing the channel stack and the support structure on both sides of the dummy gate structure on the active fin and retaining the channel stack and the support structure above the isolation fin, a graphic isolation mask layer can be formed to cover the channel stack and the support structure above the isolation fin, exposing the channel stack and the support structure on the active fin, and further using the isolation mask layer and the dummy gate structure as a mask, removing the channel stack and the support structure on both sides of the dummy gate structure on the active fin.

[0131] The first space is used to form channel sidewalls between the channel layers. The material of the channel sidewalls can be the same as or different from that of the sidewalls. Specifically, the material of the channel sidewalls can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0132] Next, refer to Figures 26 to 27 ,in, Figure 26 For a three-dimensional image, Figure 27 for Figure 26 In the cross-sectional view along the EE′ direction, doping structures 232 are formed on the active fins on both sides of the support structure, and the doping structures 232 are connected to the channel layer.

[0133] Wherein, in the step of forming the doping structure on the active fins on both sides of the support structure, the doping structure is located on both sides of the dummy gate structure.

[0134] Next, refer to Figure 28 ,in, Figure 28 for Figure 27 A structural diagram from a viewing angle forms an interlayer dielectric layer 240 covering the doped structure.

[0135] In this embodiment, the interlayer dielectric layer is flush with the top surface of the support structure.

[0136] Specifically, the steps of forming the interlayer dielectric layer include: forming an interlayer dielectric material layer (not shown) on the dummy gate structure and the exposed portion of the dummy gate structure, the interlayer dielectric material layer covering the top of the dummy gate structure; flattening the interlayer dielectric material layer, removing the interlayer dielectric material layer higher than the supporting structure, and using the remaining interlayer dielectric material layer after the flattening process as the interlayer dielectric layer.

[0137] It should be noted that the dummy gate structure in this embodiment is higher than the supporting structure. Furthermore, during the planarization process, a portion of the dummy gate structure that is higher than the supporting structure is also removed.

[0138] Next, removing the dummy gate structure to form a gate trench;

[0139] The gate trench is formed to form a process space for filling the conductive gate.

[0140] In an embodiment of the present invention, after forming the gate trench, the sacrificial layer on the active fin is removed, thereby leaving the channel layer suspended within the gate trench, and allowing the subsequently formed gate structure to surround the channel layer. It is understood that the channel layer above the active fin is supported by the channel sidewalls located on both sides of the gate trench.

[0141] Specifically, the sacrificial layer and the support structure in the channel stack may be removed by using a dry etching process, a wet etching process, or a combination of the two.

[0142] It should be noted that, in the process of removing the sacrificial layer and the support structure in the channel stack, the sacrificial layer and the support structure at the intersection of the isolation fin and the gate trench will be removed at the same time. When it is necessary to retain the support structure at the intersection of the isolation fin and the gate trench, a corresponding mask layer can be formed in the gate trench to cover the isolation fin and the support structure above the isolation fin. Specifically, the process may include: forming a third mask layer in the gate trench, the third mask layer covering the isolation fin, and the channel stack and the support structure located on the isolation fin; using the third mask layer as a mask, etching and removing the sacrificial layer and the support structure in the channel stack; removing the third mask layer to expose the channel stack and the support structure on the isolation fin.

[0143] Next, forming a gate dielectric layer and a conductive gate in the gate trench;

[0144] The gate dielectric layer is formed on the surfaces of the isolation fin and the support structure at the same time, and the gate dielectric layer, the conductive gate and the sidewall constitute a gate structure.

[0145] In this embodiment, the top surfaces of the conductive gate and the dummy gate structure are not in the same plane. Specifically, the top surface of the conductive gate is flush with the top surface of the support structure.

[0146] It should be noted that in the example of retaining the support structure at the intersection of the isolation fin and the gate trench, the gate dielectric layer is simultaneously formed on the surface of the active fin, the channel layer suspended above the active fin, the isolation fin, the channel stack located on the isolation fin, and the surface of the support structure located on the channel stack. Specifically, the process of forming the gate dielectric layer and the conductive gate may include: forming a gate dielectric layer in the gate trench that covers the surface of the active fin, the surface of the suspended channel layer, the surface of the isolation fin, the surface of the channel stack located on the isolation fin, and the surface of the support structure located on the channel stack, and after forming the gate dielectric layer, forming a conductive gate material that completely covers the gate trench and the interlayer dielectric layer; grinding away a portion of the conductive gate material and a portion of the interlayer dielectric layer until the conductive gate material is flush with the top surface of the support structure, and using the remaining conductive gate material as the conductive gate.

[0147] The conductive gate material may be formed by deposition or electroplating, and the polishing step may be performed by a chemical mechanical polishing process.

[0148] For other explanations of this step, please refer to the description in the aforementioned embodiment, and the present invention will not go into details here.

[0149] Next, refer to Figure 29 , at least the support structure between the interlayer dielectric layers is removed to form an isolation trench 260.

[0150] In an embodiment of the present invention, when the support structure is removed, the channel stack below the support structure is also removed, thereby improving the isolation effect of the device.

[0151] Specifically, a wet etching process and / or a dry etching process may be used to remove the support structure and the channel stack below the support structure to form the isolation trench 260 .

[0152] Among them, when a wet etching process is used to remove the support structure and the channel stack under the support structure, the etching selectivity ratio of the support structure and the isolation film is greater than or equal to 10:1. Based on the fact that the sacrificial layer and the support structure are made of the same material, the etching selectivity ratio of the sacrificial layer and the isolation film is greater than or equal to 10:1, thereby using the isolation film as an etching stop layer to avoid damage to the gate electrode layer.

[0153] Next, refer to Figure 30 , forming an isolation structure 270 filled in the isolation trench.

[0154] The isolation trench 270 is used to isolate the doping structures of adjacent devices.

[0155] The material of the isolation trench may be one or more of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonitride (SiOCN), etc. When multiple materials are used, it may be a stack of multiple material layers.

[0156] Specifically, an isolation material layer can be formed to completely cover the isolation trench and the surface of the gate structure, and the isolation material layer on the surface of the gate structure can be further removed by grinding, so that the isolation material layer remaining in the isolation trench serves as the isolation structure. Specifically, the isolation material layer can be formed using a deposition process, and the isolation material layer on the surface of the gate structure can be removed by grinding using a chemical mechanical polishing process.

[0157] It can be seen that the process of forming the isolation structure in the embodiment of the present invention avoids direct etching of the gate structure, thereby avoiding the impact of the etching process on the gate structure and improving the performance of the device.

[0158] Accordingly, an embodiment of the present invention further provides a semiconductor structure. Figure 28 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0159] A substrate 201 having a plurality of parallel fins disposed thereon, wherein the plurality of parallel fins include at least one isolation fin 211 and at least one active fin 212;

[0160] a support structure 222 located above the isolation fin 211;

[0161] Doping structures 232 located on the active fins on both sides of the support structure 222;

[0162] An interlayer dielectric layer 240 covers the doping structure 232 , and a top surface of the interlayer dielectric layer 240 exposes the support structure 222 .

[0163] Optionally, the support structure 222 has a thickness of 10 nm to 50 nm.

[0164] Optionally, a channel stack is also provided on the multiple parallel fins, the support structure 222 is located on the channel stack above the isolation fin 211, the channel stack includes alternatingly stacked sacrificial layers 225 and channel layers 224, and the support structure 222 is made of the same material as the sacrificial layer 225 in the channel stack.

[0165] Optionally, the semiconductor structure further includes a dummy gate structure intersecting with the active fin 212 and sidewalls located on both sides of the dummy gate structure, and channel sidewalls are provided on the sidewalls on both sides of the sacrificial layer of the channel stack.

[0166] Optionally, the material of the support structure 222 can be one or more insulating materials such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonitride (SiOCN), or one or more semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0167] The semiconductor structure of the embodiment of the present invention can be formed by the formation method of the above embodiment, or by other formation methods. For the detailed description of the semiconductor structure of this embodiment, reference can be made to the corresponding description of the above embodiment, and this embodiment will not be repeated here.

[0168] Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention shall be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein at least one surface layer of the substrate is a semiconductor material layer; removing a portion of the semiconductor material layer to form a plurality of parallel fins, wherein the plurality of parallel fins include at least one isolation fin and at least one active fin; forming a support structure above the isolation fin; forming a doping structure on the active fins on both sides of the support structure; forming an interlayer dielectric layer covering the doped structure, wherein a top surface of the interlayer dielectric layer exposes the support structure; removing at least the support structure between the interlayer dielectric layers to form an isolation trench; An isolation structure is formed to fill the isolation trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of at least removing the support structure between the interlayer dielectric layers, the support structure above the isolation fin is completely removed.

3. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the support structure is 10 nm to 50 nm.

4. The method for forming a semiconductor structure according to claim 1, wherein: The support structure and the plurality of parallel fins are formed simultaneously, and forming the support structure and the plurality of parallel fins simultaneously includes: forming a support material layer on the semiconductor material layer; The support material layer in a partial area and the semiconductor material layer of a partial thickness located in the partial area are removed, and the base of the remaining thickness is used as the substrate, the semiconductor material layer protruding from the substrate is the fin, and the support material layer remaining on the fin is used as the support structure.

5. The method for forming a semiconductor structure according to claim 4, wherein: In the step of removing at least the support structure between the interlayer dielectric layers, at least a portion of the isolation fins under the support structure is also removed.

6. The method for forming a semiconductor structure according to claim 1, wherein: A channel stack is further formed on the plurality of parallel fins. The support structure is located on the channel stack above the isolation fins. The channel stack includes sacrificial layers and channel layers that are alternately stacked.

7. The method for forming a semiconductor structure according to claim 6, wherein: The support structure and the sacrificial layer in the channel stack are made of the same material; the support structure, the channel stack, and the fin are formed simultaneously, and the support structure, the channel stack, and the plurality of parallel fins are formed simultaneously, comprising: forming a stacked material layer on the semiconductor material layer, wherein the stacked material layer comprises alternately stacked sacrificial material layers and channel material layers, and a top layer of the stacked material layer is a sacrificial material layer, and a thickness of the sacrificial material layer located on the top layer is greater than or equal to a preset thickness; The stacked material layer in a partial area and the semiconductor material layer of partial thickness located in the partial area are removed, and the base of the remaining thickness is used as the substrate, the semiconductor material layer protruding from the substrate is used as the fin, the sacrificial material layer of a preset thickness remaining below the top surface of the stacked material layer is used as the support structure, and the stacked material layer remaining between the fin and the support structure is used as the channel stack.

8. The method for forming a semiconductor structure according to claim 6, wherein: In the step of removing at least the support structure between the interlayer dielectric layers, the channel stack under the support structure is also removed.

9. The method for forming a semiconductor structure according to claim 4 or 6, wherein: After forming the support structure above the isolation fin and before forming the doping structure on the active fins on both sides of the support structure, the method further includes: The support structure above the active fin is removed.

10. The method for forming a semiconductor structure according to claim 4 or 6, wherein: After forming the support structure above the isolation fin and before forming the doping structure on the active fins on both sides of the support structure, the method further includes: forming a dummy gate structure intersecting the active fin and sidewalls located on both sides of the dummy gate structure, wherein a top surface of the dummy gate structure is higher than a top surface of the active fin; In the step of forming a doping structure on the active fins on both sides of the support structure, the doping structure is located on both sides of the dummy gate structure; In the step of forming an interlayer dielectric layer covering the doped structure, the interlayer dielectric layer is flush with the top surface of the support structure; After forming the interlayer dielectric layer covering the doped structure and before removing at least the support structure between the interlayer dielectric layers, the method further includes: removing the dummy gate structure to form a gate trench; A gate dielectric layer and a conductive gate are formed in the gate trench.

11. The method for forming a semiconductor structure according to claim 10, wherein: When a channel stack is further formed on the plurality of parallel fins, After forming the dummy gate structure intersecting the active fin and the sidewalls on both sides of the dummy gate structure, and before forming the doping structure on the active fin on both sides of the support structure, the method further includes: removing the channel stack and the support structure on both sides of the dummy gate structure on the active fin, and retaining the channel stack and the support structure above the isolation fin; removing part of the sidewalls of the sacrificial layer in the remaining channel stack on the active fin to form a first space protruding from the edge of the channel layer; and forming a channel sidewall filling the first space; In the step of forming a doping structure on the active fins on both sides of the support structure, the doping structure is connected to the channel layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: When a channel stack is further formed on the plurality of parallel fins, In the step of forming a dummy gate structure intersecting the support structure and the active fin and spacers located on both sides of the dummy gate structure, a top surface of the dummy gate structure is higher than a top surface of the channel stack; In the step of forming a gate dielectric layer and a conductive gate in the gate trench, the top surface of the gate structure is flush with the top surface of the support structure.

13. The method for forming a semiconductor structure according to claim 1, wherein: After forming the support structure above the isolation fin and before forming the doping structure on the active fins on both sides of the support structure, the method further includes forming an isolation film on surfaces of the isolation fin and the support structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: The support structure is removed by a wet etching process, and an etching selectivity ratio between the support structure and the isolation film is greater than or equal to 10:

1.

15. The method for forming a semiconductor structure according to claim 12, wherein: The material of the support structure is one or more insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, amorphous carbon, silicon oxycarbonitride, etc., or the material of the support structure is one or more semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

16. A semiconductor structure, characterized in that Formed by the method according to any one of claims 1 to 15, the semiconductor structure comprises: a substrate having a plurality of parallel fins disposed thereon, wherein the plurality of parallel fins include at least one isolation fin and at least one active fin; a support structure located above the isolation fin; doping structures on the active fins on both sides of the support structure; An interlayer dielectric layer covers the doping structure, wherein a top surface of the interlayer dielectric layer exposes the supporting structure.

17. The semiconductor structure according to claim 16, wherein: The thickness of the support structure is 10 nm to 50 nm.

18. The semiconductor structure according to claim 16, wherein: A channel stack is further provided on the multiple parallel fins. The support structure is located on the channel stack above the isolation fins. The channel stack includes alternately stacked sacrificial layers and channel layers. The support structure is made of the same material as the sacrificial layers in the channel stack.

19. The semiconductor structure according to claim 18, wherein: It also includes a dummy gate structure intersecting with the active fin and sidewalls located on both sides of the dummy gate structure, and channel sidewalls are provided on the sidewalls on both sides of the sacrificial layer of the channel stack.

20. The semiconductor structure according to claim 16, wherein The material of the support structure is one or more insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, amorphous carbon, silicon oxycarbonitride, etc., or the material of the support structure is one or more semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

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