A chip packaging structure, its fabrication method and electronic device

Abstract

This application discloses a chip packaging structure, its fabrication method, and an electronic device. The chip packaging structure includes: a first connection layer having opposing upper and lower surfaces; a bare die disposed on the upper surface of the first connection layer; a first conductive structure disposed on the upper surface of the bare die; a first molding compound covering the bare die and the first conductive structure; and a redistribution layer disposed on the first molding compound. At least a portion of the first conductive structure is exposed on the upper surface of the first molding compound, and the redistribution layer is coupled to the first conductive structure. The signals from the bare die are directly led out through the first conductive structure and the redistribution layer, saving space, reducing wiring length and interconnect inductance, and achieving low-loss, high-efficiency signal interconnection between the bare dies. By using the redistribution layer to achieve signal interconnection between the bare dies, matching circuit wiring can be set in the redistribution layer according to the impedance value of the bare die, thereby eliminating the need for components such as capacitors used for coupling impedance, saving space, and reducing design complexity.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure, its fabrication method, and an electronic device thereof. Background Technology

[0002] With the rapid increase in the penetration rate of electronic devices and the booming development of the electronic device market, there is an increasing demand for electronic products to evolve towards miniaturization and thinning while possessing high performance, multifunctionality, high reliability, and convenience. This demand places higher requirements on chip packaging, requiring it to be better, lighter, thinner, with higher packaging density, better electrical and thermal performance, higher reliability, and higher cost-effectiveness.

[0003] 5G power amplifier modules are constantly evolving towards high frequency, high efficiency and miniaturization. The existing wire bonding packaging architecture is limited by the wire diameter and wiring, resulting in large interconnect inductance in the chip packaging structure. In addition, the long wire length in the chip packaging structure leads to large insertion loss, which restricts the evolution of product miniaturization and high performance. Summary of the Invention

[0004] This application provides a chip packaging structure, its fabrication method, and an electronic device for reducing interconnect inductance in the chip packaging structure.

[0005] In a first aspect, this application provides a chip packaging structure, comprising: a first interconnect layer having opposing upper and lower surfaces; a die disposed on the upper surface of the first interconnect layer; a first conductive structure disposed on the upper surface of the die; a first molding compound covering the die and the first conductive structure; and a redistribution layer disposed on the first molding compound; wherein the die is coupled to the upper surface of the first interconnect layer, the first conductive structure is coupled to the die, at least a portion of the first conductive structure is exposed on the upper surface of the first molding compound, i.e., the upper end of the first conductive structure is not covered by the upper surface of the first molding compound, and the redistribution layer is coupled to the first conductive structure.

[0006] In the chip packaging structure provided in this application embodiment, the signals of the bare die are directly led out through the first conduction structure and the redistribution layer, which saves space, reduces wiring length, and reduces interconnect inductance, achieving low-loss and high-efficiency interconnection between bare dies; furthermore, by realizing signal interconnection between bare dies through the redistribution layer, matching circuit wiring can be set in the redistribution layer according to the impedance value of the bare die, thereby eliminating components such as capacitors used for coupling impedance in the chip packaging structure, saving space and reducing design complexity.

[0007] In one possible implementation of this application, the redistribution layer may specifically include a patterned circuit layer and a first protective layer for protecting the patterned circuit layer. The impedance value of the patterned circuit layer can be matched with the impedance value of the die coupled to the patterned circuit layer through the first conductive structure 3. Impedance matching means that, for a preset impedance value of different dies, the patterned circuit layer is set with an impedance value that is approximately the same as or within the tolerance range of that preset impedance value. The impedance value may include parameters such as inductive reactance, capacitive reactance, and resistive resistance. Specifically, the impedance value of the patterned circuit layer can be adjusted to match the impedance value of the coupled die by adjusting parameters such as the thickness and area of ​​the patterned circuit layer. The first protective layer can be solder mask or molding compound, with a thickness of 10µm-40µm.

[0008] In one possible implementation of this application, to achieve high-density integration of the module, a first conductive structure with a high thickness-to-diameter ratio can be set. A high thickness-to-diameter ratio means that the ratio of the thickness to the diameter of the first conductive structure is 2:1 or higher. That is, in the chip packaging structure, at least some of the first conductive structures have a thickness greater than or equal to twice their diameter. Depending on the chip packaging structure requirements, the thickness-to-diameter ratio of some formed first conductive structures can reach 10:1, overcoming the electroplating capability limitation that blind vias formed by laser methods require a thickness ratio ≤1:1, and solving the risk of laser-perforated thin plating layers (<2µm) on the bare die in the power amplifier module being punctured. For example, for multiple bare dies of different thicknesses, a first conductive structure with a larger thickness-to-diameter ratio can be formed on the thinner die, and a first conductive structure with a smaller thickness-to-diameter ratio can be formed on the thicker die. It is worth noting that the diameter of the first conductive structure refers to the diameter (for the case of a circular horizontal cross-section) or the width (for the case of a polygonal horizontal cross-section) of any horizontal cross-section of the first conductive structure.

[0009] In one possible implementation of this application, the chip package structure generally has multiple first conductive structures, any one of which can be multiple solder balls stacked vertically. During fabrication, wire bonding is used, and first conductive structures of varying heights can be formed on the die by stacking solder balls. For example, stacking 1-5 solder balls can form a first conductive structure with a thickness between 50µm and 250µm. By controlling the number of stacked solder balls, the aspect ratio of the formed first conductive structure can be controlled. Generally, fewer solder balls can be stacked on a thicker die, and more solder balls can be stacked on a thinner die. It is worth noting that the aspect ratio of the first conductive structure composed of multiple stacked solder balls refers to the ratio between the maximum thickness of the stacked solder balls and the maximum diameter of each solder ball.

[0010] In another possible implementation of this application, any first conductive structure can also be at least one wire arc. During fabrication, wire bonding is used to form the wire arc on the die. Specifically, the wire arc can be a metal wire of 0.6 mil to 3.0 mil. Generally, the aspect ratio of the first conductive structure formed by the wire arc method is greater than 2:1. It is worth noting that the aspect ratio of the first conductive structure composed of at least one wire arc refers to the ratio between the maximum length of all wire arcs and the maximum diameter of all wire arcs, or the ratio between the maximum length of all wire arcs and the sum of the diameters of all wire arcs. The first conductive structure 3 can be formed in different ways on different dies, or it can be formed in the same way; no limitation is made here.

[0011] In one possible implementation of this application, a first conductive structure can be composed of at least a pair of arcs. During fabrication, both ends of an initial arc can be coupled to the same die, meaning both ends of the initial arc are fixed to the same die, forming an arc shape on the die. After molding and grinding, the final first conductive structure consists of a pair of arcs, with the tops of the arc shapes of the initial arcs broken off to serve as the exposed ends of the two arcs. Having both ends of the initial arcs simultaneously fixed to a single die helps stabilize the morphology of the first conductive structure during the subsequent formation of the first molding layer. Alternatively, in other embodiments of this application, only one end of the initial arc can be coupled to the die, with the other end suspended as the exposed end of the first conductive structure.

[0012] In one possible implementation of this application, the first connecting layer can be a metal-based material or a metal-inorganic composite material. The upper surface of the first connecting layer can have a first pin, which functions as a heat sink and current-carrying element. The die can be specifically coupled to the first pin. Specifically, the die can be coupled to the first pin via a second connecting layer. During fabrication, the die can be bonded to the first pin via the second connecting layer and then sintered to fix it. Alternatively, the die and the first pin can be directly coupled. During fabrication, a eutectic bonding process can be used instead of a sintering process to directly fuse and fix the die's plating to the first pin.

[0013] In one possible implementation of this application, after forming the first conductive structure on the die, the die and the first conductive structure can be encapsulated to form a first encapsulation layer, ensuring that the die and the first conductive structure form an embedded structure within the first encapsulation layer. Subsequently, a high-precision grinding machine can be used to grind the upper surface of the first encapsulation layer to ensure that the end of the first conductive structure is exposed. The upper surface of the first encapsulation layer formed using this process is flush with the exposed end of the first conductive structure. Alternatively, the upper surface of the first encapsulation layer can be lightly ground using a high-precision grinding machine first, and then the end of the first conductive structure can be exposed by laser windowing. The first encapsulation layer formed using this process has through-grooves exposing the end of the first conductive structure, and the redistribution layer has protrusions corresponding to the through-grooves. These protrusions can be located within the through-grooves to facilitate coupling of the first conductive structure. Alternatively, the end of the first conductive structure can be exposed directly by laser windowing. The first molding layer formed by this process has a through groove that exposes the end of the first conductive structure, and the redistribution layer has a protrusion that corresponds one-to-one with the through groove. The protrusion can be located inside the through groove to facilitate coupling of the first conductive structure.

[0014] In one possible implementation of this application, multiple dies can be fixed on the first interconnect layer. The thickness of each die is not limited. Dies of different thicknesses can be coupled to the first interconnect layer, meaning that at least two dies have different thicknesses. This allows the final chip package structure to be compatible with dies of various sizes, with die thicknesses ranging from 80µm to 200µm. First conductive structures are then formed on different dies. After molding the dies and the first conductive structures together to form a first molding layer, the ends of the first conductive structures furthest from the dies are exposed by grinding (or laser windowing, or grinding combined with laser windowing). A redistribution layer coupled to the first conductive structures is then fabricated, enabling signal interconnection between the dies.

[0015] In one possible implementation of this application, when the chip packaging structure is applied to a flip-chip packaging structure, connection terminals can also be provided on the redistribution layer for coupling with an external circuit board. Specifically, the connection terminals can be solder, solder balls, solderable plating, or solderable connecting posts.

[0016] In one possible implementation of this application, to achieve high-density integration of three-dimensional stacking, it may further include: a chip disposed on a redistribution layer, a second conductive structure disposed on the redistribution layer, a second molding compound covering the chip and the second conductive structure, a third connection layer disposed on the second molding compound, and a second protective layer for protecting the third connection layer; wherein, the second protective layer may be solder mask or molding compound, at least a portion of the second conductive structure is exposed on the upper surface of the second molding compound, the third connection layer is coupled to the second conductive structure, and the chip's signals can be led out through the redistribution layer, the second conductive structure and the third connection layer to achieve vertical interconnection.

[0017] In one possible implementation of this application, the second conductive structure can specifically be multiple solder balls or at least one wire arc or pin stacked vertically. Specifically, the stacked balls or wire arc can be formed by wire bonding, and the pin can be formed by soldering. Similar to the first conductive structure, the second conductive structure can also be configured with a high aspect ratio to achieve high-density integration of the module.

[0018] In one possible implementation of this application, the chip, the second conductive structure, the second molding layer, the third connection layer, and the second protective layer can be considered as constituting a stacked structure. The chip packaging structure may include at least one stacked structure. Only one stacked structure may be provided in the chip packaging structure. When the chip packaging structure is applied to a flip-chip packaging structure, connection terminals may also be provided on the third connection layer for coupling with an external circuit board. The connection terminals may specifically be solder, solder balls, solderable plating, or solderable connection pillars. Alternatively, a multi-layer stacked structure may be provided in the chip packaging structure. The chip in the bottommost stacked structure is coupled to the redistribution layer, and the chips in other stacked structures are coupled to the third connection layer of the next lower stacked structure. When the chip packaging structure is applied to a flip-chip packaging structure, connection terminals may also be provided on the third connection layer of the topmost stacked structure for coupling with an external circuit board. The connection terminals may specifically be solder, solder balls, solderable plating, or solderable connection pillars.

[0019] In one possible implementation of this application, to achieve double-sided signal output of the chip package structure, i.e., signal output on the lower surface side of the first connection layer, the first connection layer may have a second pin, which may also be referred to as an external pin. A third conduction structure may be provided on the second pin. The third conduction structure may be formed simultaneously with the first conduction structure. The first molding layer covers the third conduction structure, and at least a portion of the third conduction structure is exposed on the upper surface of the first molding layer, so that the redistribution layer is coupled to the second pin of the first connection layer through the third conduction structure. The signal of the die can flow through the first conduction structure, the redistribution layer, the second conduction structure, and the first connection layer to the lower surface of the first connection layer for output.

[0020] In one possible implementation of this application, in order to achieve high-density integration of the module, the third conductive structure is similar to the first conductive structure and can be set with a high thickness-to-diameter ratio. According to the chip packaging structure requirements, the thickness-to-diameter ratio of the formed third conductive structure can reach 10:1, which breaks through the electroplating capability limitation that the blind hole formed by laser method needs to have a thickness ratio of ≤1:1, and solves the risk that the thin plating layer (<2um) in the power amplifier module will be perforated by laser.

[0021] In one possible implementation of this application, after forming a first conductive structure on the die and a third conductive structure on the second pin, the die, the first conductive structure, and the third conductive structure can be encapsulated to form a first encapsulation layer, ensuring that the die, the first conductive structure, and the third conductive structure simultaneously form embedded structures within the first encapsulation layer. Subsequently, a high-precision grinding machine can be used to grind the upper surface of the first encapsulation layer to ensure that the ends of the first and third conductive structures are exposed. The upper surface of the first encapsulation layer formed using this process is flush with the exposed ends of the first and third conductive structures. Alternatively, laser windowing can be used to directly expose the ends of the first and third conductive structures. The first encapsulation layer formed using this process has through-grooves exposing the ends of the first and third conductive structures, and the redistribution layer has protrusions corresponding to the through-grooves, with the protrusions located within the through-grooves. Alternatively, a small amount of grinding can be performed on the upper surface of the first molding layer using high-precision grinding equipment. Then, the ends of the first conductive structure and the third conductive structure can be exposed by laser windowing. The first molding layer formed by this process has through grooves that expose the ends of the first and third conductive structures. The redistribution layer has protrusions that correspond one-to-one with the through grooves, and the protrusions are located inside the through grooves. Alternatively, when the end of the first conductive structure is higher than the end of the third conductive structure, a high-precision grinding machine can be used to grind the upper surface of the first encapsulation layer until the end of the first conductive structure is exposed. Then, a laser windowing method can be used to expose the end of the third conductive structure. The upper surface of the first encapsulation layer formed by this process is flush with the exposed end of the first conductive structure, and the first encapsulation layer has a through groove for exposing the end of the third conductive structure. The redistribution layer has protrusions that correspond one-to-one with the through grooves, and the protrusions are located within the through grooves.

[0022] In one possible implementation of this application, the third conductive structure can specifically be multiple solder balls or at least one wire arc or pin stacked vertically. Specifically, the stacked balls or wire arc can be formed on the second pin by wire bonding, or the pin can be formed by soldering. The upper surface of the third conductive structure should be as flush as possible with the upper surface of the first conductive structure; that is, when forming the third conductive structure, the sum of the thicknesses of the first conductive structure and the die can be used as a reference.

[0023] In one possible implementation of this application, a third conductive structure can be composed of at least a pair of arcs. During fabrication, both ends of an initial arc can be coupled to the same second pin, meaning both ends of the initial arc are fixed to the same second pin, forming an arc shape on the second pin. After molding and grinding, in the final third conductive structure, the initial arc is divided into a pair of arcs, with the top of the arc shape of the initial arc broken off to serve as the exposed ends of the two arcs. Having both ends of the initial arc simultaneously fixed to a second pin helps stabilize the morphology of the third conductive structure during the subsequent formation of the first molding layer. Alternatively, in other embodiments of this application, only one end of the initial arc can be coupled to the second pin, with the other end suspended as the exposed end of the third conductive structure.

[0024] Secondly, this application provides a method for fabricating a chip packaging structure, comprising the following steps: providing a first interconnect layer having opposing upper and lower surfaces; coupling a die to the upper surface of the first interconnect layer; forming a first conductive structure on the upper surface of the die; molding the die and the first conductive structure so that the die and the first conductive structure are embedded in the first molding layer; exposing the end of the first conductive structure on the upper surface of the first molding layer; and forming a redistribution layer on the first molding layer.

[0025] In one possible implementation of this application, the die can be bonded to the first connecting layer via the second connecting layer and then sintered to fix the die to the first connecting layer; alternatively, the die can be fixed to the first connecting layer via eutectic bonding.

[0026] In one possible implementation of this application, a plurality of solder balls stacked vertically on a die can be formed using a wire bonding process. Alternatively, a wire arc can be formed on the upper surface of the die using a wire bonding process, with one end of the wire arc coupled to the die, or both ends of the wire arc coupled to the die.

[0027] In one possible implementation of this application, the end of the first conductive structure can be exposed on the upper surface of the first molding layer by grinding, or by laser windowing.

[0028] In one possible implementation of this application, when the upper surface of the first connection layer has external pins, while forming the first conductive structure on the die, it may also include: forming a third conductive structure on the external pins; while molding the die and the first conductive structure so that the die and the first conductive structure are embedded in the first molding layer, it may also include: molding the third conductive structure so that the third conductive structure is embedded in the first molding layer; while exposing the end of the first conductive structure on the upper surface of the first molding layer, it may also include: exposing the end of the third conductive structure on the upper surface of the molding layer.

[0029] In one possible implementation of this application, a plurality of solder balls stacked vertically on an external pin can be formed using wire bonding; or, a wire arc can be formed on an external pin using wire bonding, with one end of the wire arc coupled to the external pin, or both ends of the wire arc coupled to the external pin; or, a pin can be formed on an external pin using soldering.

[0030] In one possible implementation of this application, the end of the third conductive structure can be exposed on the upper surface of the first molding layer by grinding; or, the end of the third conductive structure can be exposed on the upper surface of the first molding layer by laser windowing.

[0031] In one possible implementation of this application, the following steps may also be included: fixing a chip on a redistribution layer; forming a second conductive structure on the redistribution layer; encapsulating the chip and the second conductive structure so that the chip and the second conductive structure are embedded in the second encapsulation layer; exposing the end of the second conductive structure on the upper surface of the second encapsulation layer; and forming a third connection layer and a second protective layer on the second encapsulation layer.

[0032] In one possible implementation of this application, a plurality of solder balls stacked vertically on the redistribution layer can be formed using a wire bonding process; or, a wire arc can be formed on the redistribution layer using a wire bonding process, with one end of the wire arc coupled to the redistribution layer, or both ends of the wire arc coupled to the redistribution layer; or, a soldering method can be used to form pins on the redistribution layer.

[0033] Thirdly, this application provides an electronic device, including a circuit board and a chip package structure electrically interconnected with the circuit board, either a first aspect or a second aspect of the chip package structure.

[0034] In one possible implementation of this application, when a third conductive structure is provided within the chip package structure, the chip package structure can be a positive mounting structure, and the circuit board can be disposed on the lower surface of the first interconnection layer in the chip package structure.

[0035] In one possible implementation of this application, when the chip package structure includes connection terminals, the chip package structure can be a flip-chip structure, and the circuit board can be disposed on the upper surface of the chip package structure and coupled to the connection terminals. In this case, a heat dissipation structure can also be provided on the lower surface of the first connection layer in the chip package structure. Attached Figure Description

[0036] Figure 1 This is a cross-sectional schematic diagram of an existing chip packaging structure.

[0037] Figure 2 This is a cross-sectional schematic diagram of another existing chip packaging structure;

[0038] Figure 3a This is a cross-sectional view of a chip packaging structure provided in an embodiment of this application;

[0039] Figure 3b This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0040] Figure 4 The chip packaging structure and provided in the embodiments of this application Figure 1 The relationship between the test frequency band and interconnect capacitance values ​​of the chip package structure is shown.

[0041] Figure 5a This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0042] Figure 5b This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0043] Figure 6 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0044] Figure 7 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0045] Figure 8 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0046] Figure 9 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0047] Figure 10 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0048] Figure 11 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0049] Figure 12 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0050] Figure 13 This is a cross-sectional view of a chip packaging structure provided in another embodiment of this application;

[0051] Figure 14 This is a schematic flowchart illustrating the method for fabricating the chip packaging structure provided in the embodiments of this application;

[0052] Figure 15 A cross-sectional structural schematic diagram of an electronic device provided in an embodiment of this application;

[0053] Figure 16 This is a cross-sectional structural diagram of an electronic device provided in another embodiment of this application.

[0054] Figure label:

[0055] 01-Linear arc; 02-Molding layer; 03-Blind via; 1-First connection layer; 2-Die; 3-First conductive structure; 4-First molding layer; 5-Recirculation layer; 51-Graphic circuit layer; 52-First protective layer; 6-Second connection layer; 7-Connection terminal; 8-Chip; 9-Second conductive structure; 10-Second molding layer; 11-Third connection layer; 111-Second protective layer; 12-Second pin; 13-Third conductive structure; 14-Circuit board; 15-Heat dissipation structure. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0057] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more” unless the context clearly indicates otherwise.

[0058] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0059] Furthermore, the same reference numerals in the figures denote the same or similar structures, and therefore, repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0060] Reference Figure 1 Current chip packaging solutions involve fixing the die to a heat sink frame, then using wire bonding (the wire can be gold or copper wire) to achieve signal interconnection between dies and between the die and pins. This is followed by module molding to form a system-in-package (SIP) module. As 5G power amplifier modules continue to evolve towards high frequency, high efficiency, and miniaturization, the wire bonding packaging architecture is limited by the wire diameter and wiring, resulting in large interconnect inductance in the chip package structure. Furthermore, the long wire length in the chip package structure leads to high insertion loss, hindering the evolution of product miniaturization and high performance.

[0061] Reference Figure 2 Another vertical fan-out chip packaging method involves fixing the die to a heat sink frame for module molding. Then, a blind via (03) is created in the molding layer (02) using a laser windowing method. Copper plating is then used on the blind via (03) to achieve signal interconnection between dies and between the die and pins. The plating capability of forming the blind via (03) using the laser windowing method is limited to a blind via thickness ratio ≤1:1, restricting the embedded integration of dies of different thicknesses. Furthermore, forming the blind via (03) using the laser windowing method requires the pad plating thickness of the die to be at least 5µm. Since pads are typically made of copper, custom-made dies are required, which is detrimental to reducing manufacturing costs.

[0062] The chip packaging structure proposed in this application can be applied to various electronic devices, such as smartphones, smart TVs, smart TV set-top boxes, personal computers (PCs), wearable devices, and smart broadband devices. It should be noted that the chip packaging structure proposed in this application is intended for application in these and any other suitable types of electronic devices, including but not limited to. The chip packaging structure, its fabrication method, and the electronic device provided in this application will be described in detail below with reference to the accompanying drawings.

[0063] Figure 3a A cross-sectional schematic diagram of a chip packaging structure provided in an embodiment of this application is shown as an example. (Refer to...) Figure 3a In one embodiment of this application, the chip packaging structure may include: a first connection layer 1 having opposing upper and lower surfaces; a die 2 disposed on the upper surface of the first connection layer 1; a first conductive structure 3 disposed on the upper surface of the die 2; a first molding compound 4 covering the die 2 and the first conductive structure 3; and a redistribution layer 5 disposed on the first molding compound 4. The die 2 is coupled to the upper surface of the first connection layer 1, the first conductive structure 3 is coupled to the die 2, at least a portion of the first conductive structure 3 is exposed on the upper surface of the first molding compound 4 (i.e., the upper surface of the first molding compound 4 does not cover the upper end of the first conductive structure 3), and the redistribution layer 5 is coupled to the first conductive structure 3. It is worth noting that the upper surface of a component mentioned in this application refers to the upper surface of the component along the vertical direction, and the lower surface of a component refers to the lower surface of the component along the vertical direction.

[0064] In the chip packaging structure provided in this application embodiment, the signal of the bare die 2 is directly led out through the first conduction structure 3 and the redistribution layer 5, which saves space, reduces the wiring length, and reduces the interconnection inductance, thereby achieving low-loss and high-efficiency interconnection of signals between the bare dies 2. Furthermore, by realizing the signal interconnection between the bare dies 2 through the redistribution layer 5, the circuit wiring that matches the impedance value of the bare die 2 can be set in the redistribution layer, thereby eliminating the need for components such as capacitors used for coupling impedance in the chip packaging structure, saving space and reducing design complexity.

[0065] Figure 4 The chip packaging structure and embodiment of this application are illustrated by way of example. Figure 1 The diagram illustrates the relationship between the test frequency band and interconnect capacitance values ​​for the chip package structure. (Refer to...) Figure 4 A is Figure 1 The interconnect inductance value obtained from testing the chip package structure shown is shown in the figure. B is the interconnect inductance value obtained from testing the chip package structure shown in this application, which is different from the value used in the prior art. Figure 1Compared with the traditional arc 01 interconnection method, the signal output method using the first conduction structure 3 and rewiring layer 5 of this application can reduce the interconnection inductance by 20%, increase the bandwidth by 25%, reduce signal transmission loss, and improve the power amplifier efficiency by 1-2 percentage points.

[0066] In this application, "die 2" refers to the unpackaged die of a chip. Each die 2 is an unpackaged chip with independent functionality, and it can consist of one or more circuits. Specific dies 2 include, but are not limited to, application-specific integrated circuits (ASICs), memory dies, and analog dies. Dies 2 typically consist of a silicon substrate and circuit layers disposed on the silicon substrate. The circuit layers generally contain semiconductor devices such as transistors and various functional circuits.

[0067] In this embodiment of the application, multiple bare sheets 2 can be fixed on the first connecting layer 1, and the thickness of each bare sheet 2 is not limited. Further reference can be made. Figure 3a Dies 2 of different thicknesses can be coupled onto the first connection layer 1, meaning there are at least two dies 2 with different thicknesses, so that the final chip package structure can be compatible with dies 2 of various sizes, with the thickness of the dies 2 ranging from 80um to 200um. Then, first conductive structures 3 are formed on different dies 2. After molding the dies 2 and the first conductive structures 3 together to form a first molding layer 4, the ends of the first conductive structures 3 furthest from the dies 2 are exposed by grinding (or laser windowing, or grinding plus laser windowing). Next, a redistribution layer 5 coupled to the first conductive structures 3 is fabricated, and signal interconnection between the dies 2 is achieved in the redistribution layer 5.

[0068] Figure 3b A cross-sectional view of another chip packaging structure provided in an embodiment of this application is illustrated. (Refer to...) Figure 3b As an optional solution in this application, for bare wafers 2 of different thicknesses, a corresponding recessed structure can be set in the first connecting layer 1. That is, for the thicker bare wafer 2, a groove can be set at the corresponding position in the first connecting layer 1, and the bare wafer 2 is placed in the groove. The thinner bare wafer 2 can be directly coupled to the upper surface of the first connecting layer 1. Alternatively, for the thinner bare wafer 2, a protrusion can be set at the corresponding position in the first connecting layer 1, and the bare wafer 2 is placed on the protrusion. Ultimately, the upper surfaces of bare wafers 2 of different thicknesses are made as flush as possible, which can reduce the maximum thickness of the first conductive structure 3 located on bare wafers 2 of different thicknesses.

[0069] In this embodiment of the application, reference can continue to be made to Figure 3aThe redistribution layer 5 may specifically include a patterned circuit layer 51 and a first protective layer 52 for protecting the patterned circuit layer 51. The impedance value of the patterned circuit layer 51 can be matched with the impedance value of the bare die 2 coupled to the patterned circuit layer 51 through the first conductive structure 3. Impedance matching means that for different preset impedance values ​​of the bare die 2, the patterned circuit layer 51 is set with an impedance value that is approximately the same as or within the tolerance range of the preset impedance value. The impedance value may include parameters such as inductive reactance, capacitive reactance, and resistive resistance. Specifically, the impedance value of the patterned circuit layer 51 can be adjusted to match the impedance value of the coupled bare die 2 by adjusting parameters such as the thickness and area of ​​the patterned circuit layer 51. The first protective layer 52 can be solder mask or molding compound, with a thickness of 10um-40um.

[0070] In this embodiment of the application, the first connecting layer 1 can be a metal-based material or a metal-inorganic composite material, with a thermal conductivity of 300 W / mK to 800 W / mK and a thickness of 0.10 mm to 1.00 mm. The upper surface of the first connecting layer 1 can have a first pin, which functions as a heat sink and current conveyor. The bare die 2 can be specifically coupled to the first pin. (See also...) Figure 3a The die 2 can be coupled to the first pin via a second connecting layer 6. The second connecting layer 6 can be a metal-based bonding material with a thermal conductivity of 100 W / mK to 300 W / mK, and its thickness can be 10 μm to 40 μm. During fabrication, the die 2 can be bonded to the first pin via the second connecting layer 6 and then sintered for fixation. Alternatively, the die 2 and the first pin can be directly coupled. During fabrication, a eutectic bonding process can be used instead of sintering to directly fuse the plating of the die 2 to the first pin. Eutectic bonding typically requires heating to 300-500 degrees Celsius under pressure, while sintering typically requires heating to around 200 degrees Celsius.

[0071] In this embodiment of the application, to achieve high-density integration of the module, a first conductive structure 3 with a high thickness-to-diameter ratio can be provided. A high thickness-to-diameter ratio refers to a thickness-to-diameter ratio of 2:1 or higher for the first conductive structure. That is, in the chip packaging structure, at least some of the first conductive structures 3 have a thickness greater than or equal to twice their diameter. Depending on the chip packaging structure requirements, the thickness-to-diameter ratio of some formed first conductive structures 3 can reach 10:1, overcoming the electroplating capability limitation that blind vias formed by laser require a thickness ratio ≤1:1. This solves the risk that the thin plating layer (<2µm) of the bare die 2 in the power amplifier module will be perforated by laser. For example, for multiple bare dies 2 with different thicknesses, a first conductive structure 3 with a larger thickness-to-diameter ratio can be formed on the thinner bare die 2, and a first conductive structure 3 with a smaller thickness-to-diameter ratio can be formed on the thicker bare die 2. (Continue to refer to...) Figure 3aFor example, the die 2 on the left is thicker and the die 2 on the right is thinner. Therefore, a first conductive structure 3 with a high aspect ratio can be formed on the die 2 on the left, and a first conductive structure 3 with a low aspect ratio can be formed on the die 2 on the right. It is worth noting that the diameter of the first conductive structure 3 refers to the diameter (for the case where the horizontal cross-section is circular) or the width (for the case where the horizontal cross-section is polygonal) of any horizontal cross-section of the first conductive structure 3.

[0072] Figure 5a A cross-sectional schematic diagram of another chip packaging structure provided in an embodiment of this application is illustrated. In this embodiment of the application, reference is made to... Figure 5a In a chip package structure, there are generally multiple first conductive structures 3. Each first conductive structure 3 can be a plurality of solder balls stacked vertically. During fabrication, wire bonding is used, and first conductive structures 3 of varying heights can be formed on the die 2 by stacking solder balls. For example, stacking 1-5 solder balls can form a first conductive structure 3 with a thickness between 50µm and 250µm. By controlling the number of stacked solder balls, the aspect ratio of the formed first conductive structure 3 can be controlled. Generally, fewer solder balls can be stacked on a thicker die 2, and more solder balls can be stacked on a thinner die 2. It is worth noting that the aspect ratio of the first conductive structure 3 composed of multiple stacked solder balls refers to the ratio between the maximum thickness of the stacked solder balls and the maximum diameter of each individual solder ball.

[0073] Figure 5b A cross-sectional view of another chip packaging structure provided in an embodiment of this application is illustrated. (Refer to...) Figure 5b Any first conductive structure 3 can also be at least one wire arc. During fabrication, wire bonding is used to form the wire arc on the bare die 2. Specifically, the wire arc can be a metal wire of 0.6 mil to 3.0 mil. Generally, the aspect ratio of the first conductive structure 3 formed by the wire arc method is greater than 2:1. It is worth noting that the aspect ratio of the first conductive structure 3 composed of at least one wire arc refers to the ratio between the maximum length of all wire arcs and the maximum diameter of all wire arcs, or the ratio between the maximum length of all wire arcs and the sum of the diameters of all wire arcs. Different methods can be used to form the first conductive structure 3 on different bare dies 2, or the same method can be used; no limitation is made here.

[0074] You can continue to refer to Figure 5bIn this embodiment of the application, a first conductive structure 3 can be composed of at least a pair of arcs. During fabrication, both ends of an initial arc can be coupled to the same die 2, that is, both ends of an initial arc are fixed to the same die 2, so that the initial arc forms an arc shape on the die 2. After molding and grinding, in the final first conductive structure 3, the initial arc is divided into a pair of arcs, and the top of the arc shape of the initial arc is broken off to serve as the exposed ends of the two arcs. The two ends of the initial arc are simultaneously fixed to a die 2, which is beneficial to stabilizing the morphology of the first conductive structure 3 when the first molding layer 4 is subsequently formed. Alternatively, in other embodiments of the application, the initial arc can also be coupled to the die 2 with only one end, and the other end can be suspended as the exposed end of the first conductive structure 3.

[0075] You can continue to refer to Figure 5a and Figure 5b In this embodiment of the application, after forming the first conductive structure 3 on the die 2, the die 2 and the first conductive structure 3 can be encapsulated to form a first encapsulation layer 4 with a thickness of about 400 μm, ensuring that the die 2 and the first conductive structure 3 form an embedded structure within the first encapsulation layer 4. Subsequently, a high-precision grinding machine can be used to grind the upper surface of the first encapsulation layer 4. For example, the thickness of the first encapsulation layer 4 after grinding can be about 280 ± 10 μm to ensure that the end of the first conductive structure 3 is exposed. The upper surface of the first encapsulation layer 4 formed by this process is flush with the exposed end of the first conductive structure 3. Figure 6 A cross-sectional view of another chip packaging structure provided in this application embodiment is illustrated. Alternatively, a high-precision grinding device can be used to lightly grind the upper surface of the first molding layer 4, and then a laser window can be used to expose the end of the first conductive structure 3, as shown in the figure. Figure 6 The first molding layer 4 formed using this process has a through-groove exposing the end of the first conductive structure 3. The redistribution layer 5 has protrusions corresponding to the through-groove, which can be located within the through-groove to facilitate coupling of the first conductive structure 3. Alternatively, the end of the first conductive structure 3 can be directly exposed by laser windowing, as described in the following section. Figure 6 The first molding layer 4 formed by this process has a through groove that exposes the end of the first conductive structure 3. The redistribution layer 5 has a protrusion that corresponds to the through groove. The protrusion can be located in the through groove so as to facilitate the coupling of the first conductive structure 3.

[0076] You can continue to refer to Figure 5a , Figure 5b and Figure 6In this embodiment of the application, when the chip packaging structure is applied in a flip-chip packaging structure, a connection terminal 7 can also be provided on the redistribution layer 5. The connection terminal 7 is used for coupling with an external circuit board. Specifically, the connection terminal 7 can be solder, solder ball, solderable plating, or solderable connecting post.

[0077] Figure 7 A cross-sectional view of another chip packaging structure provided in an embodiment of this application is illustrated. In another embodiment of this application, in order to achieve high-density integration through three-dimensional stacking, other chips may also be disposed on the redistribution layer 5. (Refer to...) Figure 7 In this embodiment of the application, the system may further include: a chip 8 disposed on the redistribution layer 5; a second conductive structure 9 disposed on the redistribution layer 5; a second molding compound 10 covering the chip 8 and the second conductive structure 9; a third connection layer 11 disposed on the second molding compound 10; and a second protective layer 111 for protecting the third connection layer 11. The second protective layer 111 may be solder mask or molding compound, with a thickness of 10µm-40µm. At least a portion of the second conductive structure 9 is exposed on the upper surface of the second molding compound 10. The third connection layer 11 is coupled to the second conductive structure 9. The signal of the chip 8 can be led out through the redistribution layer 5, the second conductive structure 9, and the third connection layer 11, thus achieving vertical interconnection. It should be noted that the vertical interconnection mentioned in this application refers to electrical connection achieved in the vertical direction (the thickness direction of the chip 8).

[0078] Figure 8 A cross-sectional schematic diagram of another chip packaging structure provided in an embodiment of this application is illustrated. In this embodiment of the application, the chip 8, the second conductive structure 9, the second molding layer 10, the third connection layer 11, and the second protective layer 111 can be considered as constituting a stacked structure, and the chip packaging structure may include at least one stacked structure. Further reference can be made to... Figure 7 In a chip packaging structure, only one layer of stacked structure can be set. When the chip packaging structure is applied to a flip-chip packaging structure, a connection terminal 7 can also be set on the third connection layer 11. The connection terminal 7 is used to couple with an external circuit board. The connection terminal 7 can be solder, solder ball, solderable plating, or solderable connection post. Or refer to Figure 8 In another embodiment of this application, a multi-layer stacked structure can be provided in the chip packaging structure. The chip 8 in the bottommost stacked structure is coupled to the redistribution layer 5, and the chip 8 in the other stacked structures is coupled to the third connection layer 11 in the next stacked structure. When the chip packaging structure is applied to the flip-chip packaging structure, a connection terminal 7 can also be provided on the third connection layer 11 in the topmost stacked structure. The connection terminal 7 is used to couple with an external circuit board. The connection terminal 7 can specifically be solder, solder ball, solderable plating layer or solderable connection post.

[0079] Figure 9 A cross-sectional view of another chip packaging structure provided in an embodiment of this application is illustrated. (Refer to...) Figure 7 and Figure 8 Each layer of the stacked structure can contain at least one chip 8. Chips 8 can be of different types, such as resistors, capacitors, inductors, or control ICs. (See reference...) Figure 9 As an alternative, chip 8 can be omitted in any of the above-mentioned stacked structures. Instead, components such as the second conductive structure 9, the second molding layer 10, and the third connection layer 11 can be provided. This stacked structure can play a role in preventing signal interference.

[0080] In this embodiment of the application, the second conductive structure 9 can specifically be a plurality of solder balls or at least one wire arc or pin stacked vertically. Specifically, the plurality of solder balls or at least one wire arc can be formed by wire bonding, and the pin can be formed by welding. Similar to the first conductive structure 3, the second conductive structure 9 can also be provided with a high aspect ratio to achieve high-density integration of the module. Furthermore, the parameter settings and specific manufacturing method of the second conductive structure 9 can refer to the first conductive structure 3, and will not be described in detail here.

[0081] Figure 10 A cross-sectional view of another chip packaging structure provided in an embodiment of this application is illustrated. In another embodiment of this application, in order to achieve double-sided signal output of the chip packaging structure, that is, signal output on one side of the lower surface of the first connection layer 1, the first connection layer 1 may have a second pin 12, which may also be referred to as an external pin. (Refer to...) Figure 10 A third conductive structure 13 can be set on the second pin 12. The third conductive structure 13 can be formed simultaneously with the first conductive structure 3. The first molding layer 4 covers the third conductive structure 13. At least a portion of the third conductive structure 13 is exposed on the upper surface of the first molding layer 4, so that the redistribution layer 5 is coupled to the second pin 12 of the first connection layer 1 through the third conductive structure 13. The signal of the bare die 2 can flow through the first conductive structure 3, the redistribution layer 5, the second conductive structure 9, and the first connection layer 1 to the lower surface of the first connection layer 1 for extraction.

[0082] In this embodiment of the application, in order to achieve high-density integration of the module, the third conductive structure 13 is similar to the first conductive structure 3, and a third conductive structure 13 with a high thickness-to-diameter ratio can be set. According to the chip packaging structure requirements, the thickness-to-diameter ratio of the formed third conductive structure 13 can reach 10:1, which breaks through the electroplating capability limitation that the blind hole formed by laser method needs to have a thickness ratio of ≤1:1, and solves the risk that the thin plating layer (<2um) in the power amplifier module will be laser-pierced (Figure 98).

[0083] In this embodiment of the application, the third conductive structure 13 can specifically be a plurality of solder balls or at least one wire arc or pin stacked in a vertical direction. Specifically, the stacked balls or wire arc can be formed on the second pin 12 by wire bonding, or the pin can be formed by soldering. The upper surface of the third conductive structure 13 should be as flush as possible with the upper surface of the first conductive structure 3. That is, when forming the third conductive structure 13, the sum of the thicknesses of the first conductive structure 3 and the bare die 2 can be used as a reference. For example, a wire arc of 340±20um can be formed as the third conductive structure 13. Figure 10 The example given is only the third conductive structure 13, which includes a pair of arcs. In actual products, the specific configurations of the first conductive structure 3 and the third conductive structure 10 can be combined with each other.

[0084] Similarly, in this embodiment of the application, a third conductive structure 13 can be composed of at least a pair of arcs. During fabrication, the two ends of an initial arc can be coupled to the same second pin 12, that is, both ends of an initial arc are fixed to the same second pin 12, so that the initial arc forms an arc shape on the second pin 12. After molding and grinding, in the final third conductive structure 13, the initial arc is divided into a pair of arcs, and the top of the arc shape of the initial arc is broken off to serve as the two exposed ends of the arcs. The two ends of the initial arc are simultaneously fixed to a second pin 12, which is beneficial to stabilizing the morphology of the third conductive structure 13 when the first molding layer 4 is subsequently formed. Alternatively, in other embodiments of the application, the initial arc can also be coupled to the second pin 12 with only one end, and the other end can be left suspended as the exposed end of the third conductive structure 13.

[0085] Figure 11 An exemplary cross-sectional view of another chip packaging structure provided in an embodiment of this application is shown. Figure 12 An exemplary cross-sectional view of another chip packaging structure provided in an embodiment of this application is shown. Figure 13 A cross-sectional view of another chip packaging structure provided in this application embodiment is illustrated. In this embodiment, after forming a first conductive structure 3 on the die 2 and a third conductive structure 13 on the second pin 12, the die 2, the first conductive structure 3, and the third conductive structure 13 can be plastic-encapsulated to form a first plastic-encapsulation layer 4 with a thickness of approximately 400 μm, ensuring that the die 2, the first conductive structure 3, and the third conductive structure 13 are simultaneously embedded within the first plastic-encapsulation layer 4. Subsequently, a high-precision grinding machine can be used to grind the upper surface of the first plastic-encapsulation layer 4. For example, the thickness of the first plastic-encapsulation layer 4 after grinding can be approximately 280 ± 10 μm to ensure that the ends of the first conductive structure 3 and the third conductive structure 13 are exposed. (Refer to...) Figure 10The upper surface of the first molding layer 4 formed using this process is flush with the exposed ends of the first conductive structure 3 and the third conductive structure 13. Alternatively, the ends of the first conductive structure 3 and the third conductive structure 13 can be exposed directly using laser windowing, as shown in the reference. Figure 11 The first molding layer 4 formed using this process has through grooves exposing the ends of the first conductive structure 3 and the third conductive structure 13. The redistribution layer 5 has protrusions corresponding to the through grooves, which are located within the through grooves. Alternatively, the upper surface of the first molding layer 4 can be lightly ground using high-precision grinding equipment, and then the ends of the first conductive structure 3 and the third conductive structure 13 can be exposed by laser windowing, as shown in the reference. Figure 11 The first molding layer 4 formed using this process has through grooves exposing the ends of the first conductive structure 3 and the third conductive structure 13. The redistribution layer has protrusions corresponding to the through grooves, and the protrusions are located within the through grooves. Alternatively, when the end of the first conductive structure 3 is higher than the end of the third conductive structure 13, the upper surface of the first molding layer 4 can be ground first using a high-precision grinding machine until the end of the first conductive structure 3 is exposed, and then the end of the third conductive structure 13 can be exposed by laser windowing, as shown in the reference. Figure 12 The upper surface of the first molding layer 4 formed by this process is flush with the exposed end of the first conductive structure 3, and the first molding layer 4 has a through groove for exposing the end of the third conductive structure 13. The redistribution layer 5 has protrusions corresponding to the through grooves, and the protrusions are located inside the through grooves. When the end of the third conductive structure 13 is higher than the end of the first conductive structure 3, the upper surface of the first molding layer 4 can be ground with a high-precision grinding machine until the end of the third conductive structure 13 is exposed. Then, the end of the first conductive structure 3 can be exposed by laser windowing. (Refer to...) Figure 13 The upper surface of the first molding layer 4 formed by this process is flush with the exposed end of the third conductive structure 13, and the first molding layer 4 has a through groove that exposes the end of the first conductive structure 3. The redistribution layer 5 has a protrusion that corresponds to the through groove, and the protrusion is located in the through groove.

[0086] Based on the same technical concept, this application also provides a method for fabricating a chip packaging structure. Since the principle of this fabrication method is similar to that of the aforementioned chip packaging structure, the implementation of this fabrication method can be referred to the implementation of the aforementioned chip packaging structure, and the repeated parts will not be described again.

[0087] Figure 14 A schematic flowchart illustrating the fabrication method of the chip packaging structure provided in this application is shown as an example. See also... Figure 14 The preparation method mainly includes the following steps:

[0088] S1. A first connecting layer 1 having an upper surface and a lower surface is provided.

[0089] S2. The bare die 2 is coupled and fixed on the upper surface of the first connecting layer 1.

[0090] Specifically, the bare die 2 can be bonded to the first connecting layer 1 through the second connecting layer 6 and then sintered to fix the bare die 2 to the first connecting layer 1; or, the bare die 2 can be fixed to the first connecting layer 1 through a eutectic bonding process.

[0091] S3. A first conductive structure 3 is formed on the upper surface of the bare die 2.

[0092] Specifically, a wire bonding process can be used to form multiple solder balls stacked vertically on the die 2; or, a wire arc can be formed on the die 2 using a wire bonding process, with one end of the wire arc coupled to the die 2, or both ends of the wire arc coupled to the die 2.

[0093] As an optional solution, when the upper surface of the first connection layer 1 has a second pin 12, i.e., an external pin, the formation of the first conductive structure 3 on the bare die 2 may also include: forming a third conductive structure 13 on the second pin 12. Specifically, multiple solder balls stacked vertically on the second pin 12 can be formed using wire bonding, or a wire arc can be formed on the second pin 12 using wire bonding, with one end of the wire arc coupled to the second pin 12, or both ends of the wire arc coupled to the second pin 12, or a pin can be formed on the second pin 12 using soldering.

[0094] S4, the die 2 and the first conductive structure 3 are encapsulated in the first encapsulation layer 4.

[0095] As an alternative, while encapsulating the die 2 and the first conductive structure 3, so that the die 2 and the first conductive structure 3 are embedded in the first encapsulation layer 4, it may also include: encapsulating the third conductive structure 13, so that the third conductive structure 13 is embedded in the first encapsulation layer 4.

[0096] S5. The end of the first conductive structure 3 is exposed on the upper surface of the first molding layer 4.

[0097] Specifically, the end of the first conductive structure 3 can be exposed on the upper surface of the first encapsulation layer 4 by grinding, or by laser windowing to expose the end of the first conductive structure 3 on the upper surface of the first encapsulation layer 4.

[0098] As an optional solution, while exposing the end of the first conductive structure 3 on the upper surface of the first molding layer 4, it also includes exposing the end of the third conductive structure 13 on the upper surface of the molding layer.

[0099] Specifically, the end of the third conductive structure 13 can be exposed on the upper surface of the first molding layer 4 by grinding; or the end of the third conductive structure 13 can be exposed on the upper surface of the first molding layer 4 by laser windowing.

[0100] S6. A redistribution layer 5 is formed on the first molding layer 4. Specifically, a patterned circuit layer 51 and a first protective layer 52 for protecting the patterned circuit layer 51 may be formed.

[0101] As an alternative, connection terminals 7 can also be formed on the redistribution layer 5, which are used for coupling with external circuit boards.

[0102] As an optional solution, it can continue to be referred to Figure 14 In this embodiment of the application, the following steps may also be included:

[0103] S7. Fix chip 8 on redistribution layer 5.

[0104] S8. A second conductive structure 9 is formed on the redistribution layer 5.

[0105] As an alternative, wire bonding can be used to form multiple solder balls stacked vertically on the redistribution layer 5; as another alternative, wire bonding can be used to form a wire arc on the redistribution layer 5, with one end of the wire arc coupled to the redistribution layer 5, or both ends of the wire arc coupled to the redistribution layer 5; as yet another alternative, soldering can be used to form pins on the redistribution layer 5.

[0106] S9, the encapsulated chip 8, and the second conductive structure 9 are embedded in the second encapsulation layer 10.

[0107] S10, the end of the second conductive structure 9 is exposed on the upper surface of the second molding layer 10.

[0108] S11, A third connecting layer 11 and a second protective layer 111 are formed on the second molding layer 10.

[0109] As an alternative, a connection terminal 7 can also be formed on the third connection layer 11, which is used to couple with an external circuit board.

[0110] Based on the same technical concept, this application also provides an electronic device, which includes a circuit board and a chip packaging structure from any of the above-described technical solutions or a chip packaging structure prepared by any of the preparation methods, electrically interconnected with the circuit board. The electronic devices proposed in the embodiments of this application include, but are not limited to, smartphones, smart TVs, smart TV set-top boxes, personal computers (PCs), wearable devices, smart broadband, etc., which will not be listed here. Since the principle by which this electronic device solves the problem is similar to the aforementioned chip packaging structure and preparation method, the implementation of this electronic device can refer to the implementation of the aforementioned chip packaging structure and preparation method; repeated details will not be elaborated further.

[0111] Figure 15 A cross-sectional structural schematic diagram of an electronic device provided in an embodiment of this application is illustrated. (Refer to...) Figure 15 In this embodiment of the application, when a third conductive structure 13 is provided in the chip package structure, the chip package structure can be a positive mounting structure, and the circuit board 14 can be disposed on the lower surface of the first connection layer 1 in the chip package structure.

[0112] Figure 16 A cross-sectional structural schematic diagram of another electronic device provided in an embodiment of this application is illustrated. (Refer to...) Figure 16 In another embodiment of this application, when the chip package structure is provided with connection terminals 7, the chip package structure can be a flip-chip structure, and the circuit board 14 can also be disposed on the chip package structure and coupled to the connection terminals 7. In this case, a heat dissipation structure 15 can also be provided on the lower surface of the first connection layer 1 in the chip package structure.

[0113] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A chip packaging structure, characterized in that, include: The first connecting layer has opposing upper and lower surfaces; A bare die is disposed on the upper surface of the first interconnect layer and coupled to the first interconnect layer; A first conductive structure is disposed on the upper surface of the die and coupled to the die; A first molding layer covers the bare die and the first conductive structure, with at least a portion of the first conductive structure exposed on the upper surface of the first molding layer; A redistribution layer is disposed on the first molding layer and coupled to the first conductive structure; A second conductive structure is disposed on the redistribution layer; A second molding layer covers the second conductive structure, with at least a portion of the second conductive structure exposed on the upper surface of the second molding layer; The third connecting layer is disposed on the second molding layer and coupled to the second conductive structure; The second conductive structure, the second molding layer, and the third connection layer constitute a stacked structure, and the chip packaging structure includes at least one layer of the stacked structure, wherein no chip is disposed in the at least one layer of the stacked structure.

2. The chip packaging structure as described in claim 1, characterized in that, The redistribution layer includes a patterned circuit layer and a first protective layer for protecting the patterned circuit layer, wherein the impedance value of the patterned circuit layer is matched with the impedance value of the die coupled to the patterned circuit layer through the first conductive structure.

3. The chip packaging structure as described in claim 1 or 2, characterized in that, There are multiple first conductive structures, and at least one of the multiple first conductive structures is a plurality of solder balls stacked in a vertical direction.

4. The chip packaging structure as described in claim 1 or 2, characterized in that, There are multiple first conductive structures, and at least one of the multiple first conductive structures includes at least one arc wire.

5. The chip packaging structure as described in claim 1 or 2, characterized in that, The thickness of the first conductive structure in the vertical direction is greater than or equal to twice its diameter.

6. The chip packaging structure as described in claim 1 or 2, characterized in that, The upper surface of the first molding layer is flush with the exposed end of the first conductive structure.

7. The chip packaging structure as described in claim 1 or 2, characterized in that, The first molding layer has a through groove that exposes the end of the first conductive structure, and the redistribution layer has protrusions that correspond one-to-one with the through groove.

8. The chip packaging structure as described in claim 1 or 2, characterized in that, There are multiple bare wafers, and at least two of the bare wafers have different thicknesses along the vertical direction.

9. The chip packaging structure as described in claim 1 or 2, characterized in that, The die is coupled to the upper surface of the first connecting layer through a second connecting layer; or, the die is directly coupled to the upper surface of the first connecting layer.

10. The chip packaging structure as described in claim 1 or 2, characterized in that, Also includes: A connection terminal is disposed on the redistribution layer and is used for coupling with the circuit board.

11. The chip packaging structure as described in claim 1 or 2, characterized in that, Also includes: A chip is disposed on the redistribution layer, and the second molding compound covers the chip; The second protective layer is used to protect the third connecting layer.

12. The chip packaging structure as described in claim 11, characterized in that, At least one of the second conductive structures is a plurality of solder balls stacked in a vertical direction, or at least one wire arc, or a pin.

13. The chip packaging structure as described in claim 12, characterized in that, Also includes: A connection terminal is disposed on the third connection layer and is used for coupling with the circuit board.

14. The chip packaging structure as described in claim 1, characterized in that, The first connection layer has external pins; the chip package structure further includes: a third conductive structure disposed on the external pins; the first molding layer covers the third conductive structure, and at least a portion of the third conductive structure is exposed on the upper surface of the first molding layer; the redistribution layer is coupled to the third conductive structure.

15. The chip packaging structure as described in claim 14, characterized in that, At least one of the third conductive structures is a plurality of solder balls stacked in a vertical direction, or at least one wire arc, or a pin.

16. The chip packaging structure as described in claim 14 or 15, characterized in that, The upper surface of the first molding layer is flush with the exposed end of the third conductive structure.

17. The chip packaging structure as described in claim 14 or 15, characterized in that, The first molding layer has a through groove that exposes the end of the third conductive structure, and the redistribution layer has protrusions that correspond one-to-one with the through groove.

18. A method for fabricating a chip packaging structure, characterized in that, include: A first connecting layer having opposing upper and lower surfaces is provided; A bare die is coupled to the upper surface of the first interconnect layer; A first conductive structure is formed on the upper surface of the bare die; The bare die and the first conductive structure are encapsulated in a first encapsulation layer, such that the bare die and the first conductive structure are embedded within the first encapsulation layer. The end of the first conductive structure is exposed on the upper surface of the first molding layer; A redistribution layer is formed on the first molding layer; A second conductive structure is formed on the redistribution layer; The second conductive structure is encapsulated in a plastic layer, so that the second conductive structure is embedded in the second encapsulation layer. The end of the second conductive structure is exposed on the upper surface of the second molding layer; A third bonding layer and a second protective layer are formed on the second molding layer; The second conductive structure, the second molding layer, and the third connection layer constitute a stacked structure, and the chip packaging structure includes at least one layer of the stacked structure, wherein no chip is disposed in the at least one layer of the stacked structure.

19. The preparation method according to claim 18, characterized in that, The coupling of the bare die to the upper surface of the first interconnect layer includes: The bare wafer is bonded to the first connecting layer through the second connecting layer and then sintered. Alternatively, the bare die can be fixed to the first bonding layer using a eutectic bonding process.

20. The preparation method according to claim 18 or 19, characterized in that, The formation of the first conductive structure on the upper surface of the bare die includes: Multiple solder balls are formed on the upper surface of the die using a wire bonding process, stacked vertically.

21. The preparation method according to claim 18 or 19, characterized in that, The formation of the first conductive structure on the upper surface of the bare die includes: A wire bonding process is used to form a wire arc on the upper surface of the die, with one end of the wire arc coupled to the die, or both ends of the wire arc coupled to the die.

22. The preparation method according to claim 18 or 19, characterized in that, The step of exposing the end of the first conductive structure on the upper surface of the first molding layer includes: The end of the first conductive structure is exposed on the upper surface of the first molding layer by grinding. Alternatively, laser windowing can be used to expose the end of the first conductive structure on the upper surface of the first molding layer.

23. The preparation method according to claim 18 or 19, characterized in that, Also includes: The chip is fixed on the redistribution layer; Simultaneously, the chip and the second conductive structure are encapsulated, so that the chip and the second conductive structure are embedded in the second encapsulation layer.

24. The preparation method according to claim 23, characterized in that, The process of forming a second conductive structure on the redistribution layer includes: Multiple solder balls are formed on the redistribution layer using a wire bonding process, stacked vertically. Alternatively, a wire bonding process can be used to form a wire arc on the redistribution layer, with one end of the wire arc coupled to the redistribution layer, or both ends of the wire arc coupled to the redistribution layer. Alternatively, a welding method can be used to form pins on the redistribution layer.

25. The preparation method according to claim 18 or 19, characterized in that, The first connection layer has external pins, and while forming a first conductive structure on the upper surface of the bare die, it also includes forming a third conductive structure on the external pins; The process of encapsulating the bare die and the first conductive structure, such that the bare die and the first conductive structure are embedded in the first encapsulation layer, also includes: encapsulating the third conductive structure, such that the third conductive structure is embedded in the first encapsulation layer; In addition to exposing the end of the first conductive structure on the upper surface of the first molding layer, the method also includes exposing the end of the third conductive structure on the upper surface of the molding layer.

26. The preparation method according to claim 25, characterized in that, The formation of a third conduction structure on the external pin includes: Multiple solder balls are formed on the external pins using a wire bonding process, stacked vertically. Alternatively, a wire bonding process can be used to form a wire arc on the external pin, with one end of the wire arc coupled to the external pin, or both ends of the wire arc coupled to the external pin. Alternatively, a pin can be formed on the external pin by soldering.

27. An electronic device, characterized in that, include: The chip packaging structure as described in any one of claims 1-17 or the chip packaging structure prepared by the preparation method as described in any one of claims 18-26, and the circuit board electrically interconnected with the chip packaging structure.

28. The electronic device as claimed in claim 27, characterized in that, When the chip package structure includes connection terminals, the circuit board is disposed on the upper surface of the chip package structure and coupled to the connection terminals; The electronic device further includes a heat dissipation structure disposed on the lower surface of the first connection layer in the chip packaging structure.

29. The electronic device as claimed in claim 27, characterized in that, When the chip packaging structure includes a third conductive structure, the circuit board is disposed on the lower surface of the first connection layer in the chip packaging structure.

Images