Semiconductor device, method of manufacturing the same, and electronic device

Abstract

This invention discloses a semiconductor device, its manufacturing method, and an electronic device, relating to the field of semiconductor technology. It addresses the problem that etching the cap layer during bit line etching increases the space occupied by sidewalls formed around the bit lines, leading to poor dispersion and a tendency to form sidewall tail structures. The semiconductor device includes: a substrate having a cell region, a peripheral region, and a partition region between the cell region and the peripheral region; a cap layer covering the cell region and the partition region; a bit line contact structure located in the cell region, extending through the cap layer; a bit line located in the cell region, formed on the bit line contact structure; and a sidewall forming control layer formed between the bit line contact structure and the bit line. The manufacturing method of the semiconductor device is used to manufacture semiconductor devices. The semiconductor device provided by this invention is used in electronic devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, its manufacturing method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. DRAM has a simple structure; each bit of data requires only one capacitor and one transistor for processing. Furthermore, DRAM has high density and high capacity per unit volume, resulting in lower cost.

[0003] As semiconductor memory devices become highly integrated, during the fabrication of DRAM, the etching of the bit line material layer during bit line formation also involves etching the cap layer, which increases the space occupied by the sidewalls formed around the bit lines. This results in uneven distribution and poor dispersion of the sidewall space within the wafer and chip, and also makes it easier to form sidewall tail structures, which affect the performance of semiconductor devices during subsequent fabrication processes. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device, a method for manufacturing the same, and an electronic device, to avoid the problem of sidewalls formed around bit lines subsequently occupying more space, resulting in poorer distribution and the formation of sidewall tail structures.

[0005] To achieve the above objectives, the present invention provides a semiconductor device. The semiconductor device includes:

[0006] The substrate has a unit region, a peripheral region, and a partition region located between the unit region and the peripheral region;

[0007] The cap layer covers both the unit area and the partition area;

[0008] The bit line contact structure is located in the cell region and extends through the cap layer;

[0009] Bit lines located in the cell region are formed on bit line contact structures.

[0010] Additionally, a sidewall forming control layer is formed between the position line contact structure and the position line.

[0011] Compared with existing technologies, in the semiconductor device provided by this invention, the bit line contact structure penetrates the cap layer, forming a sidewall forming control layer between the bit line contact structure and the bit line. When a bit line material layer is formed on the surface of the sidewall forming control layer, etching of this material layer avoids directly etching the cap layer. Furthermore, it ensures that the width of the etched sidewall forming control layer and the bit line is controlled within a certain range, while preventing the formation of a funnel-shaped pattern below the bit line. This ensures that the space occupied by the sidewalls formed around the bit line matches the design, and that their distribution within the wafer and chip is more uniform and better, avoiding the formation of sidewall tail structures, thereby improving the performance of the semiconductor device.

[0012] The present invention also provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes:

[0013] A substrate is provided, the substrate having a cell region, a peripheral region, and a partition region located between the cell region and the peripheral region;

[0014] A cap layer, a bit line contact structure, and a sidewall forming control layer are sequentially formed on the substrate; the cap layer covers the unit area and the partition area; the bit line contact structure penetrates the cap layer;

[0015] A sidewall forming control layer is formed on the position line contact structure;

[0016] Additionally, bit lines are formed on the sidewall forming control layer, with the bit lines located in the unit region.

[0017] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention are the same as those of the semiconductor device described in the above technical solutions, and will not be repeated here.

[0018] The present invention also provides an electronic device, comprising the semiconductor device described above; and / or,

[0019] Electronic devices are communication devices or terminal devices.

[0020] Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the semiconductor device described in the above technical solution, and will not be repeated here. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0022] Figure 1 A layout diagram of a semiconductor device provided in an embodiment of the present invention is shown;

[0023] Figure 2 A cross-sectional view of a semiconductor device structure in the prior art is shown;

[0024] Figure 3 This illustrates a schematic diagram of a semiconductor device structure in another prior art.

[0025] Figure 4 A cross-sectional view of a semiconductor device provided in an embodiment of the present invention is shown;

[0026] Figure 5 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention is shown;

[0027] Figures 6 to 15 This illustrates the various stages along which the semiconductor device is manufactured in embodiments of the present invention. Figure 1 A schematic diagram of a cross-section embodiment of line A-A' in the diagram;

[0028] Figure 16 This illustrates the process of forming bit lines during the fabrication of a semiconductor device in an embodiment of the present invention. Figure 1 A schematic diagram of a cross-section embodiment of line A-A' in the diagram;

[0029] Figure 17 This illustrates the process of forming sidewalls during the fabrication of a semiconductor device in an embodiment of the present invention. Figure 1 A schematic diagram of a cross-section of line A-A' in the diagram.

[0030] Figure label:

[0031] Substrate 100, cap layer 102, bit line contact structure 104, sidewall forming control layer 106, bit line 108, cell region 110, peripheral region 112, partition region 114, contact hole 116, gate stack 118, gate dielectric layer 120, gate electrode 122, upper gate electrode 124, lower gate electrode 126, mask 128, barrier layer 132, upper gate electrode material layer 134, lower gate electrode material layer 136, bit line material layer 138, sidewall 140, memory node 141. Detailed Implementation

[0032] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0033] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0036] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] Dynamic Random Access Memory (DRAM) is a type of volatile memory that consists of memory regions composed of cells and a peripheral region surrounding the cells. Each cell contains a transistor electrically connected to a capacitor. The transistor controls the storage and release of charge in the capacitor to store data. Each cell can be located and its data access controlled using word lines (WL) and bit lines (BL) that connect the memory region to the cell regions.

[0038] Analysis of the aforementioned semiconductor device reveals that, during DRAM manufacturing, the semiconductor device includes a cell region 110, a peripheral region 112, and a partition region 114 located between the cell region 110 and the peripheral region 112 (in the prior art, the partition region 114 is generally included within the cell region 110. For ease of description later, the partition region 114 and the cell region 110 will be described separately below, such as...). Figure 1 (As shown). An insulating film (Spin-on Dielectrics, abbreviated as SOD) is covered in the partition area 114.

[0039] In the prior art, after the bit lines are formed, an etching process can be used to partially etch the bit line contact structures exposed by the bit lines. At this time, each bit line contact structure can have a small width, which can be substantially the same as the width of each bit line. In one embodiment, a bit line structure can be formed from a bit line and an insulating pattern. The bit line can include a first conductive pattern and a second conductive pattern. The first conductive pattern can include titanium nitride. The second conductive pattern can include tungsten. Sidewalls can be sidewalls covering the bit line structure and the bit line contact structures. The sidewalls can be formed by forming an insulating layer to ensure that the top surface of the cap layer, the sidewalls of the bit line contact structures, the sidewalls of the bit lines, and the sidewalls and top surface of the insulating pattern are covered. An etch-back process on the insulating layer can then be used to expose the top surface of the cap layer.

[0040] When the lower part of the bit line material layer is a silicon nitride cap layer or an oxide cap layer material, during plasma etching, due to the low etching selectivity between the bit line 108 and the cap layer 102, the cap layer 102 is easily etched when etching the bit line material layer. This results in the cap layer 102 below the bit line 108 having a funnel-shaped pattern after the bit line 108 is formed, which increases the space occupied by the sidewalls 140 subsequently formed around the bit line 108 (e.g., ...). Figure 2 and Figure 3As shown in the figure, the space occupied by the sidewall 140 is unevenly distributed within the chip, resulting in poor dispersion; at the same time, it is easy to form a sidewall tail structure, which may cause a short circuit when it comes into contact with the storage node 141.

[0041] To avoid the aforementioned problems, embodiments of the present invention provide a semiconductor device, a method for manufacturing the same, and an electronic device. A sidewall formation control layer is deposited on the surface of the bit line contact structure to control the morphology of the sidewalls. This ensures that the cap layer is not directly etched during the etching of the bit line material layer, guaranteeing that the space occupied by the sidewalls subsequently formed around the bit lines matches the design, resulting in uniform distribution within the wafer and chip, improved dispersion, and avoidance of sidewall tail structures, thereby improving the performance of the semiconductor device (e.g., ...). Figure 4 (As shown).

[0042] For ease of description, the following only describes the differences between the semiconductor devices provided in the embodiments of the present invention and those in the prior art. Other structures not described can be referred to the descriptions in the prior art. Of course, those skilled in the art can also improve other existing semiconductor devices based on the following descriptions of the embodiments of the present invention.

[0043] In response to the above problems, Figure 1 This diagram shows a layout of a semiconductor device provided in an embodiment of the present invention. Figures 5 to 17 It shows along Figure 1 The cross-sectional view taken by line A-A' in the diagram. (See diagram below.) Figure 17 As shown, the semiconductor device includes: a substrate 100, a cap layer 102, a bit line contact structure 104, a sidewall forming control layer 106, and a bit line 108.

[0044] like Figure 17 As shown, the substrate 100 has a unit region 110, a peripheral region 112, and a partition region 114 located between the unit region 110 and the peripheral region 112. The substrate 100 can be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate formed by epitaxial growth. The following description uses a silicon substrate as an example.

[0045] For example, a first transistor and a second transistor are formed on substrate 100. The first transistor is located in cell region 110, and the second transistor is located in peripheral region 112. In practical applications, there can be one or more first transistors. When there are multiple first transistors, they can be arranged in an array in cell region 110. When there are multiple second transistors, they are arranged around the first transistor in peripheral region 112.

[0046] The first transistor within the cell region can be any common type of transistor, such as a bottom-gate transistor or a top-gate transistor. It can also be a buried channel array transistor (BCAT), but is not limited to these. The second transistor in the peripheral region can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0047] like Figure 17 As shown, the cap layer 102 covers the cell region 110 and the partition region 114. A bit line contact structure 104 penetrates the cap layer 102 and is located in the cell region 110. The bit line contact structure 104 is electrically connected to the active region of the first transistor. A bit line 108 is formed on the bit line contact structure 104, and the bit line 108 is located in the cell region 110. In practical applications, the cap layer 102 has contact holes (…). Figure 17 (Not shown in the image), bit line 108 is electrically connected to the active region of the first transistor via bit line contact structure 104 subsequently formed in the contact hole and sidewall forming control layer 106 located above bit line contact structure 104. It should be understood that the number of bit line contact structure 104, bit line 108, and sidewall forming control layer 106 can be one or more, depending on the actual situation. One bit line 108 is connected to one first transistor.

[0048] like Figure 17 As shown, a sidewall forming control layer 106 is formed between the bit line contact structure 104 and the bit line 108. The sidewall forming control layer 106 is formed on the surface of the bit line contact structure 104. The sidewall forming control layer 106 is used to control the formation morphology of the sidewall 140.

[0049] In the prior art, a cap layer 102 is located below the bit line 108, and the material used for the cap layer 102 is typically silicon nitride or oxide. Because the etching selectivity of the materials contained in the bit line 108 and the cap layer 102 is relatively low, when etching the bit line material layer 138, the cap layer 102 is etched, resulting in a funnel-shaped pattern for the cap layer 102. This, in turn, increases the space occupied by the sidewalls 140 subsequently formed around the bit line 108 (e.g., ...). Figure 2 As shown, this makes the space occupied by the sidewall 140 unevenly distributed within the chip, resulting in poor dispersion; at the same time, it is also easy to form a sidewall tail structure, which may cause a short circuit when it comes into contact with the storage node 141 later.

[0050] Furthermore, since chlorine-based gas is used to etch the bit line material layer 138, a certain over-etching process must be employed to ensure complete etching of the bit line material layer 138. The chemical etching reaction between chlorine-based gas and the cap layer 102 is weak; physical etching plays a dominant role. During the over-etching process, the cap layer 102 will inevitably be etched into a slope shape. Simultaneously, ion sputtering during the etching process will further erode and narrow the formed bit lines 108, which will affect the performance of the subsequently formed semiconductor device.

[0051] In this embodiment of the invention, since the sidewall forming control layer 106 is located below the bit line 108, the material of the sidewall forming control layer 106 can be doped polysilicon. Doped polysilicon has similar metallic properties to the bit line material layer 138, meaning it exhibits a strong chemical reaction with the chlorine-based gas used to etch the bit line material layer 138, and physical etching no longer plays a dominant role. During the over-etching stage of the bit line material layer 138, the sidewall forming control layer 106 will still form a vertical morphology, and due to the weakened physical sputtering etching effect, the width of the bit line 108 will not decrease. To ensure that the cap layer 102 is not damaged during the etching of the sidewall forming control layer 106 after the bit line material layer 138 has been over-etched, a bromine-based gas can be used to finally complete the etching of the sidewall forming control layer 106. Since this gas has weak physical etching properties, it can prevent the cap layer 102 from being etched into a slope shape. The sidewall forming control layer 106, with its vertical morphology, is used as a hard mask. A fluorine-based gas is then used to etch the cap layer 102, ensuring that the cap layer 102 forms a vertical structure with the same width as the bit line 108 and the sidewall forming control layer 106, thus avoiding a sloping funnel-shaped pattern. During subsequent etching of the sidewall 140, a more controllable sidewall morphology is obtained, with its space dimensions matching the design. No sidewall tailing structures caused by the funnel-shaped pattern appear, ensuring the stability of semiconductor device characteristics (e.g., ...). Figure 4 (As shown).

[0052] In practical applications, such as Figure 15 As shown, a stacked upper gate electrode material layer 134 and bit line material layer 138 are formed on the surface of the cap layer 102, and the etching selectivity ratio of bit line 108 to upper gate electrode material layer 134 is defined to be greater than the etching selectivity ratio of bit line 108 to cap layer 102.

[0053] Based on this, the etched bit line material layer 138 forms bit lines ( Figure 15 During the process (not shown in the image), the upper gate electrode material layer 134 will be etched into a sidewall forming control layer (…). Figure 15(Not shown in the image), due to the buffering effect of the sidewall forming control layer during the over-etching process, the cap layer 102 is prevented from being etched into a slope shape. Therefore, in this embodiment of the invention, the etch selectivity ratio between the bit line and the sidewall forming control layer can be controlled to prevent the cap layer 102 from being etched into a slope shape during the over-etching process of the bit line material layer 138. Simultaneously, this embodiment of the invention can also control the width of the sidewall forming control layer and the bit line within a certain range by controlling the etching process conditions, so that the space occupied by the sidewalls subsequently formed around the bit lines is smaller, and the sidewalls formed in the prior art are thinner, resulting in higher integration and better distribution of the sidewalls, thereby improving the performance of the semiconductor device. In this case, the cap layer formed by the semiconductor device provided in this embodiment of the invention will not form a slope shape as described above. Figure 2 The funnel-shaped pattern shown.

[0054] It should be noted that, as Figure 17 As shown, the sidewall forming control layer 106 is a doped polysilicon sidewall forming control layer. The thickness of the sidewall forming control layer 106 is 10 nm to 100 nm. It should be understood that the sidewall forming control layer 106 can be made of other materials, its core function being to serve as an etching buffer layer for the bit line material layer during over-etching. A material with similar metallic properties to the bit line 108 can be used as the sidewall forming control layer 106, meaning that a vertical structure can be formed during the over-etching process of the bit line material layer. The sidewall forming control layer 106 can be other conductive materials, including but not limited to doped polysilicon. The thickness of the sidewall forming control layer 106 can be set according to actual conditions. Furthermore, the sidewall forming control layer 106 can be a single-layer sidewall forming control layer or a multi-layer sidewall forming control layer. In the embodiment provided by this invention, the sidewall forming control layer 106 is a single-layer doped polysilicon sidewall forming control layer. It should be understood that the number of layers in the sidewall forming control layer 106 can be set according to actual conditions.

[0055] As one possible implementation, such as Figure 17 As shown, when the bit line material layer is etched ( Figure 17 (not shown in the image) and the upper gate electrode material layer ( Figure 17 After forming the bit line 108 and the sidewall forming control layer 106 (not shown in the diagram), the difference between the width of the sidewall forming control layer 106 and the width of the bit line 108 is within a preset difference range. At this time, it can be considered that the width of the sidewall forming control layer 106 and the width of the bit line 108 are approximately the same. In this embodiment, the preset range is ±4 angstroms. It should be understood that the preset difference value can be set according to actual conditions. At this time, when etching the sidewall forming control layer 106, the etching effect on the bit line 108 is small, ensuring that the shape of the bit line 108 meets the requirements.

[0056] As one possible implementation, such as Figure 17As shown, the semiconductor device provided in this embodiment of the invention further includes a gate stack 118 disposed in the peripheral region 112. The gate stack 118 includes a gate dielectric layer 120 and a gate electrode 122. The gate dielectric layer 120 is formed on the substrate 100. The gate electrode 122 includes an upper gate electrode 124 and a lower gate electrode 126. The lower gate electrode 126 may be formed on the gate dielectric layer 120, and the upper gate electrode 124 is stacked on the lower gate electrode 126. It should be understood that while the lower gate electrode 126 is formed on the gate dielectric layer 120, the lower gate electrode 126 and the upper gate electrode 124 are located in the peripheral region 112. Of course, the size of the peripheral region 112 covered by the lower gate electrode 126 and the upper gate electrode 124 is set according to actual conditions, and will not be elaborated here.

[0057] Both the upper gate electrode 124 and the lower gate electrode 126 can be made of conductive materials. These conductive materials can be doped polysilicon. For example, the upper gate electrode 124 can be a doped polysilicon upper gate electrode, and the lower gate electrode 126 can also be a doped polysilicon lower gate electrode; the materials of the upper gate electrode 124 and the lower gate electrode 126 can be the same. In the prior art, the lower gate electrode 126 formed in the peripheral region 112 is made only of doped polysilicon. In this case, the conductivity of the lower gate electrode 126 is better than that formed using both metal and doped polysilicon materials, resulting in more stable performance of the semiconductor device formed later. In this embodiment of the invention, by depositing doped polysilicon material in the unit region 110 and the peripheral region 112 respectively to form the upper gate electrode 124 and the lower gate electrode 126, the conductivity of the lower gate electrode 126 in the peripheral region 112 can be guaranteed to be the same as that of the lower gate electrode 126 in the prior art. Of course, both the upper gate electrode 124 and the lower gate electrode 126 can be made of metal, but this is not a limitation. The thickness of the upper gate electrode 124 can be 10 nm to 100 nm, and the thickness of the lower gate electrode 126 can also be 10 nm to 100 nm. This facilitates adjustment of the thickness of the upper gate electrode 124 and the lower gate electrode 126 formed in the peripheral region 112, and also helps to adjust the height of the bit line 108 formed in the cell region 110, and to ensure that the shape of the bit line 108 is vertical. It should be understood that the thickness of the upper gate electrode 124 and the lower gate electrode 126 can be set according to actual conditions.

[0058] At this time, the sidewall forming control layer 106 and the upper gate electrode 124 are made of the same material, which saves manufacturing steps in the semiconductor device manufacturing process. The sidewall forming control layer 106 and the upper gate electrode 124 can be formed by depositing material once.

[0059] As one possible implementation, such as Figure 17As shown, the cap layer 102 is a silicon nitride cap layer, and a mask 128 is formed between the substrate 100 and the cap layer 102. The mask 128 can be an oxide mask. The cap layer 102 also covers the peripheral region 112. Since the size of the peripheral region 112 covered by the cap layer 102 is set according to the actual situation, part of the substrate 100 in the peripheral region 112 is exposed, which facilitates subsequent deposition, photolithography, and etching processes in the peripheral region 112. Of course, the material of the mask 128 can also be selected according to the actual situation, such as silicon nitride, silicon carbide, etc., but is not limited to these. The cap layer 102 is a silicon nitride cap layer, but the material of the cap layer 102 can also be selected according to the actual situation, such as a cap layer made of silicon carbide, oxide, etc.

[0060] The number of cap layers 102 and masks 128 can be one or more, depending on the actual situation. When there are multiple masks 128, the masks 128 are formed on the substrate 100 and cover the unit region 110, the partition region 114, and the peripheral region 112. In this case, the size of the peripheral region 112 covered by the mask 128 can be set according to the actual situation. When there are multiple cap layers 102, the cap layers 102 are formed on the multiple masks 128.

[0061] As one possible implementation, such as Figure 17 As shown, the cap layer 102 covers the unit area 110, the partition area 114, and the peripheral area 112. The gate stack 118 covers the remaining portion of the peripheral area 112.

[0062] The gate stack 118 can be formed close to the cap layer 102. Of course, the size of the area occupied by the gate stack 118 and the cap layer 102 in the outer region 112 can be set according to the actual situation.

[0063] This invention also provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes:

[0064] like Figure 17 As shown, firstly, a substrate 100 is provided. The substrate 100 has a cell region 110, a peripheral region 112, and a partition region 114 located between the cell region 110 and the peripheral region 112. The selection of the substrate 100 can be referred to the previous text and will not be repeated here.

[0065] like Figure 17 As shown, a cap layer 102, a bit line contact structure 104, and a sidewall forming control layer 106 are then sequentially formed on the substrate 100. The cap layer 102 covers the unit region 110 and the partition region 114. The bit line contact structure 104 penetrates the cap layer 102.

[0066] like Figure 17As shown, a sidewall forming control layer 106 is then formed on the bit line contact structure 104. A bit line 108 is formed on the sidewall forming control layer 106, the bit line 108 being located in the cell region 110.

[0067] In the upper gate electrode material layer ( Figure 17 A bit line material layer is formed on (not shown in the image). Figure 17 (Not shown in the image), the bit line material layer is etched to form bit lines 108, and the upper gate electrode material layer is etched to form a sidewall forming control layer 106. Through contact holes ( Figure 17 The bit line contact structure 104 (not shown in the figure) forms a bit line contact structure that electrically connects the bit line 108 to the active region of the first transistor located in the substrate 100.

[0068] Compared with the prior art, the semiconductor device manufacturing method provided in the embodiments of the present invention has the same beneficial effects as the semiconductor device provided in the above embodiments, and will not be repeated here.

[0069] like Figure 17 As shown, the difference between the width of the sidewall forming control layer 106 and the width of the bit line 108 is within a preset range. In this case, the width of the sidewall forming control layer 106 and the width of the bit line 108 can be considered to be approximately the same. In the embodiment provided by this invention, the preset range is ±4 angstroms. It should be understood that the preset range can be set according to actual conditions. The sidewall forming control layer 106 can be a doped polysilicon sidewall forming control layer, and the thickness of the sidewall forming control layer 106 can be 10 nm to 100 nm. It should be understood that the sidewall forming control layer 106 can be made of other materials, and its core function is to serve as an etching buffer layer for the bit line material layer during over-etching. A material with similar metallic properties to the bit line 108 can be used as the sidewall forming control layer 106, that is, a vertical structure can be formed during the over-etching process of the bit line material layer. The sidewall forming control layer 106 can be other conductive materials, including but not limited to doped polysilicon. The thickness of the sidewall forming control layer 106 can be set according to actual conditions.

[0070] As one possible implementation, such as Figure 17 As shown, forming a cap layer 102, a bit line contact structure 104, and a sidewall forming control layer 106 on a substrate 100 includes:

[0071] like Figure 6 As shown, a cap layer 102 is formed on the substrate 100. The cap layer 102 covers the cell region 110 and the partition region 114.

[0072] like Figure 6As shown, before forming the cap layer 102 on the substrate 100, a mask 128 is formed on the substrate 100, wherein the mask 128 can be an oxide mask. That is, the cap layer 102 is formed on the oxide mask, and the cap layer 102 can be a silicon nitride cap layer. The aforementioned oxide mask and silicon nitride cap layer are located in the cell region 110 and the partition region 114. It is understood that the materials of the mask 128 and the cap layer 102 can be other practically suitable materials.

[0073] like Figure 7 As shown, through contact holes 116 are formed in the cap layer 102 and the mask 128.

[0074] like Figure 7 As shown, the oxide mask and silicon nitride cap layer are etched to form a contact hole 116 that penetrates the oxide mask and silicon nitride cap layer, and the contact hole 116 is located in the cell region 110.

[0075] like Figure 8 As shown, bit line contact structures 104 are formed on the cap layer 102 and the mask 128.

[0076] like Figure 8 As shown, at this time, the bit line contact structure 104 is formed in the contact hole ( Figure 8 (Not shown in the image). The bit line contact structure 104 is formed by the following process: forming contact holes in an oxide mask and a silicon nitride cap layer, and filling the contact holes with doped polysilicon. The bit line contact structure 104 formed at this time is located in the cap layer 102, that is, the top surface of the bit line contact structure 104 is lower than the top surface of the silicon nitride cap layer.

[0077] As one possible implementation, such as Figure 12 As shown, before forming the lower gate electrode material layer 136 on the cap layer 102 and the gate dielectric layer 120, the semiconductor device manufacturing method further includes:

[0078] like Figures 9 to 11 As shown, a barrier layer 132 is formed on the cap layer 102. The barrier layer 132 covers the unit region 110, the peripheral region 112, and the partition region 114. It should be understood that the size of the peripheral region 112 covered by the barrier layer 132 can be set according to the actual situation, and will not be described in detail here.

[0079] A barrier layer is formed by depositing silicon nitride on the silicon nitride cap layer, where the barrier layer is a silicon nitride cap layer with a bit-line contact structure. Silicon nitride material is then deposited on the silicon nitride cap layer to form the bit-line contact structure. The bit-line contact structure silicon nitride cap layer can be formed using any of various deposition techniques. For example, it can be formed using low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and other suitable deposition techniques.

[0080] For example, a silicon nitride cap layer with a bit-line contact structure can be formed using chemical vapor deposition. It is understood that other practically suitable methods can also be used to form it.

[0081] like Figure 10 As shown, the mask 128, cap layer 102, and barrier layer 132 located in the outer region 112 are patterned to expose the active area of ​​the outer region 112. Figure 10 (Not shown in the image).

[0082] like Figure 10 As shown, a portion of the oxide mask, silicon nitride cap layer, and silicon nitride cap layer of the bit line contact structure are selectively removed. For example, plasma etching or wet etching is used to selectively remove a portion of the oxide mask, silicon nitride cap layer, and silicon nitride cap layer of the bit line contact structure to expose the peripheral region 112, facilitating subsequent deposition, photolithography, and etching processes in the peripheral region 112. It is understood that other practically suitable methods can also be used to remove a portion of the oxide mask, silicon nitride cap layer, and silicon nitride cap layer of the bit line contact structure.

[0083] As one possible implementation, such as Figure 11 As shown, after forming the bit line contact structure 104 on the cap layer 102, a lower gate electrode located in the peripheral region 112 is formed on the substrate 100. Figure 11 Before (not shown), a gate dielectric layer 120 located in the peripheral region 112 is formed on the substrate 100.

[0084] like Figure 11As shown, after exposing the active region of the peripheral region 112, an oxide layer 120 is deposited on the active region to form a gate dielectric layer 120. That is, the gate dielectric layer 120 located in the peripheral region 112 is formed on the substrate 100. The method of oxide deposition can be referred to above and will not be repeated here. In the embodiment of the present invention, the oxide layer 120 is formed by atomic layer deposition.

[0085] It should be noted that the above-mentioned gate dielectric layer can be formed in various ways. How the gate dielectric layer is formed is not a key feature of the embodiments of this invention; therefore, it is only briefly described in this specification to enable those skilled in the art to easily implement the embodiments provided by this invention. Those skilled in the art can certainly conceive of other methods for manufacturing the gate dielectric layer.

[0086] As one possible implementation, such as Figure 12 and Figure 13 As shown, forming a lower gate electrode 126 located in the peripheral region 112 on the substrate 100 includes forming a lower gate electrode material layer 136 on the cap layer 102 and the gate dielectric layer 120.

[0087] like Figure 12 As shown, since a barrier layer 132 is formed on the cap layer 102, doped polysilicon is deposited on the barrier layer 132 and the gate dielectric layer 120 as the lower gate electrode material layer 136, and the thickness of the lower gate electrode material layer 136 is 10 nm to 100 nm. At this time, the lower gate electrode material layer 136 is located in the unit region 110 and the peripheral region 112. Of course, the material contained in the lower gate electrode material layer 136 can also be other suitable conductive materials. The thickness of the lower gate electrode material layer 136 can be set according to the actual situation. The method of depositing doped polysilicon can be referred to the previous text and will not be repeated here.

[0088] like Figure 12 and Figure 13 As shown, the lower gate electrode material layer 136 is etched to obtain the lower gate electrode 126 located on the gate dielectric layer 120. The lower gate electrode 126 is located in the peripheral region 112.

[0089] like Figure 12 and Figure 13As shown, the lower gate electrode material layer 136 is etched, removing the barrier layer 132 formed below the lower gate electrode material layer 136 and above the cap layer 102. For example, the lower gate electrode material layer 136 is etched using either dry etching or wet etching. For instance, plasma etching can be used when dry etching is employed. The barrier layer 132 is removed using sputter etching; however, it is understood that other practically suitable methods can also be used to etch the lower gate electrode material layer 136 and the barrier layer 132. This exposes the cell region 110, obtaining the lower gate electrode 126, which is located in the peripheral region 112. The size of the lower gate electrode 126 covering the peripheral region 112 is determined according to actual conditions and will not be elaborated here. The thickness of the lower gate electrode 126 is 10 nm to 100 nm. It should be understood that the thickness of the lower gate electrode 126 can be set according to actual conditions.

[0090] As one possible implementation, such as Figures 14 to 16 As shown, obtaining the upper gate electrode includes:

[0091] like Figures 14 to 16 As shown, an upper gate electrode material layer 134 is formed on the cap layer 102 and the lower gate electrode 126. The upper gate electrode material layer 134 is etched to obtain the sidewall forming control layer 106 and the upper gate electrode 124. The upper gate electrode 124 covers the lower gate electrode 126. The upper gate electrode 124 is located in the peripheral region 112. At this time, the sidewall forming control layer 106 and the upper gate electrode 124 are made of the same material, which saves manufacturing steps in the semiconductor device manufacturing process. The sidewall forming control layer 106 and the upper gate electrode 124 can be formed by depositing material once.

[0092] Doped polysilicon is deposited on the cap layer 102 and the lower gate electrode 126 as the upper gate electrode material layer 134, and the thickness of the upper gate electrode material layer 134 is 10 nm to 100 nm. At this time, the upper gate electrode material layer 134 is located in the cell region 110 and the peripheral region 112. It should be understood that the material contained in the upper gate electrode material layer 134 can also be other suitable conductive materials. The method of depositing doped polysilicon can be referred to the previous text and will not be repeated here. After processing the upper gate electrode material layer 134, a sidewall forming control layer 106 covering the bit line contact structure 104 and an upper gate electrode 124 covering the lower gate electrode 126 are obtained. The thickness of the upper gate electrode 124 is 10 nm to 100 nm. It should be understood that the thickness of the upper gate electrode 124 can be set according to actual conditions.

[0093] As one possible implementation, word lines are formed in the substrate, and these word lines are electrically connected to the gate electrode of a first transistor located in the substrate. Contact holes are formed in the cap layer and the mask, allowing the bit lines formed on the cap layer to be electrically connected to the active region of the first transistor located in the substrate through the bit line contact structure formed by the contact holes and the sidewall forming control layer.

[0094] like Figure 17 As shown, after forming the bit line 108, an etching process can be used to partially etch the bit line contact structures 104 exposed by the bit line 108 and the sidewall forming control layer 106. At this time, each bit line contact structure 104 can have a small width, which can be substantially the same as the width of each bit line 108 and the sidewall forming control layer 106. In one embodiment, a bit line structure ( Figure 17 (Not shown in the image) can consist of a bit line and an insulating pattern ( Figure 17 (Not shown in the image) is formed. The bit line may include a first conductive pattern and a second conductive pattern. The first conductive pattern may include titanium nitride. The second conductive pattern may include tungsten. Figure 17 As shown, the sidewall 140 can be a sidewall covering the bit line 108, the sidewall forming control layer 106, and the bit line contact structure 104. The sidewall 140 can be formed by forming an insulating layer to ensure the top surface of the cap layer 102, the sidewalls of the bit line contact structure 104, the sidewalls of the bit line 108, and the sidewall forming control layer 106 are covered. An etch-back process on the insulating layer can then be used to expose the top surface of the cap layer 102.

[0095] This invention also provides an electronic device. The electronic device includes... Figure 5 The semiconductor device shown. The above electronic device can be a communication device or a terminal device.

[0096] As one possible implementation, the electronic device provided in this embodiment of the invention may include, for example, communication devices such as base stations and terminal devices such as mobile phones, tablets, and wearable devices, but is not limited thereto. Further, the electronic device includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks. It may also include computers, mobile phones, base stations, servers, etc., but is not limited thereto.

[0097] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0098] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: The substrate has a unit region, a peripheral region, and a partition region located between the unit region and the peripheral region; A cap layer that covers the unit area and the partition area; A bit line contact structure located in the unit region, the bit line contact structure penetrating the cap layer; The bit line is located in the unit region and is formed on the bit line contact structure; And, a sidewall forming control layer formed between the bit line contact structure and the bit line; The semiconductor device further includes a gate stack disposed in the peripheral region; the gate stack includes a gate dielectric layer and a gate electrode, the gate dielectric layer being formed on the substrate; the gate electrode includes an upper gate electrode and a lower gate electrode; the lower gate electrode is formed on the gate dielectric layer; the upper gate electrode is stacked and formed on the lower gate electrode; the sidewall forming control layer and the upper gate electrode are made of the same material; the materials contained in the sidewall forming control layer, the upper gate electrode, and the lower gate electrode are all conductive materials; The conductive material is doped polycrystalline silicon; The etching selectivity ratio between the bit line and the sidewall forming control layer is greater than the etching selectivity ratio between the bit line and the cap layer; the material used to make the bit line has similar metallic properties to the material used to make the sidewall forming control layer.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the sidewall forming control layer, the upper gate electrode, and the lower gate electrode are all 10nm~100nm.

3. The semiconductor device according to claim 1 or 2, characterized in that, The sidewall forming control layer is a single-layer sidewall forming control layer; or... The sidewall forming control layer is a multi-layer sidewall forming control layer.

4. The semiconductor device according to claim 1, characterized in that, The cap layer is a silicon nitride cap layer, and the cap layer also covers the peripheral area; A mask is formed between the substrate and the cap layer, and the mask is an oxide mask.

5. A method for manufacturing a semiconductor device, characterized in that, The method for manufacturing the semiconductor device is used to produce the semiconductor device according to any one of claims 1 to 4; The method for manufacturing the semiconductor device includes: A substrate is provided, the substrate having a cell region, a peripheral region, and a partition region located between the cell region and the peripheral region; A cap layer, a bit line contact structure, and a sidewall forming control layer are sequentially formed on the substrate; the cap layer covers the unit region and the partition region, and the bit line contact structure penetrates the cap layer. A sidewall forming control layer is formed on the bit line contact structure; Additionally, bit lines are formed on the sidewall forming control layer, the bit lines being located in the cell region.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The formation of the cap layer, bit line contact structure, and sidewall forming control layer on the substrate includes: A cap layer is formed on the substrate; The bit line contact structure is formed on the cap layer; A lower gate electrode located in the peripheral region is formed on the substrate; An upper gate electrode material layer is formed on the cap layer and the lower gate electrode; The upper gate electrode material layer is etched to obtain a sidewall forming control layer and an upper gate electrode located in the peripheral region, the upper gate electrode covering the lower gate electrode.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The step of forming a lower gate electrode in the peripheral region on the substrate includes: A lower gate electrode material layer is formed on the cap layer and the gate dielectric layer; The lower gate electrode material layer is etched to obtain the lower gate electrode located on the gate dielectric layer; The thickness of both the upper gate electrode material layer and the lower gate electrode material layer is 10nm~100nm.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The etching method used in the etching process of the lower gate electrode material layer includes dry etching; or, Wet etching; The dry etching method includes plasma etching.

9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, Also includes: Before forming a lower gate electrode material layer on the cap layer and the gate dielectric layer, the method for manufacturing the semiconductor device further includes: forming a barrier layer on the cap layer; The barrier layer covers the unit area, the peripheral area, and the partition area.

10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 4.

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