Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has an air gap and a boron nitride cap to reduce a capacitive coupling in a pattern dense region. The semiconductor element includes a first conductive feature and a second conductive feature disposed on a pattern dense region of a semiconductor substrate. The semiconductor element also includes a third conductive feature and a fourth conductive feature disposed on a pattern sparse region of the semiconductor substrate. The semiconductor element further includes a boron nitride layer disposed on the pattern dense region and the pattern sparse region of the semiconductor substrate. A first portion of the boron nitride layer between the first conductive feature and the second conductive feature is disposed apart from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer between the third conductive feature and the fourth conductive feature directly contacts the semiconductor substrate.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 16 / 937,347, filed July 23, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of fabricating the same. In particular, the present disclosure relates to a semiconductor device and a method of fabricating the same, the semiconductor device having an air gap and a boron nitride cap to reduce the capacitive coupling in a pattern dense region. BACKGROUND

[0003] Semiconductor devices are indispensable for many modern applications. As electronic technology advances, the size of semiconductor devices becomes smaller, while providing better functionality and including larger numbers of integrated circuits. Due to the small size of semiconductor devices, different types and sizes of semiconductor devices that implement different functions are integrated and packaged in a single module. Furthermore, many manufacturing steps are performed on the integration of various types of semiconductor devices.

[0004] However, the manufacturing and integration of semiconductor devices include many complex steps and operations. The integration in semiconductor devices is becoming more complex. The increase in complexity of the manufacturing and integration of semiconductor devices can cause a number of defects, such as parasitic capacitance between adjacent conductive elements, which results in increased power consumption and unwanted resistive-capacitive (RC) delay (e.g., signal delay), especially in a pattern dense region. Accordingly, there is a continuing need to improve the manufacturing process of semiconductor devices in order to deal with the defects.

[0005] The above description of the background art is provided merely for purposes of background information and does not constitute an admission, by express or implied reference, that the background art is prior art to the present disclosure, that any art referenced constitutes part of the prior art, or that the background art is consi dered relevant to the present disclosure in determining priority. Any discussion of the background art is intended only to enhance understanding of the present disclosure and should be considered in that light. SUMMARY

[0006] An embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a first conductive feature and a second conductive feature disposed on a pattern dense region of a semiconductor substrate. The semiconductor element also includes a third conductive feature and a fourth conductive feature disposed on a pattern sparse region of the semiconductor substrate. The semiconductor element further includes a boron nitride layer disposed on the pattern dense region and the pattern sparse region of the semiconductor substrate, wherein a first portion of the boron nitride layer between the first conductive feature and the second conductive feature is disposed apart from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer between the third conductive feature and the fourth conductive feature directly contacts the semiconductor substrate.

[0007] In an embodiment, the first conductive feature is separated from the second conductive feature by a first distance, the third conductive feature is separated from the fourth conductive feature by a second distance, and the second distance is greater than the first distance. In an embodiment, the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature are covered by the boron nitride layer, and an upper surface of the first conductive feature is higher than a lower surface of the first portion of the boron nitride layer. In an embodiment, the semiconductor element further includes a first gap sub disposed on a sidewall of the first conductive feature, and a second gap sub disposed on a sidewall of the second conductive feature, wherein the air gap is surrounded by the first gap sub, the second gap sub, the first portion of the boron nitride layer, and the semiconductor substrate. In an embodiment, the semiconductor element further includes a third gap sub disposed on a sidewall of the third conductive feature, wherein the third gap sub is surrounded by the third conductive feature, the boron nitride layer, and the semiconductor substrate, and a fourth gap sub disposed on a sidewall of the fourth conductive feature, wherein the fourth gap sub is surrounded by the fourth conductive feature, the boron nitride layer, and the semiconductor substrate. In an embodiment, the semiconductor element further includes an energy removable layer disposed between the first conductive feature and the second conductive feature, wherein a portion of the energy removable layer is between the air gap and the semiconductor substrate. In an embodiment, the pattern dense region is in a memory cell of a memory element, and the pattern sparse region is in a surrounding region outside the memory cell of the memory element.

[0008] Another embodiment of the present disclosure provides a semiconductor element. The semiconductor element includes a first conductive feature and a second conductive feature disposed on a pattern dense region of a semiconductor substrate. The semiconductor element also includes a third conductive feature and a fourth conductive feature disposed on a pattern sparse region of the semiconductor substrate, wherein a distance between the first conductive feature and the second conductive feature is less than a distance between the third conductive feature and the fourth conductive feature. The semiconductor element further includes a boron nitride layer covering the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature. The boron nitride layer includes a first portion between the first conductive feature and the second conductive feature and a second portion between the third conductive feature and the fourth conductive feature, and a height of the second portion is greater than a height of the first portion.

[0009] In an embodiment, the height of the second portion is substantially the same as a height of the third conductive feature. In an embodiment, a width of the second portion of the boron nitride layer is greater than a width of the first portion of the boron nitride layer. In an embodiment, the semiconductor element further includes a first gap sub disposed on a sidewall of the first conductive feature, a second gap sub disposed on a sidewall of the second conductive feature, a third gap sub disposed on a sidewall of the third conductive feature, and a fourth gap sub disposed on a sidewall of the fourth conductive feature, wherein the air gap is between the first gap sub and the second gap sub. In an embodiment, a contact area between the second portion of the boron nitride layer and the third gap sub is greater than a contact area between the first portion of the boron nitride layer and the first gap sub. In an embodiment, the semiconductor element further includes an energy removable structure disposed between the first gap sub and the second gap sub and covered by the first portion of the boron nitride layer, wherein the energy removable structure surrounds the air gap and the air gap is between the first conductive feature and the second conductive feature.

[0010] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first conductive feature, a second conductive feature, a third conductive feature, and a fourth conductive feature on a semiconductor substrate, wherein the first conductive feature and the second conductive feature are formed on a pattern dense region of the semiconductor substrate, and the third conductive feature and the fourth conductive feature are formed on a pattern sparse region of the semiconductor substrate; and depositing a boron nitride layer on the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature; wherein a first portion of the boron nitride layer extends between the first conductive feature and the second conductive feature such that the first portion of the boron nitride layer is disposed apart from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer extends between the third conductive feature and the fourth conductive feature such that the second portion of the boron nitride layer directly contacts the semiconductor substrate.

[0011] In one embodiment, a lowermost width of the second portion of the boron nitride layer is greater than a lowermost width of the first portion of the boron nitride layer. In one embodiment, the method of fabricating a semiconductor device further includes, prior to depositing the boron nitride layer, forming a first gap on a sidewall of the first conductive feature, forming a second gap on a sidewall of the second conductive feature, forming a third gap on a sidewall of the third conductive feature, and forming a fourth gap on a sidewall of the fourth conductive feature. In one embodiment, the method of fabricating a semiconductor device further includes, prior to depositing the boron nitride layer, performing a deposition process to selectively form an energy removable layer between the first gap and the second gap in the pattern dense region without depositing the energy removable layer between the third gap and the fourth gap in the pattern sparse region. In one embodiment, the boron nitride layer is formed to cover the energy removable layer, and the method further includes performing a thermal process to remove the energy removable layer such that the air gap is enclosed by the first gap, the second gap, the first portion of the boron nitride layer, and the semiconductor substrate. In one embodiment, the boron nitride layer is formed to cover the energy removable layer, and the method further includes performing a thermal process to transform the energy removable layer into an energy removable structure, wherein the air gap is enclosed by the energy removable structure, and the energy removable structure is denser than the energy removable layer. In one embodiment, forming the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature includes forming a doped oxide layer on the semiconductor substrate; etching the doped oxide layer to form openings to expose the semiconductor substrate; forming the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature in the openings; and removing the doped oxide layer, which is performed prior to depositing the boron nitride layer.

[0012] In the present disclosure, a plurality of embodiments of a semiconductor device is provided. The semiconductor device has a plurality of conductive features and a boron nitride layer on a pattern dense region and a pattern sparse region of a semiconductor substrate. The boron nitride layer has a first portion and a second portion, the first portion is disposed between the conductive features in the pattern dense region, and the second portion is disposed between the conductive features in the pattern sparse region. The first portion of the boron nitride layer is disposed apart from the semiconductor substrate by an air gap, and the second portion of the boron nitride layer directly contacts the semiconductor substrate. Thus, parasitic capacitance between the conductive features in the pattern dense region can be reduced. Thus, overall device performance can be improved.

[0013] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described below. The present disclosure is directed to all such technical features and advantages of the present disclosure. It should be appreciated that the concepts and specific embodiments disclosed can be readily utilized as base structures or procedures for modifying or designing other structures or procedures for carrying out the same purposes of the present disclosure. Those skilled in the art who have the present disclosure before them will appreciate that other equally effective build structures and procedures can be substituted for the concepts disclosed without departing from the spirit and scope of the present disclosure as set forth in the claims. BRIEF DESCRIPTION OF DRAWINGS

[0014] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which like reference numerals refer to like elements throughout the figures.

[0015] Figure 1 A top view schematic diagram of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 2 A cross-sectional view schematic diagram of the semiconductor device along line I-I’ of Figure 1 according to some embodiments of the present disclosure.

[0017] Figure 3 A flowchart schematic diagram of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 4 A flowchart schematic diagram of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 5 A top view schematic diagram of an intermediate stage of forming a plurality of conductive features during fabrication of the semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 6 A cross-sectional view schematic diagram of an intermediate stage of forming a plurality of conductive features along line I-I’ ofFigure 5 A cross-sectional view of line segment I-I'.

[0021] Figure 7 This is a top view schematic diagram of an intermediate stage in the formation of a plurality of spacers during the formation of the semiconductor element according to some embodiments of the present disclosure.

[0022] Figure 8 According to some embodiments of this disclosure, during the formation of the semiconductor device, an intermediate stage is performed along which multiple spacers are formed. Figure 7 A cross-sectional view of line segment I-I'.

[0023] Figure 9 This is a top view schematic diagram of an intermediate stage in the formation of a doped oxide layer during the formation of the semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 10 This is a cross-sectional schematic diagram of an intermediate stage in the formation of a patterned mask during the formation of the semiconductor device, according to some embodiments of the present disclosure.

[0025] Figure 11 This is a cross-sectional schematic diagram showing an intermediate stage in the formation of the semiconductor device during the formation of the doped oxide layer, according to some embodiments of the present disclosure.

[0026] Figure 12 This is a cross-sectional schematic diagram showing an intermediate stage in the formation of a plurality of conductive features in the doped oxide layer during the formation of the semiconductor device according to some embodiments of the present disclosure.

[0027] Figure 13 This is a cross-sectional schematic diagram of an intermediate stage during the formation of the semiconductor device, according to some embodiments of the present disclosure, of removing the doped oxide layer.

[0028] Figure 14 This is a cross-sectional schematic diagram of an intermediate stage in the formation of a plurality of spacers during the formation of the semiconductor device according to some embodiments of the present disclosure.

[0029] Figure 15 This is a cross-sectional schematic diagram of an intermediate stage in the formation of a dielectric layer during the formation of the semiconductor device according to some embodiments of the present disclosure.

[0030] Figure 16 This is a cross-sectional schematic diagram of an intermediate stage in the formation of an energy-removable layer during the formation of the semiconductor device, according to some embodiments of the present disclosure.

[0031] Figure 17 This is a cross-sectional schematic diagram of an intermediate stage in the formation of a dielectric layer during the formation of the semiconductor device according to some embodiments of the present disclosure.

[0032] Figure 18 FIG. 8 is a cross-sectional view of an intermediate stage of forming an energy-removable layer in accordance with some embodiments of the present disclosure.

[0033] Figure 19 FIG. 9 is a cross-sectional view of an intermediate stage of forming an energy-removable structure in accordance with some embodiments of the present disclosure.

[0034] Figure 20 FIG. 10 is a partial structure diagram of an exemplary integrated circuit having an array of memory cells in accordance with some embodiments of the present disclosure.

[0035] Wherein, the reference numerals are explained as follows:

[0036] 10: method

[0037] 100: semiconductor element

[0038] 100': semiconductor element

[0039] 101: substrate

[0040] 103: doped oxide layer

[0041] 105: patterned mask

[0042] 106: opening

[0043] 106b: opening

[0044] 108a: opening

[0045] 108b: opening

[0046] 116a: opening

[0047] 116b: opening

[0048] 118a: opening

[0049] 118b: opening

[0050] 125a: conductive feature

[0051] 125b: conductive feature

[0052] 127a: conductive feature

[0053] 127b: conductive feature

[0054] 135a: gap sub

[0055] 135b: gap sub

[0056] 135b: gap sub

[0057] 137b: gap sub

[0058] 140a: opening

[0059] 140a': opening

[0060] 140b: opening

[0061] 143: boron nitride layer

[0062] 151: energy-removable layer

[0063] 151': energy-removable structure

[0064] 1000: memory element

[0065] 20: method

[0066] 30: memory cell

[0067] 31: field effect transistor

[0068] 33: capacitor

[0069] 35: drain

[0070] 37: source

[0071] 39: gate

[0072] A: pattern dense region

[0073] B: pattern sparse region

[0074] BL: bit line

[0075] BS: bottom surface

[0076] D1: distance

[0077] D2: distance

[0078] G: air gap

[0079] H1: height

[0080] H2: height

[0081] P1: first portion

[0082] P2: second portion

[0083] TS: top surface

[0084] W1: width

[0085] W2: width

[0086] WL: word line

[0087] S11: step

[0088] S13: step

[0089] S15-1: step

[0090] S15-2: step

[0091] S15-3: step

[0092] S17: step

[0093] S19: step

[0094] S21: step

[0095] S23: step

[0096] S25: step

[0097] S27: step

[0098] S29-1: step

[0099] S29-2: step

[0100] S29-3: step

[0101] S31: step

[0102] S33: step DETAILED DESCRIPTION

[0103] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0104] "one embodiment," "an embodiment," "exemplary embodiment," "other embodiments," "another embodiment," and the like, refer to specific embodiments of the present disclosure that contain the particular feature, structure, or characteristic, but other embodiments can contain the particular feature, structure, or characteristic. Moreover, use of the phrases "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment.

[0105] In order that the present disclosure can be fully understood, the following description provides detailed steps and structures. It is apparent that the implementation of the present disclosure will not limit the specific details of the present disclosure known to those skilled in the art. In addition, known structures and steps are not described in detail in order not to unnecessarily limit the present disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure can be widely implemented in other embodiments in addition to the detailed description. The scope of the present disclosure is not limited to the detailed description, but is defined by the claims.

[0106] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the apparatus. Furthermore, the description of a first feature being formed "on" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at different scales. In the drawings, some layers / features may be omitted for simplicity.

[0107] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0108] Figure 1 This is a top view schematic diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 2 According to some embodiments of this disclosure, the semiconductor device along Figure 1 A cross-sectional view of line segment I-I'. In some embodiments, such as Figure 1 and Figure 2As shown, according to some embodiments, the semiconductor element 100 includes a semiconductor substrate 101, a plurality of conductive features 125a, 125b, 127a, 127b, a plurality of gap fillers 135a, 135b, 137a, 137b, and a dielectric layer, such as a boron nitride (BN) layer 143. In some embodiments, the conductive features 125a, 125b, 127a, 127b are conductive lines, such as interconnect lines or bit lines, configured to electrically connect two conductive terminals disposed laterally apart from each other. In some embodiments, the conductive features 125a, 125b, 127a, 127b are conductive features, such as bit line plugs or capacitor plugs, configured to electrically connect two conductive terminals disposed vertically apart from each other. The conductive features 125a, 125b, 127a, 127b are exemplified by metal plugs and described in detail in conjunction with the following figures.

[0109] In some embodiments, a plurality of insulating structures (not shown) are disposed in the semiconductor substrate 101, and a plurality of active regions (not shown) are defined by the insulating structures in the semiconductor substrate 101. Each active region can include a plurality of source / drain regions. In some embodiments, the semiconductor substrate 101 has a pattern dense region A and a pattern sparse region B, the conductive features 125a and 127a are disposed on the pattern dense region A, and the conductive features 125b and 127b are disposed on the pattern sparse region B. It should be understood that the distance Dl between the conductive features 125a and 127a is smaller than the distance D2 between the conductive features 125b and 127b. There is no apparent interface between the pattern dense region A and the pattern sparse region B. As shown in FIG. 1A, the conductive features 125a and 127a are disposed on the pattern dense region A, and the conductive features 125b and 127b are disposed on the pattern sparse region B. Figure 1 and Figure 2 The dashed lines shown are used to illustrate the present disclosure.

[0110] The gap fillers 135a and 137a are disposed on the pattern dense region A, and the gap fillers 135b and 137b are disposed on the pattern sparse region B. In some embodiments, the conductive feature 125a is surrounded by the gap filler 135a, the conductive feature 127a is surrounded by the gap filler 137a, the conductive feature 125b is surrounded by the gap filler 135b, and the conductive feature 127b is surrounded by the gap filler 137b. The dielectric layer (BN layer) 143 is disposed on the pattern dense region A and the pattern sparse region B.

[0111] In particular, the conductive features 125a, 125b, 127a, 127b and the spacers 135a, 135b, 137a, 137b located on the densely patterned region A and the sparsely patterned region B are covered by a boron nitride layer 143. In some embodiments, the boron nitride layer 143 has a first portion P1 and a second portion P2, the first portion P1 being between conductive features 125a and 127a, and the second portion P2 being between conductive features 125b and 127b. In other words, the first portion P1 of the boron nitride layer 143 is on the densely patterned region A of the semiconductor substrate 101, and the second portion P2 of the boron nitride layer 143 is on the sparsely patterned region B of the semiconductor substrate 101. Specifically, the first portion P1 of the boron nitride layer 143 is located between spacers 135a and 137a and directly contacts spacers 135a and 137a; while the second portion P2 of the boron nitride layer 143 is located between spacers 135b and 137b and directly contacts spacers 135b and 137b. In some embodiments, the contact area between the first portion P1 of the boron nitride layer 143 and spacer 135a (or spacer 137a) is smaller than the contact area between the second portion P2 of the boron nitride layer 143 and spacer 135b (or spacer 137b).

[0112] It should be understood that the first portion P1 of the boron nitride layer 143 is separated from the semiconductor substrate 101 by an air gap G, while the second portion P2 of the boron nitride layer 143 is in direct contact with the semiconductor substrate 101. In other words, there is no air gap in the patterned sparse region B. Figure 2 As shown, the second portion P2 of the boron nitride layer 143 extends to cover the lowermost portions of spacers 135b and 137b, such that spacer 135b is surrounded by conductive feature 125b, the second portion P2 of the boron nitride layer 143, and the semiconductor substrate 101, and spacer 137b is surrounded by conductive feature 127b, the second portion P2 of the boron nitride layer 143, and the semiconductor substrate 101. In some embodiments, the air gap G is located between spacers 135a and 137a in the patterned dense region A, and an upper surface TS of conductive feature 125a is a lower surface BS higher than the first portion P1 of the boron nitride layer 143 (i.e., the interface between the first portion P1 of the boron nitride layer 143 and the air gap G).

[0113] In some embodiments, the first portion P1 of the boron nitride layer 143 has a width W1, the second portion P2 of the boron nitride layer 143 has a width W2, and the width W2 is greater than the width W1. Further, the first portion P1 of the boron nitride layer 143 has a height H1, the second portion P2 of the boron nitride layer 143 has a height H2, and the height H2 is greater than the height H1. It should be understood that the height H2 of the second portion P2 of the boron nitride layer 143 is substantially the same as the height of the conductive feature 125b or the height of the conductive feature 127b. In the present disclosure, the word "substantially" means preferably 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0114] Further, a plurality of bit lines (not shown) and a plurality of storage nodes (not shown) can be formed on the structures of Figure 1 and Figure 2 In some embodiments, the bit lines and the storage nodes are electrically connected to the source / drain regions in the semiconductor substrate 101. In some embodiments, the semiconductor device 100 is a dynamic random access memory (DRAM).

[0115] Figure 3 FIG. 10 is a flow diagram of a method 10 for fabricating a semiconductor device 100 according to some embodiments of the present disclosure. According to some embodiments, the method 10 includes steps S11, S13, S15-1, S15-2, S15-3, S17, and S19. Figure 4 FIG. 20 is a flow diagram of a method 20 for fabricating a semiconductor device 100 according to some embodiments of the present disclosure. According to some embodiments, the method 20 includes steps S21, S23, S25, S27, S29-1, S29-2, S29-3, S31, and S33. Figure 3 Steps S11 to S19 of the method 10 of FIG. 10 and steps S21 to S33 of the method 20 of FIG. 20 are described in detail in conjunction with the following figures. Figure 4 Steps S11 to S19 of the method 10 of FIG. 10 and steps S21 to S33 of the method 20 of FIG. 20 are described in detail in conjunction with the following figures.

[0116] Figure 5 and Figure 7 are top view schematic diagrams of various intermediate stages in the fabrication of the semiconductor device 100. Figure 6 and Figure 8 are cross-sectional schematic diagrams of various intermediate stages in the fabrication of the semiconductor device 100 according to some embodiments. It should be understood that Figure 6 and Figure 8 are cross-sectional schematic diagrams along the cross-sectional line I-I' of Figure 5 and Figure 7 are cross-sectional schematic diagrams along the cross-sectional line I-I' of

[0117] As Figure 5 and Figure 6As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 can be a semiconductor wafer, such as a silicon wafer. Additionally or alternatively, the semiconductor substrate 101 can include an elementary semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of the elementary semiconductor material can include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of the compound semiconductor material can include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. Examples of the alloy semiconductor material can include, but are not limited to, silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP).

[0118] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer that covers a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which can include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer. The semiconductor-on-insulator substrate can be, for example, a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0119] As described above, the semiconductor substrate 101 has a pattern dense region A and a pattern sparse region B, and the insulating structure and the source / drain regions can be formed in the semiconductor substrate 101. In these examples, the conductive features 125a, 125b, 127a, 127b are formed on the source / drain regions. In some embodiments, the conductive features 125a and 127a are formed on the pattern dense region A, and the conductive features 125b and 127b are formed on the pattern sparse region B. The individual steps are illustrated in FIG. 1 1, which is step S 11 of the method 10 shown in FIG. 1. Figure 3 It should be understood that the number of conductive features on the pattern dense region A is not limited to two, and can be greater than two. Similarly, the number of conductive features on the pattern sparse region B is not limited to two, and can be greater than two.

[0120] In some embodiments, the conductive features 125a, 125b, 127a, 127b are made of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), tantalum alloy, other applicable conductive materials, or combinations thereof. In some embodiments, the conductive features 125a, 125b, 127a, 127b can be formed by electroplating. In some other embodiments, the conductive features 125a, 125b, 127a, 127b are formed by chemical vapor deposition (CVD) process, metal organic chemical vapor deposition (MOCVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, sputtering process, or other applicable processes.

[0121] Next, in FIGS. 13 and 14, according to some embodiments, the gap fillers 135a, 135b, 137a, 137b are formed to surround the conductive features 125a, 125b, 127a, 127b. The individual steps are illustrated in FIG. 13, which is step S 13 of the method 10 shown in FIG. 1. Figure 7 Figure 8 In some embodiments, the gap fillers 135a, 135b, 137a, 137b are formed on the sidewalls of the conductive features 125a, 125b, 127a, 127b. Figure 3

[0122] ​​In some embodiments, the spacers 135a, 135b, 137a, 137b are formed of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, other applicable dielectric material, or a combination thereof. In some embodiments, the spacers 135a, 135b, 137a, 137b are formed by including conformally depositing a spacer material (not shown) on the respective upper surfaces of the conductive features 125a, 125b, 127a, 127b and on the upper surface of the semiconductor substrate 101, and etching the spacer material to form the spacers 135a, 135b, 137a, 137b on the respective sidewalls of the conductive features 125a, 125b, 127a, 127b.

[0123] The deposition process for forming the spacers 135a, 135b, 137a, 137b can include a CVD process, a PVD process, an ALD process, a spin-on process, or other applicable process. Further, the etching process for forming the spacers 135a, 135b, 137a, 137b can be a non-isotropic etching process that removes the same amount of spacer material vertically at all locations, leaving the spacers 135a, 135b, 137a, 137b on the respective sidewalls of the conductive features 125a, 125b, 127a, 127b. In some embodiments, the etching process is a dry etching process. Thus, an opening 140a is obtained between the spacers 135a and 137a, and other openings 140b are obtained between the spacers 135b and 137b.

[0124] Referring to Figure 2 , according to some embodiments, after the spacers 135a, 135b, 137a, 137b are formed, a boron nitride layer 143 is deposited on the structure of Figure 7 and Figure 8 to form the air gap G in the pattern dense region A. The individual steps are illustrated in step S15-1 in the method 10 as shown in Figure 3 In some embodiments, the boron nitride layer 143 has a hexagonal textured structure.

[0125] In some embodiments, the boron nitride layer 143 is formed using ALD and / or PEALD techniques. In such embodiments, the elements are placed in a reaction chamber, preferably heated to a temperature between 100 °C and 500 °C, and a chamber pressure between 0.8 Torr and 10 Torr. More preferably, the temperature is between 300 °C and 400 °C, and the chamber pressure is between 0.5 Torr and 3 Torr.

[0126] In some embodiments, a boron precursor gas or a precursor gas diluted with an inert gas, such as boron trichloride (BC13), trimethylboron (B(CH3)3), diborane (B2H6), boron tribromide (BBr3), and the inert gas is, for example, helium (He) or argon (Ar), is pulsed into the chamber to allow formation of a monolayer or less than a monolayer on each exposed surface of the element, i.e., the gate stack, hardmask, semiconductor body, and each surface of the liner layer, if present. In some embodiments, the boron precursor is pulsed for a period of time between 2 seconds and 30 seconds, and at a flow rate from 50 standard cubic centimeters per minute (seem) to 1000 seem. In some embodiments, the boron precursor is pulsed into the chamber at a flow rate between 100 seem and 500 seem.

[0127] In some embodiments, after the boron precursor is pulsed into the chamber, the chamber is purged with an inert gas, such as nitrogen (N2), argon (Ar), or helium (He), for a period of time (e.g., 30 seconds) to remove by-products and all unreacted species from the chamber.

[0128] In some embodiments, then, a nitrogen-containing reactive gas is pulsed into the deposition chamber to react with the first layer and form a monolayer of boron nitride, and the nitrogen-containing reactive gas is, for example, nitrogen, ammonia (NH3), or a mixture of nitrogen and hydrogen (H2). In some embodiments, the nitrogen-containing gas is pulsed into the chamber for a period of time between 1 second and 10 seconds, and at a flow rate between 50 seem and 1000 seem. In some embodiments, the nitrogen-containing gas is pulsed into the chamber at a flow rate between 100 seem and 300 seem.

[0129] In some embodiments, when the nitrogen-containing reactive gas is provided to the chamber, PEALD techniques can also be used to assist in the reaction to form boron-nitrogen bonds by using plasma to dissociate the reactive gas. In some embodiments, where PEALD is used, the plasma is generated at a power between 50 W and 500 W, and more preferably, the power is between 100 W and 200 W.

[0130] In some embodiments, after the nitrogen-containing reactive gas is pulsed, the chamber is again purged for a suitable period of time, and the cycle is repeated until deposition of the boron nitride layer has occurred to the desired thickness.

[0131] Since the width W2 of the opening 140b is larger than the width W1 of the opening 140a (see Figure 8 ), the opening 140b is completely filled with the boron nitride layer 143 due to a loading effect, while the opening 140a is only partially filled with the boron nitride layer 143. As a result, the air gap G is enclosed by the first portion P1 of the boron nitride layer 143. In some embodiments, the air gap G is enclosed by the first portion P1 of the boron nitride layer 143, the gaps 135a and 137a, and the semiconductor substrate 101. Furthermore, as shown, in accordance with some embodiments, the width W2 is also the width of a second portion P2 of the boron nitride layer 143 between the gaps 135b and 137b, and the width W1 is also the width W1 of the first portion P1 of the boron nitride layer 143 between the gaps 135a and 137a. Figure 2

[0132] After the boron nitride layer 143 is deposited, the semiconductor device 100 is obtained. By forming the air gap G between the conductive features 125a and 127a (or between the gaps 135a and 137a surrounding the conductive features 125a and 127a), the parasitic capacitance between the conductive features 125a and 127a, especially in the pattern dense region A, can be reduced. As a result, the overall device performance (i.e. power consumption and signal delay) can be improved.

[0133] Figures 9 to 15 FIGS. 2A to 2E are cross-sectional schematic views of various intermediate stages of forming the semiconductor device 100 in accordance with some embodiments. As shown, the fabrication method is different from the fabrication method shown in FIGS. 1A to 1E. Figures 9 to 15 Figure 1 Figure 2 Figures 5 to 8

[0134] In accordance with some embodiments, as shown, a doped oxide layer is formed on the pattern dense region A and the pattern sparse region B of the semiconductor substrate 101. The individual steps are shown in step S21 of the method 20 as shown. Figure 9 Figure 4 In some embodiments, the doped oxide layer 103 is made of silicon oxide, or is implanted with P-type dopants or N-type dopants, where the P-type dopants are, for example, boron (B), gallium (Ga), or indium (In), and the N-type dopants are, for example, phosphorus (P) or arsenic (As). In some embodiments, the doped oxide layer 103 is formed by a deposition process, and is doped in-situ during the deposition process. In some other embodiments, the doped oxide layer 103 is formed by a deposition process followed by an ion implantation process.

[0135] Next, in accordance with some embodiments, as shown,​​​​​​Figure 10 As shown, a patterned mask 105 is formed on the doped oxide layer 103. The patterned mask 105 has openings 106a, 106b, 108a, 108b and some portions of the doped oxide layer 103 are exposed through the openings 106a, 106b, 108a, 108b of the patterned mask 105.

[0136] The patterned mask 105 is formed by a deposition process and a patterning process. The deposition process for forming the patterned mask 105 can be a CVD process, a high-density plasma CVD (HDCVD) process, a spin-coating process or other applicable processes. The patterning process for forming the patterned mask 105 can include a photolithography process and an etching process. The photolithography process can include photoresist coating (i.e. spin-coating), soft baking, mask aligning, exposure, post-exposure baking, developing photoresist, rinsing, and drying (e.g. hard baking). The etching process can include a dry etching process or a wet etching process.

[0137] Next, according to some embodiments, as shown in FIG. 1C, an etching process is performed on the doped oxide layer 103 using the patterned mask 105 as a mask. After the etching process, openings 116a, 116b, 118a, 118b are formed in the doped oxide layer 103. In some embodiments, some portions of the semiconductor substrate 101 are exposed through the openings 116a, 116b, 118a, 118b of the doped oxide layer 103. In particular, according to some embodiments, the openings 116a and 118a are on the pattern-dense region A of the semiconductor substrate 101, and the openings 116b and 118b are on the pattern-sparse region B of the semiconductor substrate 101. After the openings 116a, 116b, 118a, 118b are formed, the patterned mask 105 can be removed. Figure 11 Then, according to some embodiments, as shown in FIG. 1D, conductive features 125a, 125b, 127a, 127b are formed in the openings 116a, 116b, 118a, 118b. The individual steps are illustrated in step S23 of the method 20 as shown in FIG. 1E. In some embodiments, the conductive features 125a and 127a are formed on the pattern-dense region A of the semiconductor substrate 101, and the conductive features 125b and 127b are formed on the pattern-sparse region B of the semiconductor substrate 101.

[0138] Figure 12 Figure 4

[0139] The conductive features 125a, 125b, 127a, 127b are formed by a deposition process and a patterning process. The deposition process for forming the conductive features 125a, 125b, 127a, 127b can be a CVD process, a high-density plasma CVD (HDCVD) process, a spin-coating process or other applicable processes. The patterning process for forming the conductive features 125a, 125b, 127a, 127b can include a photolithography process and an etching process. The photolithography process can include photoresist coating (i.e. spin-coating), soft baking, mask aligning, exposure, post-exposure baking, developing photoresist, rinsing, and drying (e.g. hard baking). The etching process can include a dry etching process or a wet etching process. Figure 12 ​​​The conductive characteristics of some materials, such as 125a, 125b, 127a, and 127b, are similar to or identical to those used in forming... Figure 6 The conductive characteristics of materials 125a, 125b, 127a, and 127b are described, but their detailed descriptions will not be repeated in this text. Furthermore, Figure 12 The formation of conductive features 125a, 125b, 127a, 127b may include depositing a conductive material (not shown) in openings 116a, 116b, 118a, 118b and on the doped oxide layer 103; and performing a planarization process to remove excess conductive material to expose the doped oxide layer 103. In some embodiments, after the openings 116a, 116b, 118a, 118b are formed, the patterned mask 105 (see reference) is not removed. Figure 10 The conductive layer is deposited in openings 116a, 116b, 118a, 118b, and on the patterned mask 105. In these examples, the patterned mask 105 can be removed during the planarization process. The planarization process can be a chemical mechanical polishing (CMP) process.

[0140] According to some embodiments, such as Figure 13 As shown, after the conductive features 125a, 125b, 127a, and 127b are formed, the doped oxide layer 103 is removed. Individual steps are illustrated in... Figure 4 Step S25 of method 20 is shown. In some embodiments, the doped oxide layer 103 is removed by an ashing or stripping process. In some other embodiments, an etching process is used to remove the doped oxide layer 103. The etching process may include a wet etching process, a dry etching process, or a combination thereof.

[0141] Next, based on some embodiments, such as Figure 14 As shown, spacers 135a, 135b, 137a, and 137b are formed to surround conductive features 125a, 125b, 127a, and 127b. Individual steps are illustrated in... Figure 4 Step S27 of method 20 is shown. Used in forming Figure 14 The materials and processes used in the spacers 135a, 135b, 137a, and 137b are similar to or identical to those used in the formation of... Figure 8 The gaps 135a, 135b, 137a, and 137b are not described in detail here.

[0142] After the spacers 135a, 135b, 137a, and 137b are formed, an opening 140a is obtained between spacers 135a and 137a, and an opening 140b is obtained between spacers 135b and 137b. It should be understood that, according to some embodiments, the width W1 of the opening 140a in the dense pattern region A is smaller than the width W2 of the opening 140b in the sparse pattern region B.

[0143] According to some embodiments, such as Figure 15 As shown, after the formation of spacers 135a, 135b, 137a, and 137b, boron nitride layer 143 is deposited. Figure 14 Structurally, this allows the air gap G to form an opening 140a in the patterned dense region A. Individual steps are illustrated as follows: Figure 4 Step S29-1 in method 20 is shown. Used in forming Figure 15 Some materials and processes used in the formation of boron nitride layer 143 are similar to or identical to those used in the process of... Figure 2 The materials and processes of the boron nitride layer 143 are not described in detail here.

[0144] As mentioned above, the width W2 of opening 140b is larger than the width W1 of opening 140a (please refer to...). Figure 14 Therefore, opening 140b is completely filled by boron nitride layer 143, while opening 140a is only partially filled by boron nitride layer 143 due to the loading effect. Thus, air gap G is sealed by the first portion P1 of boron nitride layer 143, while the second portion P2 of boron nitride layer 143 is in direct contact with semiconductor substrate 101.

[0145] Figures 16 to 18 This is a cross-sectional schematic diagram showing the intermediate stages in forming the semiconductor device 100 according to some embodiments. Figures 16 to 18 The preparation method shown is different from that of... Figure 1 , Figure 2 as well as Figures 5 to 8 The preparation method shown and as Figures 9 to 15 The preparation method shown.

[0146] According to some embodiments, in Figure 8 or Figure 14 After the structure, such as Figure 16 As shown, an energy-removable layer 151 is selectively deposited between spacers 135a and 137a in the patterned dense region A. Individual steps are illustrated as follows: Figure 4Step S29-2 in method 20 shown. It should be understood that, according to some embodiments, the energy-removable layer 151 is formed by performing a deposition process that selectively deposits the energy-removable layer 151 between spacers 135a and 137a in the patterned dense region A, without depositing the energy-removable layer 151 between spacers 135b and 137b in the patterned sparse region B.

[0147] In some embodiments, the material of the energy-removable layer 151 includes a photodegradable material, an electron beam degradable material, or other applicable energy-regradable material. In particular, in some embodiments, the material of the energy-removable layer 151 includes a base material and a degradable pore-forming material that is substantially removed upon exposure to an energy source (i.e., a heat source).

[0148] In some embodiments, the base material comprises hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous SiO2, while the decomposable pore-forming material comprises a porogen organic compound that provides porosity to the space otherwise occupied by the energy-removable layer 151 in subsequent processes. Furthermore, the deposition process for forming the energy-removable layer 151 may include CVD, PVD, ALD, spin coating, or other applicable processes. After the energy-removable layer 151 is formed, a reduced opening 140a' is obtained on the energy-removable layer 151.

[0149] Then, according to some embodiments, such as Figure 17 As shown, a boron nitride layer 143 is formed to cover as... Figure 16 The structure is shown. Individual steps are illustrated in, for example... Figure 3 Step S17 in method 10 shown, and in such a way Figure 4 Step S31 in method 20 shown. Using in forming Figure 17 Some materials and processes used in the boron nitride layer 143 are similar to or identical to those used in other boron nitride layers. Figure 2 The boron nitride layer 143 is described in detail elsewhere, but will not be repeated here. It should be understood that there is no air gap in the structure at this stage.

[0150] According to some embodiments, such as Figure 18As shown, after the deposition of the boron nitride layer 143, a heat treatment process is performed. In some embodiments, during the heat treatment process, an energy-removable layer 151 is removed to allow an air gap G to form between spacers 135a and 137a in the patterned dense region A. Individual steps are illustrated as follows: Figure 3 Step S19 in method 10 shown, and in such a way Figure 4 Step S33 in method 20 shown.

[0151] More specifically, according to some embodiments, a heat treatment process is used to remove the biodegradable pore-forming material of the energy-removable layer 151, thereby creating pores that are filled with air to obtain air gaps G. In some other embodiments, the heat treatment process can be replaced by a light treatment process, an electron beam treatment process, a combination thereof, or other applicable energy treatment processes. For example, ultraviolet light or laser light can be used to remove the biodegradable pore-forming material of the energy-removable layer 151 to obtain air gaps G.

[0152] Figure 19 This is a cross-sectional schematic diagram of an intermediate stage in the formation of an energy-removable structure 151' during the formation of an improved semiconductor element 100', according to some embodiments of the present disclosure.

[0153] continue Figure 17 According to some embodiments, such as Figure 19 As shown, a heat treatment process is performed to remove a portion of the energy-removable layer 151. In some embodiments, during the heat treatment process, the energy-removable layer 151 is transformed into an energy-removable structure 151' such that the air gap G is surrounded by the energy-removable structure 151'. Individual steps are illustrated in... Figure 3 Step S19 in method 10 shown, and in such a way Figure 4 Step S33 in method 20 shown.

[0154] More specifically, in some embodiments, a heat treatment process is used to remove the biodegradable pore-forming material of the energy-removable layer 151 to create multiple pores, and the base material of the energy-removable material 151 is accumulated at the edges of the energy-removable material 151. According to some embodiments, after removing the biodegradable pore-forming material, the pores are filled with air to create an air gap G (i.e., energy-removable structure 151') inside the remaining portion of the energy-removable layer 151. In some other embodiments, due to gravity, the air gap G is not completely surrounded by the energy-removable structure 151', and a portion of the energy-removable structure 151' is located between the air gap G and the semiconductor substrate 101. After the energy-removable structure 151' is formed, an improved semiconductor element 100' is obtained.

[0155] Figure 20 Figure 1 illustrates a portion of an exemplary integrated circuit having an array of memory cells 30 in accordance with some embodiments of the present disclosure. The integrated circuit is, for example, a memory device 1000. In some embodiments, the memory device 1000 comprises a dynamic random access memory (DRAM). In some embodiments, the memory device 1000 comprises a plurality of memory cells 30 arranged in a grid pattern and having a plurality of rows and a plurality of columns. The number of memory cells 30 can vary depending on the system requirements and the manufacturing technology.

[0156] In some embodiments, each memory cell 30 has an access element and a storage element. The access element is configured to provide control for accessing the storage element. In particular, in accordance with some embodiments, the access element is a field effect transistor (FET) 31 and the storage element is a capacitor 33. In each memory cell 30, the FET 31 has a drain 35, a source 37, and a gate 39. One terminal of the capacitor 33 is electrically connected to the source 37 of the FET 31, and the other terminal of the capacitor 33 can be electrically connected to ground. In addition, in each memory cell 30, the gate 39 of the FET 31 is electrically connected to a word line WL, and the drain 35 of the FET 31 is electrically connected to a bit line BL.

[0157] The above description refers to the terminal of the FET 31 electrically connected to the capacitor 33 being the source 37, and the terminal of the FET 31 electrically connected to the bit line BL being the drain 35. However, during read and write operations, the terminal of the FET 31 electrically connected to the capacitor 33 can be the drain, and the terminal of the FET 31 electrically connected to the bit line BL can be the source. That is, either terminal of the FET 31 can be a source or a drain, depending on the manner in which the FET 31 is controlled by the voltages applied to the source, drain, and gate.

[0158] By controlling the voltage at the gate 39 via the word line WL, a voltage potential can be generated across the FET 30 such that electrical charge can flow from the source 35 to the capacitor 33. Thus, the electrical charge stored in the capacitor 33 can represent a binary data in the memory cell 30. For example, a positive electrical charge stored in the capacitor 33 above a threshold voltage represents a binary "1." If the electrical charge in the capacitor 33 is below the threshold, a binary "0" can be said to be stored in the memory cell 30.

[0159] The bit lines BL are configured to read or write data from or to the memory cells 30. The word lines WL are configured to activate the field transistors 31 to access a particular column of the memory cells 30. Accordingly, the memory element 1000 also has a peripheral region which can include an address buffer, a row decoder, and a column decoder. The row and column decoders selectively access the memory cells 30 in response to a plurality of address signals which are provided to the address buffer during read, write, and refresh operations. The address signals are typically provided by an external controller, such as a microprocessor or other type of memory controller.

[0160] Please refer back to Figure 2 and Figure 19 , an air gap G is formed in a pattern dense region A of the semiconductor element 100 or 100', while no air gap is formed in a pattern sparse region B of the semiconductor element 100 or 100'. The pattern dense region A can be any one of the regions of the memory cells 30 of the memory element 1000, and the pattern sparse region B can be any one of the regions of the address buffer, the column decoder, or the row decoder of the memory element 1000.

[0161] In the present disclosure, a plurality of embodiments of a semiconductor device 100 and 100' are provided. The semiconductor device 100 and 100' has a plurality of conductive features 125a, 125b, 127a, 127b and a boron nitride layer 143, the conductive features 125a, 125b, 127a, 127b are on a pattern dense region A and a pattern sparse region B of a semiconductor substrate 101, a gap sub 135a, 135b, 137a, 137b respectively surrounds the conductive features 125a, 125b, 127a, 127b; and the boron nitride layer 143 covers the conductive features 125a, 125b, 127a, 127b and the gap sub 135a, 135b, 137a, 137b. In particular, the boron nitride layer 143 has a first portion P1 and a second portion P2, the first portion P1 is between the conductive features 135a and 137a in the pattern dense region A, and the second portion P2 is between the conductive features 135b and 137b in the pattern sparse region B; the first portion P1 of the boron nitride layer 143 is disposed apart from the semiconductor substrate 101 by an air gap G, and the second portion P2 of the boron nitride layer 143 directly contacts the semiconductor substrate 101. Therefore, the parasitic capacitance between the conductive features 125a and 127a on the pattern dense region A can be reduced. Therefore, the overall device performance (i.e. reduced power consumption and resistance-capacitance delay) can be improved.

[0162] An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first conductive feature and a second conductive feature disposed on a pattern dense region of a semiconductor substrate. The semiconductor device also has a third conductive feature and a fourth conductive feature disposed on a pattern sparse region of the semiconductor substrate. The semiconductor device further has a boron nitride layer disposed on the pattern dense region and the pattern sparse region of the semiconductor substrate, wherein a first portion of the boron nitride layer between the first conductive feature and the second conductive feature is disposed apart from the semiconductor substrate by an air gap; and a second portion of the boron nitride layer between the third conductive feature and the fourth conductive feature directly contacts the semiconductor substrate.

[0163] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a first conductive feature and a second conductive feature disposed on a pattern dense region of the semiconductor substrate. The semiconductor device also has a third conductive feature and a fourth conductive feature disposed on a pattern sparse region of the semiconductor substrate, wherein a distance between the first conductive feature and the second conductive feature is less than a distance between the third conductive feature and the fourth conductive feature. The semiconductor device further has a boron nitride layer covering the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature. The boron nitride layer has a first portion between the first conductive feature and the second conductive feature and a second portion between the third conductive feature and the fourth conductive feature, and a height of the second portion is greater than a height of the first portion.

[0164] Another embodiment of the present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first conductive feature, a second conductive feature, a third conductive feature, and a fourth conductive feature on a semiconductor substrate, wherein the first conductive feature and the second conductive feature are formed on a pattern dense region of the semiconductor substrate, and the third conductive feature and the fourth conductive feature are formed on a pattern sparse region of the semiconductor substrate; and depositing a boron nitride layer on the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature; wherein a first portion of the boron nitride layer extends between the first conductive feature and the second conductive feature such that the first portion of the boron nitride layer is disposed apart from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer extends between the third conductive feature and the fourth conductive feature such that the second portion of the boron nitride layer directly contacts the semiconductor substrate.

[0165] Embodiments of the present disclosure have some advantageous features. By forming an air gap between adjacent conductive features in a pattern dense region, the parasitic capacitance between the conductive features in the pattern dense region can be reduced. This greatly improves the overall device performance.

[0166] While the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be implemented in different methodologies than those described above, and the methodologies described above can be implemented in other sequences than those described above and in combinations of the described methodologies, and other processes can also be used instead of or in addition to the processes described above.

[0167] Moreover, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of the present application is intended to be illustrative, but not limiting, of the scope of the application, which is set forth in the following claims.

Claims

1. A semiconductor device, comprising: a first conductive feature and a second conductive feature disposed on a pattern dense region of a semiconductor substrate; a third conductive feature and a fourth conductive feature disposed on a pattern sparse region of the semiconductor substrate; a boron nitride layer disposed on the pattern dense region and the pattern sparse region of the semiconductor substrate, wherein a first portion of the boron nitride layer between the first conductive feature and the second conductive feature is disposed apart from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer between the third conductive feature and the fourth conductive feature directly contacts the semiconductor substrate; and an energy removable structure disposed between the first conductive feature and the second conductive feature, wherein a portion of the energy removable structure is between the air gap and the semiconductor substrate. The first conductive feature is separated from the second conductive feature by a first distance, the third conductive feature is separated from the fourth conductive feature by a second distance, and the second distance is greater than the first distance.

2. The semiconductor element according to claim 1, wherein The first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature are covered by the boron nitride layer, and an upper surface of the first conductive feature is higher than a lower surface of the first portion of the boron nitride layer.

3. The semiconductor device according to claim 1, wherein 4. The semiconductor device of claim 1, further comprising: a first gap sub disposed on a sidewall of the first conductive feature; and a second gap sub disposed on a sidewall of the second conductive feature, wherein the air gap is surrounded by the first gap sub, the second gap sub, the first portion of the boron nitride layer, and the semiconductor substrate.

5. The semiconductor device of claim 1, further comprising: a third gap sub disposed on a sidewall of the third conductive feature, wherein the third gap sub is surrounded by the third conductive feature, the boron nitride layer, and the semiconductor substrate; and a fourth gap sub disposed on a sidewall of the fourth conductive feature, wherein the fourth gap sub is surrounded by the fourth conductive feature, the boron nitride layer, and the semiconductor substrate. The pattern dense region is in a memory cell of a memory device, and the pattern sparse region is in a surrounding region outside the memory cell of the memory device.

7. A semiconductor device, comprising:

6. The semiconductor device according to claim 1, wherein a first conductive feature and a second conductive feature disposed on a pattern dense region of a semiconductor substrate; a third conductive feature and a fourth conductive feature disposed on a pattern sparse region of the semiconductor substrate, wherein a distance between the first conductive feature and the second conductive feature is less than a distance between the third conductive feature and the fourth conductive feature; a boron nitride layer covering the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature, wherein the boron nitride layer has a first portion between the first conductive feature and the second conductive feature, and a second portion between the third conductive feature and the fourth conductive feature, and a height of the second portion is greater than a height of the first portion. ​ ​ a first gap sub on a sidewall of the first conductive feature; a second gap sub on a sidewall of the second conductive feature; a third gap sub on a sidewall of the third conductive feature; a fourth gap sub on a sidewall of the fourth conductive feature, wherein the air gap is between the first gap sub and the second gap sub; and an energy-removable structure disposed between the first gap sub and the second gap sub and covered by the first portion of the boron nitride layer, wherein the energy-removable structure surrounds the air gap, and the air gap is between the first conductive feature and the second conductive feature.

8. The semiconductor device according to claim 7, wherein The height of the second portion is substantially the same as a height of the third conductive feature, and the first portion is disposed apart from the semiconductor substrate by an air gap between the first conductive feature and the second conductive feature.

9. The semiconductor device according to claim 7, wherein A width of the second portion of the boron nitride layer is greater than a width of the first portion of the boron nitride layer.

10. The semiconductor device according to claim 8, wherein A contact area between the second portion of the boron nitride layer and the third gap sub is greater than a contact area between the first portion of the boron nitride layer and the first gap sub.

11. A method for fabricating a semiconductor device, comprising: forming a first conductive feature, a second conductive feature, a third conductive feature, and a fourth conductive feature on a semiconductor substrate, wherein the first conductive feature and the second conductive feature are formed on a pattern-dense region of the semiconductor substrate, and the third conductive feature and the fourth conductive feature are formed on a pattern-sparse region of the semiconductor substrate; depositing a boron nitride layer on the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature, wherein a first portion of the boron nitride layer extends between the first conductive feature and the second conductive feature such that the first portion of the boron nitride layer is disposed apart from the semiconductor substrate by an air gap, and a second portion of the boron nitride layer extends between the third conductive feature and the fourth conductive feature such that the second portion of the boron nitride layer directly contacts the semiconductor substrate; prior to the depositing of the boron nitride layer, forming a first gap sub on a sidewall of the first conductive feature, forming a second gap sub on a sidewall of the second conductive feature, forming a third gap sub on a sidewall of the third conductive feature, and forming a fourth gap sub on a sidewall of the fourth conductive feature; and prior to the depositing of the boron nitride layer, performing a deposition process to selectively form an energy-removable layer between the first gap sub and the second gap sub in the pattern-dense region without depositing the energy-removable layer between the third gap sub and the fourth gap sub in the pattern-sparse region, wherein the boron nitride layer is formed to cover the energy-removable layer, and the method further comprises performing a thermal treatment to transform the energy-removable layer into an energy-removable structure, wherein the air gap is surrounded by the energy-removable structure, and the energy-removable structure is denser than the energy-removable layer.

12. The method for producing a semiconductor element according to claim 11, wherein A lowermost width of the second portion of the boron nitride layer is greater than a lowermost width of the first portion of the boron nitride layer.

13. The method for producing a semiconductor element according to claim 11, wherein Formation of the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature includes: forming a doped oxide layer on the semiconductor substrate; etching the doped oxide layer to form a plurality of openings to expose the semiconductor substrate; forming the first conductive feature, the second conductive feature, the third conductive feature, and the fourth conductive feature in the openings; and removing the doped oxide layer is performed prior to deposition of the boron nitride layer.

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