Semiconductor device

Abstract

A semiconductor device includes a gate electrode on a substrate, a channel on the substrate surrounding a side wall of the gate electrode, and source / drain electrodes on the substrate on opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source / drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.

Description

Technical Field

[0001] The example implementation relates to a semiconductor device. More specifically, the example implementation relates to a semiconductor device having a channel comprising an oxide semiconductor. Background Technology

[0002] In related technology transistors with channels including oxide semiconductors, source / drain electrodes are formed on the channel, and a gate electrode is formed between the source / drain electrodes. Since impurities may not be doped into the channel, the conduction current may decrease and the oscillation characteristics may deteriorate as the distance between the source and drain electrodes increases. If the distance between the source and drain electrodes decreases, the parasitic capacitance between the source / drain electrodes and the gate electrode increases, and the insulating layer between them may be damaged by breakdown voltage. Summary of the Invention

[0003] An example implementation provides a semiconductor device with good characteristics.

[0004] According to an example embodiment, a semiconductor device is provided. The semiconductor device may include: a gate electrode on a substrate; a channel on the substrate surrounding a sidewall of the gate electrode; and source / drain electrodes on the substrate, on opposite sides of the gate electrode in a first direction parallel to the upper surface of the substrate. The thickness of the channel from the gate electrode to the source / drain electrode in the horizontal direction parallel to the upper surface of the substrate may not be constant, but may vary in a vertical direction perpendicular to the upper surface of the substrate.

[0005] According to an example embodiment, a semiconductor device is provided. The semiconductor device may include: a gate electrode on a substrate; a channel on the substrate surrounding a sidewall of the gate electrode; and source / drain electrodes on opposite sides of the gate electrode in a first direction parallel to the upper surface of the substrate. The distance between the gate electrode and each source / drain electrode in the first direction may not be constant, but may vary in a vertical direction perpendicular to the upper surface of the substrate.

[0006] According to an example embodiment, a semiconductor device is provided. The semiconductor device may include: a gate electrode on a substrate; a channel on the substrate surrounding a sidewall of the gate electrode; source / drain electrodes on the substrate, on opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate; a first contact plug on the gate electrode; second and third contact plugs on the source / drain electrodes; and first to third wirings respectively contacting the upper surfaces of the first to third contact plugs. The thickness of the channel in a horizontal direction parallel to the upper surface of the substrate may not be constant, but may vary in a vertical direction perpendicular to the upper surface of the substrate, and the thickness of each of the source / drain electrodes in the horizontal direction may not be constant, but may vary in the vertical direction. The horizontal distance between the first contact plug and each of the second and third contact plugs may be greater than the minimum horizontal distance between the gate electrode and each of the source / drain electrodes. Attached Figure Description

[0007] Figure 1 and Figure 2 These are a plan view and a cross-sectional view of a semiconductor device according to an example embodiment;

[0008] Figures 3 to 21 These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment;

[0009] Figure 22 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0010] Figure 23 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0011] Figure 24 and Figure 25 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment; and

[0012] Figures 26 to 28 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0013] The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein the same reference numerals always refer to the same elements.

[0014] Figure 1 and Figure 2 These are a plan view and a cross-sectional view of a semiconductor device according to an example embodiment. Figure 1 It's a floor plan. Figure 2 It is along Figure 1 Cross-sectional view of the centerline A-A'.

[0015] In the following description (but not necessarily in the claims), two directions that are substantially parallel to the upper surface of the substrate and intersect each other may be defined as a first direction D1 and a second direction D2, respectively, and a direction that is substantially perpendicular to the upper surface of the substrate may be defined as a third direction D3. In some example embodiments, the first direction D1 and the second direction D2 may be substantially perpendicular to each other.

[0016] Reference Figure 1 and Figure 2 The semiconductor device may include a gate electrode 250 on a substrate 100, a channel 180 surrounding the sidewall of the gate electrode 250, source / drain electrodes 260 and 265 on the substrate 100 on opposite sides of the gate electrode 250 in a first direction D1, a first contact plug 280 on the gate electrode 250, a second contact plug 290 and a third contact plug 295 on the source / drain electrodes 260 and 265, and a first wiring 310, a second wiring 320 and a third wiring 325 that respectively contact the upper surfaces of the first to third contact plugs 280, 290 and 295.

[0017] The semiconductor device may also include a pad layer 110, an etch stop layer 120, an insulating layer 130, a separator layer 150, a gate insulating pattern 190, and a barrier pattern 230.

[0018] The substrate 100 may include semiconductor materials, such as silicon, germanium, silicon-germanium, or III-V semiconductor compounds, such as GaP, GaAs, GaSb, etc.

[0019] Pad layer 110 and etch stop layer 120 may be sequentially stacked on substrate 100. Pad layer 110 may include oxide, such as silicon oxide, and etch stop layer 120 may include metal oxide, such as aluminum oxide.

[0020] In some example embodiments, the gate electrode 250 may extend along the first direction D1 between source / drain electrodes 260 and 265 spaced apart from each other, and the plurality of gate electrodes 250 may be spaced apart from each other along a second direction D2. Figure 1 In the example embodiment shown, two gate electrodes 250 are illustrated between the source / drain electrodes 260 and 265. However, the inventive concept is not limited thereto, and in some embodiments, only one gate electrode 250 may be formed between the source / drain electrodes 260 and 265.

[0021] The gate electrode 250 may include metals such as tungsten, copper, aluminum, titanium, tantalum, etc.

[0022] The sidewalls and lower surface of the gate electrode 250 may be covered by a gate insulating pattern 190. The gate insulating pattern 190 may include oxides, such as silicon oxide.

[0023] The channel 180 may cover the sidewalls and lower surface of the gate insulating pattern 190, which in turn covers the sidewalls and lower surface of the gate electrode 250, so that the channel 180 may surround the sidewalls of the gate electrode 250. In some example embodiments, the channel 180 may cover the sidewalls and lower surface of the gate insulating pattern 190, which in turn covers the sidewalls and lower surface of the gate electrode 250, such that the channel 180 may surround the sidewalls of the gate electrode 250 and the gate insulating pattern 190 is located therebetween.

[0024] In an example implementation, the channel 180 may have a thickness in the first direction D1 (i.e., the horizontal direction), which may not be constant but may vary in the third direction D3 (i.e., the vertical direction). Unlike the inner wall of the channel 180 that contacts the gate insulating pattern 190, the outer wall of the channel 180 that does not contact the gate insulating pattern 190 may not be flat or level, but may have protrusions and depressions in the third direction, as shown in... Figure 2 As best seen in the image. In some example embodiments, the channel 180 may have a first portion having a relatively large thickness in the first direction D1 (i.e., the horizontal direction) and a second portion having a relatively small thickness in the first direction D1, the first portion and the second portion may be stacked alternately and repeatedly in the third direction D3, such as Figure 2 As shown. The second portion of the channel 180 may contact the sidewall of the insulating layer 130.

[0025] In some example embodiments, channels 180 surrounding the sidewalls of the gate electrode 250, which is spaced apart from each other in a second direction D2 between the source / drain electrodes 260 and 265, can be connected to each other, with the source / drain electrodes 260 and 265 spaced apart from each other in a first direction D1. That is, in some example embodiments, in Figure 1 The channels 180 of the central gate electrode 250 can be connected to each other. However, the inventive concept is not limited thereto, and the channels 180 surrounding the sidewalls of the gate electrode 250 may not be connected to each other but may be spaced apart. In this case, nitrides (e.g., silicon nitrides, see...) are included. Figure 9 and Figure 10 A portion of the first sacrificial layer 140 may be retained between the first portions of the channel 180.

[0026] In an example embodiment, channel 180 may include an oxide semiconductor. The oxide semiconductor may include, for example, barium tin oxide (BaSnO3), zinc oxide (ZnO), lanthanum aluminate / strontium titanate tandem (LaAlO3 / SrTiO3), gallium oxide (Ga2O3), tin oxide (SnO2), indium oxide (In2O3), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium tin oxide (ITO), indium tungsten tin oxide (IWZO), and / or indium zinc oxide (IZO).

[0027] However, the inventive concept is not limited thereto, and the channel 180 may include other materials, such as amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon germanium, etc. In other exemplary embodiments, the channel 180 may include two-dimensional materials, such as carbon nanotubes (CNTs), or transition metal dichalcogenides (TMDCs), such as molybdenum ditelluride (MoTe2), molybdenum disulfide (MoS2), etc.

[0028] like Figure 2 As shown in the example, each of the source / drain electrodes 260 and 265 may include a vertical portion extending in a third direction D3 and a horizontal portion extending in a first direction D1. In the example implementation, the plurality of horizontal portions may be spaced apart from each other in the third direction D3, so that the width of each of the source / drain electrodes 260 and 265 in the horizontal direction may change periodically in the third direction D3.

[0029] In an example embodiment, a first portion of the channel 180 may face the horizontal portion of each of the source / drain electrodes 260 and 265 in a first direction D1, and a second portion of the channel 180 may face the vertical portion of each of the source / drain electrodes 260 and 265 in the first direction D1. An insulating layer 130 may be interposed between the second portion of the channel 180 and the vertical portion of each of the source / drain electrodes 260 and 265.

[0030] In the example embodiment, the first distance S1 between the sidewall of the horizontal portion of the first portion of the source / drain electrode 260 and 265 facing the channel 180 and the sidewall of the gate electrode 250 can be smaller than the second distance S2 between the sidewall of the vertical portion of the second portion of the source / drain electrode 260 and 265 facing the channel 180 and the sidewall of the gate electrode 250. That is, even if the first portion of the channel 180 surrounding the sidewall of the gate electrode 250 has a thickness greater than its second portion, the horizontal portion of the first portion of the source / drain electrode 260 and 265 facing the channel 180 can have a width greater than the width of the vertical portion of the second portion of the source / drain electrode 260 and 265 facing the channel 180, so the distance from the horizontal portion of the source / drain electrode 260 and 265 to the gate electrode 250 can be smaller than the distance from the vertical portion of the source / drain electrode 260 and 265 to the gate electrode 250.

[0031] Therefore, the distance between the gate electrode 250 and each of the source / drain electrodes 260 and 265 in the first direction D1 may not be constant, but may vary in the third direction D3. In particular, the first and second portions of the channel 180 may be alternately and repeatedly arranged in the third direction D3, and the horizontal and vertical portions of each of the source / drain electrodes 260 and 265 may be alternately and repeatedly arranged in the third direction D3. Therefore, the distance between the gate electrode 250 and each of the source / drain electrodes 260 and 265 in the first direction D1 may change periodically in the third direction D3.

[0032] In an example embodiment, one of the source / drain electrodes 260 and 265, located on opposite sides of the gate electrode 250 in the first direction D1, can be used as a source electrode, and the other can be used as a drain electrode. Each of the source / drain electrodes 260 and 265 may include a metal, such as tungsten, copper, aluminum, titanium, tantalum, etc.

[0033] The blocking pattern 230 may cover the sidewalls and lower surface of each of the source / drain electrodes 260 and 265. In some example embodiments, the blocking pattern 230 may cover the sidewalls and lower surface of each of the source / drain electrodes 260 and 265. Thus, the blocking pattern 230 covering the sidewalls of the horizontal portion of each of the source / drain electrodes 260 and 265 may contact the sidewalls of the first portion of the channel 180. The blocking pattern 230 may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, etc., or a metal, such as titanium, tantalum, etc.

[0034] Each of the source / drain electrodes 260 and 265, as well as the blocking pattern 230, can form a source / drain electrode structure.

[0035] Multiple insulating layers 130 may be formed at multiple horizontal locations, spaced apart from each other on a third direction D3, and may be interposed between the second portion of the channel 180 and the vertical portions of each of the source / drain electrodes 260 and 265. The insulating layers 130 may include oxides, such as silicon oxide.

[0036] A separator layer 150 may be formed on the etch stop layer 120 and may separate structures, each of which may include a gate electrode 250, a gate insulating pattern 190, a channel 180, source / drain electrodes 260 and 265, a barrier pattern 230, and an insulating layer 130. Thus, multiple structures may be spaced apart from each other in each of the first direction D1 and the second direction D2. The separator layer 150 may include an oxide, such as silicon oxide, and therefore may be incorporated with the insulating layer 130 in some example embodiments.

[0037] In some example embodiments, a plurality of first contact plugs 280 may be spaced apart from each other on the gate electrode 250 in a first direction D1. However, the inventive concept is not limited thereto. In some example embodiments, only one first contact plug 280 may be on the gate electrode 250. Additionally, a plurality of second contact plugs 290 may be spaced apart from each other on the source / drain electrode 260 in a second direction D2, and a plurality of third contact plugs 295 may be spaced apart from each other on the source / drain electrode 265 in the second direction D2, as shown below. Figure 1 The best view is shown in the middle. However, the inventive concept is not limited thereto. Each of the first to third contact plugs 280, 290 and 295 may include a metal, a metal nitride, a metal silicide, doped polysilicon, etc.

[0038] In an example embodiment, the third distance S3 between the first contact plug 280 and each of the second and third contact plugs 290 and 295 in the first direction D1 can be greater than the minimum distance between the gate electrode 250 and each of the source / drain electrodes 260 and 265 in the first direction D1, i.e., the first distance S1. Furthermore, the third distance S3 can be greater than the maximum distance between the gate electrode 250 and each of the source / drain electrodes 260 and 265 in the first direction D1, i.e., the second distance S2. In some example embodiments, as described above, the plurality of first contact plugs 280 can be spaced apart from each other on the gate electrode 250 in the first direction D1. In this case, the third distance S3 can be from the outermost first contact plug 280 to each of the second and third contact plugs 290 and 295.

[0039] The first wiring 310 may extend in the first direction D1 and may commonly contact the first contact plugs 280 spaced apart from each other in the first direction D1 on the gate electrode 250. Each of the second and third wirings 320 and 325 may respectively commonly contact the second and third contact plugs 290 and 295, and each of the second and third contact plugs 290 and 295 may be spaced apart from each other in the second direction D2 on a corresponding one of the source / drain electrodes 260 and 265. That is, the second wiring 320 may commonly contact the second contact plug 290, and the third wiring 325 may commonly contact the third contact plug 295.

[0040] Each of the first to third wirings 310, 320 and 325 may include a metal, a metal nitride, a metal silicide, doped polysilicon, etc.

[0041] As described above, each of the source / drain electrodes 260 and 265 may include a vertical portion extending in the third direction D3 and a horizontal portion extending in the horizontal direction from its vertical portion, and the minimum distance from the gate electrode 250 to each of the source / drain electrodes 260 and 265 (which may be a first distance S1 from the gate electrode 250 to the horizontal portion of each of the drain electrodes 260 and 265) may be less than a second distance S2 from the gate electrode 250 to the vertical portion of each of the drain electrodes 260 and 265.

[0042] Because of the insulating layer 130, the second portion of the channel 180 between the vertical portions of the gate electrode 250 and each of the source / drain electrodes 260 and 265 can be excluded from use as a channel, and only the first portion of the channel 180 between the horizontal portions of the gate electrode 250 and each of the source / drain electrodes 260 and 265 can be used as a channel. Therefore, in a transistor comprising the gate electrode 250, the channel 180, and the source / drain electrodes 260 and 265, the distance between the gate electrode 250 and each of the source / drain electrodes 260 and 265 (with the first portion of the channel 180 between them) can be small, allowing the transistor to have increased on-current and enhanced performance and subthreshold swing characteristics.

[0043] Specifically, when channel 180 comprises an oxide semiconductor, compared to channels comprising, for example, silicon, channel 180 can have lower cutoff current and lower on-current due to its lower mobility. However, compared to channels not comprising, such as... Figure 1 Compared to related technology transistors with gate electrode 250, channel 180, and source / drain electrodes 260 and 265 configured in the middle, the channel 180, which includes oxide semiconductor, can have increased on-current because the distance between the gate electrode 250 and each of the source / drain electrodes 260 and 265 is small.

[0044] Furthermore, the plurality of first portions of channel 180 may be spaced apart from each other on the third-direction D3, and the plurality of horizontal portions of each of source / drain electrodes 260 and 265 may be spaced apart from each other on the third-direction D3, thus unlike those not included... Figure 1-2 Compared to the related technology transistors with gate electrode 250, channel 180, and source / drain electrodes 260 and 265 configured in the middle, the width of the first portion of the channel 180 (which can be disposed between the gate electrode 250 and each of the source / drain electrodes 260 and 265 and used as an active channel) on the third direction D3 can be increased, thereby enhancing the aforementioned effect.

[0045] The third distance S3 between the outermost of the first contact plugs 280 on the gate electrode 250 and each of the second and third contact plugs 290 and 295 on the corresponding one of the source / drain electrodes 260 and 265 can be greater than the first distance S1 (which can be the minimum distance between the gate electrode 250 and each of the source / drain electrodes 260 and 265), and further can be greater than the second distance S2 between them. Therefore, with respect to distances not including those in… Figure 1-2 Compared to the related technology transistors with gate electrode 250, channel 180, and source / drain electrodes 260 and 265 configured in the middle, the parasitic capacitance between the first contact plug 280 and each of the second and third contact plugs 290 and 295 can be reduced, and the first insulating interlayer 270 between them can be prevented from being damaged by breakdown voltage (BV).

[0046] Figures 3 to 21 These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. Specifically, Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 18 and Figure 20 It's a floor plan. Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16-17 , Figure 19 and Figure 21 These are cross-sectional views taken along line A-A' in their respective planar diagrams.

[0047] Reference Figure 3 and Figure 4The pad layer 110 and the etch stop layer 120 can be sequentially stacked on the substrate 100, and the insulating layer 130 and the first sacrificial layer 140 can be alternately and repeatedly stacked on the etch stop layer 120 to form a mold layer including a plurality of insulating layers 130 and a plurality of first sacrificial layers 140.

[0048] The insulating layer 130 may include an oxide, such as silicon oxide, the first sacrificial layer 140 may include a material that is etch-selective with respect to the insulating layer 130, such as a silicon nitride nitride, silicon germanium, polysilicon, etc., and the etch stop layer 120 may include a material that is etch-selective with respect to the insulating layer 130 and the first sacrificial layer 140, such as a metal oxide, such as aluminum oxide.

[0049] Reference Figure 5 and Figure 6 The mold layer can be partially etched to form a first opening that exposes the upper surface of the etch stop layer 120, and the separator layer 150 can be formed in the first opening.

[0050] The separator layer 150 may include oxides, such as silicon oxide, and therefore, in some embodiments, may be incorporated with the insulating layer 130.

[0051] When the separator layer 150 is formed, the mold layer, including the insulating layer 130 and the first sacrificial layer 140, can be divided into a plurality of molds spaced apart from each other in each of the first direction D1 and the second direction D2. In an example embodiment, each mold can extend in the first direction D1.

[0052] Reference Figure 7 and Figure 8 Each mold can be partially etched to form a second opening 160 that exposes the upper surface of the etch stop layer 120.

[0053] In an example embodiment, a plurality of second openings 160 may be formed to be spaced apart from each other at the center portion of each mold in the first direction D1, and Figure 7 Two second openings 160 in each mold are shown. However, in some embodiments, only one second opening 160 may be formed in each mold.

[0054] In the example implementation, each second opening 160 may extend in the first direction D1.

[0055] Reference Figure 9 and Figure 10 The portion of each first sacrificial layer 140 adjacent to the second opening 160 can be removed to form a first groove 170 adjacent to the second opening in each first sacrificial layer 140.

[0056] In an example embodiment, the first groove 170 can be formed by a wet etching process, so the upper part of the uppermost of the first sacrificial layers 140 can also be removed. The first groove 170 can be connected to the second opening 160, and the first groove 170 between adjacent insulating layers 130 in the third direction D3 can have a width W in the first direction D1 from the sidewall of the second opening 160.

[0057] In an example embodiment, a portion of each first sacrificial layer 140 between the second openings 160 spaced apart in the second direction D2 can be completely removed from each mold. However, the inventive concept is not limited thereto, and in some example embodiments, if the distance between the second openings 160 spaced apart in the second direction D2 is large, the portion of each first sacrificial layer 140 between the second openings 160 may not be completely removed but may be partially retained.

[0058] Reference Figure 11 and Figure 12 The channel layer can be formed on the etch stop layer 120, the first sacrificial layer 140, the insulating layer 130 and the separator layer 150 to fill the first groove 170. The gate insulating layer can be formed on the channel layer, and a second sacrificial layer can be formed to fill the second opening 160.

[0059] The second sacrificial layer may include a material that is etch-selective relative to the insulating layer 130, the first sacrificial layer 140, and the separating layer 150, such as polysilicon.

[0060] The second sacrificial layer, gate insulating layer, and channel layer can be planarized until the upper surface of the uppermost of the insulating layer 130 and the separator layer 150 is exposed. Therefore, a channel 180 can be formed that fills the first recess 170 and contacts the sidewalls of the insulating layer 130 and the first sacrificial layer 140, as well as the upper surface of the etch stop layer 120. Additionally, a gate insulating pattern 190 can be formed on the channel 180, and a second sacrificial pattern 200 filling the second opening 160 can be formed on the gate insulating pattern 190.

[0061] Planarization processes can be performed, for example, by chemical mechanical polishing (CMP) and / or etch-back processes.

[0062] The thickness T of the channel 180 between the insulating layers 130 stacked on the third direction D3 can be proportional to the width W of the first groove 170 in the first direction D1, which can be referenced by a reference figure. Figure 9 and Figure 10 The process shown is such that the thickness T of the channel 180 in the first direction D1 can be adjusted by controlling the wet etching process used to form the first groove 170.

[0063] refer to Figure 13 and Figure 14 Each mold can be partially etched to form a third opening 210 that exposes the upper surface of the etch stop layer 120.

[0064] In an example embodiment, a third opening 210 may be formed on each opposite side of the second sacrificial pattern 200 in the first direction D1. Therefore, the insulating layer 130 and the first sacrificial layer 140 in each mold may be partially exposed by the third opening 210.

[0065] Reference Figure 15 and Figure 16 The first sacrificial layer 140 exposed by the third opening 210 can be removed, and a second groove 220 can be formed between adjacent insulating layers 130 in the insulating layers 130 stacked along the third direction D3.

[0066] In the example embodiment, the second groove 220 can be formed by a wet etching process. With the formation of the second groove 220, the outer walls of the channel 180, the sidewalls of the separator layer 150, and the lower and upper surfaces of each insulating layer 130 can be exposed.

[0067] Reference Figure 17 A blocking pattern 230 can be formed on the upper surface of the etch stop layer 120 exposed by the third opening 210 and the second groove 220, as well as on the sidewalls and lower and upper surfaces of each insulating layer 130 and the sidewalls of the separating layer 150.

[0068] The barrier pattern 230 can be formed by forming a barrier layer on the upper surface of the etch stop layer 120 exposed by the third opening 210 and the second groove 220, as well as the sidewalls, lower and upper surfaces of each insulating layer 130, and the sidewalls and upper surfaces of the separator layer 150, the channel 180, the gate insulating pattern 190 and the second sacrificial pattern 200, and removing portions of the barrier layer on the upper surfaces of the separator layer 150, the channel 180, the gate insulating pattern 190 and the second sacrificial pattern 200, and portions of the barrier layer on the uppermost upper surface of the insulating layer 130.

[0069] The second sacrificial pattern 200 can be removed to form the fourth opening 240, thus exposing the upper surface of the gate insulating pattern 190.

[0070] Reference Figure 18 and Figure 19 It can form a gate electrode 250 that fills the fourth opening 210 and source / drain electrodes 260 and 265 that fill the third opening 210 and the second groove 220.

[0071] The gate electrode 250 and source / drain electrodes 260 and 265 can be formed by forming a conductive layer on the gate insulating pattern 190, the barrier pattern 230, the uppermost of the insulating layer 130, the separator layer 150 and the channel 180 to fill the third opening 210 and the fourth opening 240 and the second groove 220, and planarizing the conductive layer until the upper surface of the uppermost of the insulating layer 130 and the upper surface of the separator layer 150 are exposed.

[0072] Each of the source / drain electrodes 260 and 265, and the blocking pattern 230 covering the sidewalls and lower surface of each of the source / drain electrodes 260 and 265, can form a source / drain electrode structure.

[0073] Reference Figure 20 and Figure 21 The first insulating interlayer 270 can be formed on the gate electrode 250, the source / drain electrodes 260 and 265, the uppermost one of the insulating layers 130, the separator layer 150, the channel 180, the gate insulating pattern 190 and the barrier pattern 230, and the first to third contact plugs 280, 290 and 295 can be formed to contact the upper surfaces of the gate electrode 250 and the source / drain electrodes 260 and 265, respectively.

[0074] In an example implementation, one or more first contact plugs 280 may be formed on each gate electrode 250. Figure 21 The diagram shows five first contact plugs 280 spaced apart from each other in the first direction D1. However, the inventive concept is not limited thereto.

[0075] In an example implementation, one or more second contact plugs 290 may be formed on the source / drain electrode 260 and one or more third contact plugs 295 may be formed on the source / drain electrode 265. Figure 21 The diagram shows three second contact plugs 290 spaced apart from each other in the second direction D2 and three third contact plugs 295 spaced apart from each other in the second direction D2. However, the inventive concept is not limited thereto.

[0076] Refer again Figure 1 and Figure 2 A second insulating layer 300 can be formed on the first insulating layer 270 and the first to third contact plugs 280, 290 and 295, and the first, second and third wirings 310, 320 and 325 can be formed to contact the upper surfaces of the first to third contact plugs 280, 290 and 295 respectively.

[0077] In an example implementation, the first wiring 310 may extend in a first direction D1 to contact the upper surface of the first contact plug 280, the second wiring 320 may extend in a second direction D2 to contact the upper surface of the second contact plug 290, and the third wiring 325 may extend in a second direction D2 to contact the upper surface of the third contact plug 295.

[0078] Semiconductor devices can be manufactured using the above processes.

[0079] As described above, each of the molds comprising alternating stacked insulating layers 130 and a first sacrificial layer 140 can be partially etched to form a second opening 160. A portion of the first sacrificial layer 140 adjacent to the second opening 160 can be removed to form a first recess 170. A channel 180 can be formed to fill the first recess 170, and a second sacrificial pattern 200 can be formed in the second opening 160. Each of the molds spaced apart from the second opening 160 in the first direction D1 can be partially etched to form a third opening 210. The first sacrificial layer 140 can be removed through the third opening 210 to form a second recess 220, and the second sacrificial pattern 200 can be removed to form a fourth opening 240. A gate electrode filling the fourth opening 240, and source / drain electrodes 260 and 265 filling the third opening 210 and the second recess 220, can be formed between the gate electrode 250 and each of the source / drain electrodes 260 and 265.

[0080] The channel 180 may have a thickness T proportional to the width W of the first groove 170 in the first direction D1 (see...). Figure 10 , Figure 12 Therefore, the thickness T of the channel 180 can be adjusted by controlling the etching process used to form the first groove 170.

[0081] Figure 22 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. In addition to the source / drain electrode structure, the semiconductor device can be coupled with… Figure 1 and Figure 2 The semiconductor devices are essentially the same or similar. Therefore, the same reference numerals refer to the same elements, and their detailed descriptions are omitted here for brevity.

[0082] Reference Figure 22 The blocking pattern 230 may not contact the upper surface of the etch stop layer 120, so the lower surface of each of the source / drain electrodes 260 and 265 may contact the upper surface of the etch stop layer 120. That is, the blocking pattern 230 of each of the source / drain electrode structures may only cover the sidewalls of each of the source / drain electrodes 260 and 265, but may not cover the lower surface of each of the source / drain electrodes 260 and 265.

[0083] For reference Figure 17 As shown, during the formation of the barrier pattern 230, when a portion of the barrier layer on the upper surface of the separator layer 150, the channel 180, the gate insulating pattern 190, the second sacrificial layer 200, and the uppermost of the insulating layer 130 is removed, a portion of the barrier layer on the upper surface of the etch stop layer 120 can also be removed, so that the barrier pattern 230 does not cover the lower surface of each of the source / drain electrodes 260 and 265.

[0084] Figure 23 This is a cross-sectional view illustrating a semiconductor device according to an example embodiment. Apart from the gate electrode, gate insulating pattern, and channel, the semiconductor device can be... Figure 1 and Figure 2 The semiconductor devices are essentially the same or similar. Therefore, the same reference numerals refer to the same elements, and detailed descriptions of them are omitted here for brevity.

[0085] Reference Figure 23 The channel 180 and the gate insulating pattern 190 may not be formed on the upper surface of the etch stop layer 120, so the lower surface of the gate electrode 250 can contact the upper surface of the etch stop layer 120.

[0086] For reference Figure 11 and Figure 12 As shown, after forming a channel layer on the etch stop layer 120, the first sacrificial layer 140, the insulating layer 130, and the separator layer 150 to fill the first recess 170, and after conformally forming a gate insulating layer on the channel layer, before forming a second sacrificial layer to fill the second opening 160, the uppermost portion of the gate insulating layer and the channel layer on the etch stop layer 120, the insulating layer 130, and the portion on the separator layer 150 can be removed, so that the channel 180 and the gate insulating pattern 190 can not be formed on the upper surface of the etch stop layer 120.

[0087] Therefore, the gate insulating layer and the channel layer can be transformed into gate insulating patterns 190 and 180, respectively, and the second sacrificial layer can be planarized until the uppermost one of the insulating layers 130 and the separator layer 150 are exposed to form the second sacrificial pattern 200.

[0088] Figure 24 and Figure 25 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. The method may include, as referenced... Figures 3 to 21 as well as Figure 1 and Figure 2 The processes shown are basically the same or similar, so for the sake of brevity, repeated explanations are omitted here.

[0089] refer to Figure 24 It can be executed and referenced. Figures 3 to 12 The processes shown are substantially the same or similar, and a capping layer 350 can be formed on the mold, separator layer 150, channel 180, gate insulating pattern 190 and second sacrificial pattern 200.

[0090] The capping layer 350 may include a material that has etch selectivity relative to the first sacrificial layer 140 and the separating layer 150, such as a metal oxide, like aluminum oxide.

[0091] Reference Figure 25 It can be executed and referenced. Figures 13 to 16 The processes shown are basically the same or similar.

[0092] Therefore, each of the molds can be partially etched to form a third opening 210 that exposes the upper surface of the etch stop layer 120, and the first sacrificial layer 140 can be removed through the third opening 210 to form the second groove 220.

[0093] Because a capping layer 350, comprising a material having etch selectivity relative to the first sacrificial layer 140 and the separator layer 150, has been formed on the mold, the separator layer 150, the channel 180, the gate insulating pattern 190, and the second sacrificial pattern 200, the second sacrificial pattern 200 can be covered by the capping layer 350 without being removed when the third opening 210 and the second recess 220 are formed. Therefore, with Figure 11 and Figure 12 Unlike the first sacrificial layer 140, the second sacrificial pattern 200 may not have etch selectivity relative to the first sacrificial layer 140 and may only have etch selectivity relative to the insulating layer 130 and the separator layer 150. That is, the second sacrificial pattern 200 may include a material with etch selectivity relative to the insulating layer 130 and the separator layer 150, such as polysilicon or silicon nitride.

[0094] Executable and referenced Figures 17 to 21 as well as Figure 1 and Figure 2 The processes shown are essentially the same or similar to those used to manufacture semiconductor devices.

[0095] Figures 26 to 28 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. The method may include, as referenced... Figures 3 to 21 as well as Figure 1 and Figure 2 The processes shown are basically the same or similar, so for the sake of brevity, repeated explanations are omitted here.

[0096] Reference Figure 26 It can be executed and referenced. Figures 3 to 10The processes shown are substantially the same or similar, and a second sacrificial pattern 200 can be formed to fill the first groove 170 and the second opening 160.

[0097] Reference Figure 27 It can be executed and referenced. Figures 13 to 17 The processes shown are substantially the same or similar, so that a third opening 210 and a second groove 220 can be formed in each mold, and a blocking pattern 230 can be formed on the upper surface of the etch stop layer 120 exposed by the third opening 210 and the second groove 220, as well as on the sidewalls, lower surface, and upper surface of each of the insulating layers 130.

[0098] However, after forming the blocking pattern 230, the second sacrificial pattern 200 may not need to be removed.

[0099] Executable and referenced Figure 18 and Figure 19 The processes shown are substantially the same or similar, so that source / drain electrodes 260 and 265 can be formed on the blocking pattern 230 to fill the third opening 210 and the second groove 220, and the gate electrode 250 can be omitted because the second sacrificial pattern 200 is not removed.

[0100] Reference Figure 28 After removing the second sacrificial pattern 200 to form the fourth opening 240, the process can be performed in accordance with the reference. Figure 11 and Figure 12 The processes shown are substantially the same or similar, such that a channel layer can be formed on the etch stop layer 120, the first sacrificial layer 140, the insulating layer 130 and the separator layer 150 to fill the first recess 170, and a gate insulating layer can be conformally formed on the channel layer.

[0101] However, the second sacrificial layer may not be formed on the fourth opening 240, and the conductive layer may be formed on the gate insulating layer to fill the fourth opening 240.

[0102] The conductive layer, gate insulating layer, and channel layer can be planarized until the upper surface of the uppermost one of the insulating layers 130 and the upper surface of the separator layer 150 are exposed, such that the channel 180 filling the first recess 170 can be formed to contact the sidewalls of the insulating layer 130 and the barrier pattern 230 and the upper surface of the etch stop layer 120, the gate insulating pattern 190 can be formed on the channel 180, and the gate electrode 250 filling the fourth opening 240 can be formed on the gate insulating pattern 190.

[0103] In the example implementation, the channel 180 can be formed after the barrier pattern 230 and the source / drain electrodes 260 and 265 are formed, so that the characteristics of the channel 180 are not degraded by the heat treatment used to form the barrier pattern 230 and the source / drain electrodes 260 and 265.

[0104] Executable and referenceable Figure 20 as well as Figure 1 and Figure 2 The processes shown are essentially the same or similar to those used to manufacture semiconductor devices.

[0105] While exemplary embodiments have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made without departing from the spirit and scope of the appended claims.

[0106] This application claims priority to Korean Patent Application No. 10-2020-0091624, filed on July 23, 2020 with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device comprising: a gate electrode over a substrate; a channel over the substrate, the channel surrounding sidewalls of the gate electrode; source / drain electrodes over the substrate on opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate; and a barrier pattern over sidewalls and a lower surface of the source / drain electrodes, wherein a thickness of the channel in a horizontal direction from the gate electrode to the source / drain electrodes is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate, wherein the source / drain electrodes and the barrier pattern form a source / drain electrode structure, and wherein a first portion of the channel has a greater thickness in the first direction than a second portion of the channel, and the first portion of the channel is in contact with the source / drain electrode structure and the second portion of the channel is not in contact with the source / drain electrode structure.

2. The semiconductor device according to claim 1, wherein each of the source / drain electrodes comprises: a vertical portion extending in the vertical direction; and a horizontal portion extending in the horizontal direction from the vertical portion, and wherein the first portion of the channel faces the horizontal portion of each of the source / drain electrodes and the second portion of the channel faces the vertical portion of each of the source / drain electrodes.

3. The semiconductor device according to claim 2, wherein the horizontal portion of each of the source / drain electrodes is one of a plurality of horizontal portions spaced apart from each other in the vertical direction, and wherein the channel comprises a plurality of first portions and a plurality of second portions alternately stacked in the vertical direction.

4. The semiconductor device according to claim 3, further comprising an insulating layer between the vertical portion of each of the source / drain electrodes and the plurality of second portions of the channel.

5. The semiconductor device according to claim 1, wherein the channel comprises an oxide semiconductor.

6. The semiconductor device according to claim 5, wherein the channel comprises barium tin oxide (BaSn03), zinc oxide (ZnO), laminated lanthanum aluminate / srtontium titanate (LaAl03 / SrTi03), gallium oxide (Ga203), tin oxide (Sn02), indium oxide (In203), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium tin oxide (ITO), indium tungsten tin oxide (IWZO), and / or indium zinc oxide (IZO).

7. The semiconductor device according to claim 1, wherein the channel comprises amorphous silicon, polysilicon, single crystal silicon, or silicon germanium.

8. The semiconductor device according to claim 1, wherein the channel contacts the barrier pattern.

9. The semiconductor device according to claim 1, wherein the gate electrode is one of a plurality of gate electrodes spaced apart from each other in a second direction between the source / drain electrodes, and ​ ​ wherein the second direction is parallel to the upper surface of the substrate and perpendicular to the first direction.

10. The semiconductor device according to claim 9, wherein the trench is one of a plurality of trenches respectively surrounding sidewalls of the plurality of gate electrodes, and wherein the plurality of trenches are connected to each other between the plurality of gate electrodes.

11. The semiconductor device according to claim 1, further comprising: a first contact plug on the gate electrode; and a second contact plug and a third contact plug respectively on the source / drain electrodes, wherein a contact plug distance between the first contact plug and each of the second contact plug and the third contact plug is greater than a minimum distance between the gate electrode and each of the source / drain electrodes.

12. The semiconductor device according to claim 11, wherein the first contact plug is one of a plurality of first contact plugs spaced apart from each other in the first direction on the gate electrode, wherein the second contact plug is one of a plurality of second contact plugs spaced apart from each other in a second direction on a first one of the source / drain electrodes, and the third contact plug is one of a plurality of third contact plugs spaced apart from each other in the second direction on a second one of the source / drain electrodes, the contact plug distance is between an outermost one of the plurality of first contact plugs and each of the second contact plug and the third contact plug, and wherein the second direction is parallel to the upper surface of the substrate and perpendicular to the first direction.

13. The semiconductor device according to claim 12, further comprising: a first wiring extending in the first direction and commonly contacting upper surfaces of the plurality of first contact plugs; a second wiring extending in the second direction and commonly contacting upper surfaces of the plurality of second contact plugs; and a third wiring extending in the second direction and commonly contacting upper surfaces of the plurality of third contact plugs.

14. A semiconductor device comprising: a gate electrode on a substrate; a trench on the substrate, the trench surrounding a sidewall of the gate electrode; a source / drain electrode on the substrate on an opposite side of the gate electrode in a first direction parallel to an upper surface of the substrate; and a barrier pattern on sidewalls and a lower surface of the source / drain electrode, wherein a distance between the gate electrode and each of the source / drain electrodes in the first direction is not constant but varies in a perpendicular direction perpendicular to the upper surface of the substrate, wherein the source / drain electrode and the barrier pattern form a source / drain electrode structure, and wherein a first portion of the trench has a thickness in the first direction that is greater than a thickness in the first direction of a second portion of the trench, and the first portion of the trench is in contact with the source / drain electrode structure and the second portion of the trench is not in contact with the source / drain electrode structure.

15. The semiconductor device according to claim 14, wherein each of the source / drain electrodes comprises: a perpendicular portion extending in the perpendicular direction; and a horizontal portion extending in the first direction. ​ ​ a horizontal portion extending from the vertical portion in a horizontal direction parallel to the upper surface of the substrate, and wherein a distance between the gate electrode and the vertical portion of each of the source / drain electrodes in the first direction is larger than a distance between the gate electrode and the horizontal portion of each of the source / drain electrodes in the first direction.

16. The semiconductor device according to claim 15, wherein the horizontal portion of each of the source / drain electrodes is one of a plurality of horizontal portions spaced apart from each other in the vertical direction, and wherein a distance between the gate electrode and each of the source / drain electrodes in the first direction periodically increases and decreases.

17. The semiconductor device according to claim 15, wherein the channel includes a plurality of first portions and a plurality of second portions alternately stacked in the vertical direction, each of the plurality of first portions having a relatively large thickness in the horizontal direction, each of the plurality of second portions having a relatively small thickness in the horizontal direction.

18. The semiconductor device according to claim 17, wherein each of the plurality of first portions faces the horizontal portion of each of the source / drain electrodes in the first direction, and each of the plurality of second portions faces the vertical portion of each of the source / drain electrodes in the first direction.

19. The semiconductor device according to claim 14, further comprising: a first contact plug on the gate electrode; and a second contact plug and a third contact plug on the source / drain electrodes, respectively, wherein a distance between the first contact plug and each of the second contact plug and the third contact plug in the first direction is larger than a minimum distance between the gate electrode and each of the source / drain electrodes in the first direction.

20. A semiconductor device comprising: a gate electrode on a substrate; a channel on the substrate, the channel surrounding a sidewall of the gate electrode; source / drain electrodes on the substrate on opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate; a first contact plug on the gate electrode; a second contact plug and a third contact plug on the source / drain electrodes, respectively; and first to third wirings contacting upper surfaces of the first to third contact plugs, respectively, wherein a thickness of the channel between the gate electrode and the source / drain electrodes in a horizontal direction is not constant but varies in a vertical direction, and a thickness of each of the source / drain electrodes in the horizontal direction is not constant but varies in the vertical direction, the horizontal direction being parallel to the upper surface of the substrate, the vertical direction being perpendicular to the upper surface of the substrate, and wherein a distance between the first contact plug and each of the second contact plug and the third contact plug in the horizontal direction is larger than a minimum distance between the gate electrode and each of the source / drain electrodes in the horizontal direction.

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