Light emitting element, method of manufacturing light emitting element, and display device

Abstract

A light-emitting element, a method for manufacturing a light-emitting element, and a display device including a light-emitting element are provided. The light-emitting element includes a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer; an electrode layer provided over the second semiconductor layer; an insulating structure provided over the electrode layer and having a maximum diameter smaller than a diameter of the electrode layer; and an insulating film surrounding side surfaces of the first semiconductor layer, side surfaces of the light-emitting layer, and side surfaces of the second semiconductor layer.

Description

Technical Field

[0001] The embodiments relate to a light-emitting element, a method for manufacturing a light-emitting element, and a display device. Background Technology

[0002] With the development of multimedia technology, display devices have become increasingly important. Various display devices, such as organic light-emitting diode (OLED) displays, liquid crystal displays (LCDs), and similar devices, are being used.

[0003] Typical display devices include display panels such as organic light-emitting display panels or liquid crystal display (LCD) panels. Light-emitting display panels may include light-emitting elements. For example, light-emitting diodes (LEDs) include organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic LEDs that use inorganic materials as fluorescent materials. Summary of the Invention

[0004] The embodiments provide a light-emitting element that minimizes damage to the electrode layer and a method for manufacturing the light-emitting element.

[0005] The embodiment also provides a display device that has improved brightness by including a light-emitting element that minimizes damage to the electrode layer.

[0006] However, the embodiments are not limited to those described herein. The above and other embodiments will become clearer to those skilled in the art from the following detailed description of the disclosure.

[0007] According to an embodiment, the light-emitting element may include: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; an electrode layer disposed on the second semiconductor layer; an insulating structure disposed on the electrode layer and having a maximum diameter smaller than the diameter of the electrode layer; and an insulating film surrounding the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

[0008] The insulating structure may include: a bottom surface, a contact electrode layer, and inclined side surfaces relative to the bottom surface. The diameter of the insulating structure may decrease from the bottom surface to the top.

[0009] The height of the insulating structure can range from about 500 nm to about 1 μm.

[0010] The maximum diameter of the insulating structure can range from about 100 nm to about 500 nm.

[0011] The insulating structure may include a first part and a second part. The first part may have the maximum diameter (or width) of the insulating structure, and the first part may include inclined side surfaces. The second part may be connected to the lower part of the first part and has a width smaller than the maximum diameter of the insulating structure.

[0012] The insulating structure may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the insulating film may be a single layer or multiple layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, zirconium oxide, and hafnium oxide.

[0013] The thickness of the insulating film can range from about 10 nm to about 200 nm.

[0014] The light-emitting element may further include: a third semiconductor layer disposed between the first semiconductor layer and the light-emitting layer; a fourth semiconductor layer disposed between the second semiconductor layer and the light-emitting layer; and a fifth semiconductor layer disposed between the second semiconductor layer and the fourth semiconductor layer, wherein the insulating film may also surround the side surfaces of the third semiconductor layer, the fourth semiconductor layer and the fifth semiconductor layer.

[0015] According to an embodiment, a method for manufacturing a light-emitting element may include the following steps: forming a semiconductor structure on a target substrate, the semiconductor structure including a plurality of semiconductor material layers; forming a mask layer on the semiconductor structure; etching the semiconductor structure in a direction perpendicular to the top surface of the target substrate to form an element rod, each element rod including an insulating structure and a plurality of semiconductor layers, the insulating structure being formed by a portion of the mask layer; forming an insulating film surrounding a portion of the side surface of the element rod; and separating the element rod from the insulating film from the target substrate.

[0016] The steps of forming a mask layer may include: forming an insulating mask layer on a semiconductor structure; and forming a metal pattern layer on the insulating mask layer, the metal pattern layer comprising patterns spaced apart from each other, and the insulating structure may be formed by etching the insulating mask layer.

[0017] The steps of forming a component bar may include performing a first etching step and performing a second etching step. The first etching step may include etching an insulating mask layer along a metal pattern layer to form a hard mask layer; and etching a semiconductor structure along the hard mask layer. The second etching step may include etching the semiconductor structure etched along the hard mask layer to form a component bar including an insulating structure.

[0018] The first etching step may include a dry etching process, and the second etching step may include a wet etching process.

[0019] The semiconductor structure can be etched to have exposed and tilted side surfaces by a first etching step, and the semiconductor layer of the element rod can be formed to have side surfaces perpendicular to the target substrate.

[0020] The component rod may include: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; and an electrode layer disposed on the second semiconductor layer. An insulating structure may be formed on the electrode layer, and an insulating film may be formed surrounding the side surfaces of the first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the electrode layer.

[0021] The insulating structure can be formed with inclined side surfaces, such that the diameter of the insulating structure decreases from the bottom surface to the top surface of the insulating structure.

[0022] According to an embodiment, the display device may include: a first substrate; a first electrode disposed on the first substrate; a second electrode disposed on the first substrate and spaced apart from the first electrode; a first insulating layer disposed on the first substrate and covering the first electrode and the second electrode; a plurality of light-emitting elements disposed on the first insulating layer and including a first end disposed on the first electrode and a second end disposed on the second electrode; a first contact electrode electrically contacting the first electrode and the first end of the plurality of light-emitting elements; and a second contact electrode electrically contacting the second electrode and the second end of the plurality of light-emitting elements. Each of the plurality of light-emitting elements includes: a first semiconductor layer doped with an n-type dopant; a second semiconductor layer doped with a p-type dopant; a light-emitting layer disposed between the first semiconductor layer and the second semiconductor layer; an electrode layer disposed on the second semiconductor layer; an insulating structure disposed on the electrode layer and having a maximum diameter smaller than the diameter of the electrode layer; and an insulating film surrounding the side surface of the first semiconductor layer, the side surface of the light-emitting layer, and the side surface of the second semiconductor layer.

[0023] The insulating structure may include a bottom surface and inclined side surfaces, and the diameter of the insulating structure may decrease from the bottom surface to the top.

[0024] The insulating structure may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0025] The display device may further include: a first contact surface, a portion of the top surface of the electrode layer and the first contact electrode contacting each other at the first contact surface; a second contact surface, a portion of the side surface of the insulating structure and the first contact electrode contacting each other at the second contact surface; and a third contact surface, a bottom surface of the first semiconductor layer and the second contact electrode contacting each other at the third contact surface, wherein the first contact surface may be smaller than the third contact surface.

[0026] The space can be formed between the insulating structure of each of the multiple light-emitting elements and the first insulating layer, and the electrode layer can include a surface adjacent to the space but not in contact with the first contact electrode.

[0027] According to the above and other embodiments, the light-emitting element may include an insulating structure formed by the remainder of the mask layer during the manufacturing of the light-emitting element. Since no chemical processing is required to remove the insulating structure, damage to the electrode layer can be minimized, thereby improving the luminous efficiency and brightness of the light-emitting element.

[0028] Furthermore, since the light-emitting element is included in the display device, the amount of light emitted by each sub-pixel of the display device can be increased.

[0029] Other features and embodiments may become clear from the following detailed description, drawings, and claims. Attached Figure Description

[0030] The above and other embodiments and features will become clearer from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a schematic plan view of a display device according to an embodiment;

[0032] Figure 2 yes Figure 1 A schematic plan view of the pixels of a display device;

[0033] Figure 3 It is along Figure 2 A schematic cross-sectional view taken from lines Q1-Q1′, Q2-Q2′ and Q3-Q3′;

[0034] Figure 4 This is a schematic perspective view of the light-emitting element according to an embodiment;

[0035] Figure 5 yes Figure 4 A schematic top view of the light-emitting element;

[0036] Figure 6 yes Figure 4 A schematic cross-sectional view of the light-emitting element;

[0037] Figure 7 yes Figure 3 An enlarged schematic cross-sectional view of part A;

[0038] Figure 8 schematically shown Figure 3 The contact surface between the first end of the light-emitting element and the first contact electrode;

[0039] Figure 9It shows from Figure 4 An enlarged schematic cross-sectional view of the path of light emitted by the light-emitting element;

[0040] Figure 10 This is a flowchart illustrating a method for manufacturing a light-emitting element according to an embodiment;

[0041] Figures 11 to 18 It is shown Figure 10 A schematic cross-sectional view of the method;

[0042] Figure 19 This is a schematic perspective view of the light-emitting element according to an embodiment;

[0043] Figure 20 yes Figure 19 A schematic cross-sectional view of the light-emitting element; and

[0044] Figure 21 This is a schematic cross-sectional view of the light-emitting element according to an embodiment. Detailed Implementation

[0045] The invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0046] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on said other layer or substrate, or there may be an intermediate layer. Throughout the specification, the same reference numerals indicate the same components.

[0047] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0048] The accompanying drawings and description are intended to be illustrative only and are therefore not intended to limit the embodiments described and claimed herein. In order to describe embodiments of the invention, some parts not directly related to the description may be omitted, and throughout the specification, the same reference numerals refer to the same elements.

[0049] In the accompanying drawings, the dimensions and thicknesses of each element are depicted arbitrarily for better understanding and ease of description; however, the invention is not limited thereto. In the accompanying drawings, the thicknesses of layers, films, panels, regions, and other elements may be exaggerated for clarity. In the accompanying drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0050] In the specification, the phrase "in a plan view" refers to the view of a portion of an object from above, while the phrase "in a sectional view" refers to the view of a section obtained by vertically cutting a portion of an object from the side. Furthermore, the terms "overlapping" or "stacked" indicate that the first object may be above or below the second object, or vice versa.

[0051] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device shown in the drawings is flipped, the device positioned “below” or “under” another device may be “above” the other device. Therefore, the descriptive term “below” can include both a lower and upper position. The device may also be oriented in other directions, and thus the spatial relative terms may be interpreted differently depending on the orientation.

[0052] As used herein, “about” or “approximately” includes the stated value and indicates an acceptable deviation from the particular value as determined by a person skilled in the art, taking into account the measurements discussed and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±80%, ±5% of the stated value.

[0053] Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to another element or “electrically connected” to another element, with one or more intermediate elements placed between them.

[0054] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In the specification and claims, for the purposes of their meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one of the group consisting of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0056] It will also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or combinations thereof.

[0057] In the following description, a display device, a light-emitting element, and a method of manufacturing a light-emitting element according to embodiments will be described with reference to the accompanying drawings.

[0058] Figure 1 This is a schematic plan view of the display device 10 according to an embodiment.

[0059] Reference Figure 1 The display device 10 displays moving or still images. The display device 10 can refer to virtually any type of electronic device that provides a display screen. Examples of display devices 10 may include televisions (TVs), laptop computers, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet PCs, electronic watches, smartwatches, watch phones, head-mounted displays (HMDs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, camcorders, etc.

[0060] Display device 10 includes a display panel that provides a display screen. Examples of display panels for display device 10 include inorganic light-emitting diode (ILED) display panels, organic light-emitting diode (OLED) display panels, quantum dot light-emitting diode (QLED) display panels, plasma display panels (PDP), field emission display (FED) panels, etc. The display panel of display device 10 will be described below as, for example, an ILED display panel, but embodiments are not limited thereto. Various other display panels are also suitable for the display panel of display device 10.

[0061] The shape of the display device 10 can vary. For example, the display device 10 can have a rectangular shape that extends longer in the horizontal direction than in the vertical direction, a rectangular shape that extends longer in the vertical direction than in the horizontal direction, a square shape, a quadrilateral shape with rounded corners, a non-quadrilateral polygonal shape, or a circular shape. The shape of the display area DPA of the display device 10 can be similar to the shape of the display device 10. Figure 1 The display device 10 and the display area DPA are shown to have rectangular shapes that are longer in the horizontal direction (first direction DR1) than in the vertical direction (second direction DR2).

[0062] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an area where an image is displayed, and the non-display area NDA may be an area where no image is displayed. The display area DPA may also be referred to as the active area, and the non-display area NDA may also be referred to as the inactive area. The display area DPA may occupy the middle portion of the display device 10.

[0063] The display area DPA may include multiple pixels PX. Pixels PX may be arranged in both row and column directions. Pixels PX may have a rectangular or square shape in a planar view, but embodiments are not limited thereto. Pixels PX may have a rhombus shape with sides slanted relative to a particular direction. Pixels PX may be arranged alternately in a striped or pentile pattern. Each of the pixels PX may include one or more light-emitting elements 30 (see [link to relevant documentation]) that emit light within a specific wavelength range. Figure 2 ).

[0064] The non-display area NDA can be disposed around the display area DPA. The non-display area NDA can surround the entire display area DPA or a portion of the display area DPA. The display area DPA can have a rectangular shape, and the non-display area NDA can be disposed adjacent to the four sides of the display area DPA. The non-display area NDA can form the bezel of the display device 10. Lines (wiring) or circuit drivers included in the display device 10 can be disposed in the non-display area NDA, or external devices can be mounted in the non-display area NDA.

[0065] Figure 2 yes Figure 1 A schematic plan view of the pixels PX of the display device 10.

[0066] Reference Figure 2A pixel PX may include sub-pixels PXn (where n is an integer from 1 to 3). For example, a pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may emit light of a first color, a second color, and a third color, respectively. For example, the first color, the second color, and the third color may be blue, green, and red, respectively, but the embodiment is not limited thereto. In another example, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may emit light of the same color. Figure 2 The illustration shows that pixel PX includes three sub-pixels PXn, but the number of sub-pixels PXn in the embodiment is not limited, and pixel PX may include more than three sub-pixels PXn.

[0067] Each of the sub-pixels PXn may include an emitting region EMA and a non-emitting region. The emitting region EMA may be a region in which a light-emitting element 30 is disposed to emit light within a specific wavelength range, and the non-emitting region may be a region in which no light is emitted due to the absence of a light-emitting element 30. The emitting region EMA may include a region in which a light-emitting element 30 is disposed and an area around the light-emitting element 30 from which light emitted by the light-emitting element 30 is emitted.

[0068] However, the embodiments are not limited to this. The emission region EMA may also include the area from which light emitted by the light-emitting element 30 is output and then reflected or refracted by other components. A plurality of light-emitting elements 30 may be disposed in each of the sub-pixels PXn to form the emission region EMA.

[0069] Each sub-pixel PXn may further include a cut region CBA disposed in a non-emitting region. The cut region CBA may be disposed on one side of the emitting region EMA in the second direction DR2. The cut region CBA may be disposed between the emitting regions EMA of two adjacent sub-pixels PXn in the second direction DR2. The emitting regions EMA and cut regions CBA may be arranged in the display area DPA of the display device 10. For example, the emitting regions EMA may be arranged in a row in the first direction DR1, the cut regions CBA may be arranged in a row in the first direction DR1, and the emitting regions EMA and cut regions CBA may be arranged alternately in the second direction DR2. The distance between cut regions CBA in the first direction DR1 may be smaller than the distance between emitting regions EMA in the first direction DR1. A second dam BNL2 may be disposed between the cut regions CBA and the emitting regions EMA, and the distances between the cut regions CBA, the emitting regions EMA, and the cut regions CBA and the emitting regions EMA may vary depending on the width of the second dam BNL2. Since the light-emitting element 30 is not disposed in the cut area CBA of each of the sub-pixels PXn, no light is output from the cut area CBA of each of the sub-pixels PXn. Instead, portions of electrodes 21 and 22 may be disposed in the cut area CBA of each of the sub-pixels PXn. Electrodes 21 and 22 may be divided (or separated) in the cut area CBA of each of the sub-pixels PXn.

[0070] Figure 3 It is along Figure 2 The sectional views taken by lines Q1-Q1′, Q2-Q2′ and Q3-Q3′. Figure 3 It shows from Figure 2 A cross-sectional view taken from one end to the other of the light-emitting element 30 in the first sub-pixel PX1.

[0071] Reference Figure 3 and Figure 2 The display device 10 may include a first substrate 11 and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate 11. The semiconductor layer, conductive layers, and insulating layers may form the circuit layer and the light-emitting layer of the display device 10.

[0072] The first substrate 11 may be an insulating substrate. The first substrate 11 may be formed of an insulating material such as glass, quartz, or polymer resin. The first substrate 11 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable.

[0073] A light-blocking layer BML may be disposed on the first substrate 11. The light-blocking layer BML is configured to be stacked with the active layer ACT1 of the first transistor T1. The light-blocking layer BML comprises a material capable of blocking light, thus preventing light from incident on the active layer ACT1 of the first transistor T1. For example, the light-blocking layer BML may be formed of an opaque metallic material capable of blocking light transmission, but the embodiments are not limited thereto. In some embodiments, the light-blocking layer BML may not be disposed.

[0074] The buffer layer 12 may be disposed on the entire surface of the first substrate 11. For example, the buffer layer 12 may be configured to cover the top surface of the first substrate 11. The buffer layer 12 may be formed on the first substrate 11 to protect the first transistor T1 (e.g., to protect the transistor from moisture) and may perform a surface planarization function.

[0075] The active layer ACT1 can be disposed on the buffer layer 12. The active layer ACT1 can be configured to partially overlap with the gate electrode G1 of the first conductive layer, which will be described below.

[0076] Figure 3 Only the first transistor T1, which is included in the first sub-pixel PX1, is shown, but the embodiment is not limited thereto. The display device 10 may include more than one transistor in each of the sub-pixels PXn. For example, the display device 10 may include two or three transistors in each of the sub-pixels PXn.

[0077] The active layer ACT1 may include polycrystalline silicon, monocrystalline silicon, or oxide semiconductors. When the active layer ACT1 includes an oxide semiconductor, it may include multiple conductor regions and channel regions disposed between the conductor regions. The oxide semiconductor may contain indium (In). For example, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0078] In other embodiments, the active layer ACT1 may include polycrystalline silicon, which can be formed by crystallizing amorphous silicon. In this case, the conductive region of the active layer ACT1 may be an impurity-doped region.

[0079] The first gate insulating layer 13 can be disposed on the active layer ACT1 and the buffer layer 12. For example, the first gate insulating layer 13 can be configured to cover the entire surface of the active layer ACT1 and the buffer layer 12. The first gate insulating layer 13 can be used as the gate insulating film of each transistor.

[0080] A first conductive layer is disposed on the first gate insulating layer 13. The first conductive layer may include the gate electrode G1 of the first transistor T1 and the first capacitance electrode CSE1 of the storage capacitor. The gate electrode G1 may be configured to overlap with the channel region of the active layer ACT1 in the thickness direction, said thickness direction being a plane defined by a first direction DR1 and a second direction DR2. Figure 3 The bottom extends to Figure 3 The normal direction at the top. The first capacitor electrode CSE1 can be configured to be stacked with the second capacitor electrode CSE2, which will be described below, in the thickness direction. For example, the first capacitor electrode CSE1 can be integrally formed with the gate electrode G1 and electrically connected to the gate electrode G1. The first capacitor electrode CSE1 can be configured to be stacked with the second capacitor electrode CSE2 in the thickness direction, and the storage capacitor can be formed using the first capacitor electrode CSE1 and the second capacitor electrode CSE2.

[0081] The first interlayer insulating layer 15 can be disposed on the first conductive layer. The first interlayer insulating layer 15 can serve as an insulating film between the first conductive layer and the layer disposed on the first conductive layer. The first interlayer insulating layer 15 can be configured to cover and protect the first conductive layer.

[0082] The second conductive layer may be disposed on the first interlayer insulating layer 15. The second conductive layer may include the first source electrode S1 and the first drain electrode D1 of the first transistor T1, the data line DTL, and the second capacitor electrode CSE2.

[0083] The first source electrode S1 and the first drain electrode D1 of the first transistor T1 can contact the doped region of the active layer ACT1 through contact holes penetrating the first interlayer insulating layer 15 and the first gate insulating layer 13. The first source electrode S1 of the first transistor T1 can contact the light blocking layer BML through another contact hole.

[0084] The data line DTL can apply data signals to other transistors (not shown) included in the first sub-pixel PX1. Although not specifically shown, the data line DTL can be electrically connected to the source / drain electrodes of the other transistors included in the first sub-pixel PX1 and transmit data signals to the source / drain electrodes.

[0085] The second capacitor electrode CSE2 can be configured to be stacked on top of the first capacitor electrode CSE1 in the thickness direction. For example, the second capacitor electrode CSE2 can be integrally formed with the first source electrode S1 and electrically connected to the first source electrode S1.

[0086] The second interlayer insulating layer 17 can be disposed on the second conductive layer. The second interlayer insulating layer 17 can serve as an insulating film between the second conductive layer and the layer disposed on the second conductive layer. The second interlayer insulating layer 17 can cover and protect the second conductive layer.

[0087] A third conductive layer is disposed on the second interlayer insulating layer 17. The third conductive layer may include a first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP. A high potential voltage (or a first power supply voltage) supplied to the first transistor T1 may be applied to the first voltage line VL1, and a low potential voltage (or a second power supply voltage) supplied to the second electrode 22 may be applied to the second voltage line VL2. Furthermore, an alignment signal for aligning the light-emitting element 30 during the manufacture of the display device 10 may be applied to the second voltage line VL2.

[0088] The first conductive pattern CDP can be electrically connected to the second capacitor electrode CSE2 through contact holes formed in the second interlayer insulating layer 17. The second capacitor electrode CSE2 can be integrally formed with the first source electrode S1 of the first transistor T1, and the first conductive pattern CDP can be electrically connected to the first source electrode S1. The first conductive pattern CDP can contact the first electrode 21, which will be described later, and the first transistor T1 can transmit a first power supply voltage applied from the first voltage line VL1 to the first electrode 21 via the first conductive pattern CDP. The third conductive layer is shown as including a first voltage line VL1 and a second voltage line VL2, but the embodiment is not limited thereto. The third conductive layer may include more than one first voltage line VL1 and more than one second voltage line VL2.

[0089] Each of the buffer layer 12, the first gate insulating layer 13, the first interlayer insulating layer 15, and the second interlayer insulating layer 17 may be composed of a plurality of alternately stacked inorganic films. For example, each of the buffer layer 12, the first gate insulating layer 13, the first interlayer insulating layer 15, and the second interlayer insulating layer 17 may be formed as a double layer or multiple layers, wherein silicon oxide (SiO2) is included. x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y One or more inorganic layers of at least one of the following are stacked alternately. Each of the buffer layer 12, the first gate insulating layer 13, the first interlayer insulating layer 15, and the second interlayer insulating layer 17 may be formed as a single inorganic layer comprising at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0090] A first planarization layer 19 is disposed on the third conductive layer. The first planarization layer 19 may include an organic insulating material (such as polyimide (PI) as an example) and may perform surface planarization functions.

[0091] A first dam BNL1, multiple electrodes 21 and 22, a light-emitting element 30, multiple contact electrodes CNE1 and CNE2, and a second dam BNL2 are disposed on the first planarization layer 19. Multiple insulating layers PAS1, PAS2, and PAS3 may also be disposed on the first planarization layer 19.

[0092] The first dam, BNL1, can be directly installed on the first planarization layer 19. (Refer to...) Figure 2 and Figure 3 The first dam BNL1 may have a predetermined width in each of the sub-pixels PXn (e.g., the first sub-pixel PX1) and may extend in the second direction DR2. The first dam BNL1 does not extend in the second direction DR2 into adjacent sub-pixels PXn and may be set within the emission region EMA of each sub-pixel PXn. Furthermore, the first dams BNL1 may be set to be spaced apart from each other in the first direction DR1.

[0093] Multiple first dams BNL1 can be set in each of the sub-pixels PXn. Figure 2 The illustration shows two first dams BNL1 disposed in each of the sub-pixels PXn to form a linear pattern in the display area DPA, but the embodiment is not limited thereto. The number of first dams BNL1 disposed in each of the sub-pixels PXn can vary depending on the number of electrodes 21 and 22 in each of the sub-pixels PXn and the arrangement of the light-emitting elements 30, or the shape of the first dams BNL1 can be modified to form an island-shaped pattern in the display area DPA.

[0094] The first dam BNL1 may protrude at least partially from the top surface of the first planarization layer 19. Each of the protruding portions of the first dam BNL1 may have a sloping side surface, and light emitted from the light-emitting element 30 may be reflected by electrodes 21 and 22 disposed on the first dam BNL1 to be emitted in an upward direction from the first planarization layer 19. The first dam BNL1 may provide an area for arranging the light-emitting element 30 and may serve as a reflective wall for upward reflection of light emitted from the light-emitting element 30. The side surfaces of the first dam BNL1 may be linearly sloping (or form bevels), but the embodiments are not limited thereto. The first dam BNL1 may have a semi-circular or semi-elliptical shape with a curved outer surface. The first dam BNL1 may comprise an organic insulating material such as polyimide, but the embodiments are not limited thereto. In other embodiments, the first dam BNL1 may not be provided.

[0095] Electrodes 21 and 22 may extend in one direction and may be disposed in each of the sub-pixels PXn. Electrodes 21 and 22 may extend in a second direction DR2 and may be spaced apart from each other in a first direction DR1. In each of the sub-pixels PXn, for example, in the first sub-pixel PX1, the first electrode 21 and the second electrode 22 may be spaced apart from each other in the first direction DR1, but the embodiment is not limited thereto. The number and position of electrodes 21 and 22 disposed in each of the sub-pixels PXn may vary depending on the number of light-emitting elements 30 disposed in each of the sub-pixels PXn.

[0096] The first electrode 21 and the second electrode 22 can be disposed in the emission region EMA of the first sub-pixel PX1, and can be disposed partially beyond the emission region EMA of the first sub-pixel PX1 to overlap with the second dam BNL2 in the thickness direction. The electrodes 21 and 22 of the first sub-pixel PX1 can extend in the second direction DR2 within the first sub-pixel PX1, and can be spaced apart from the electrodes 21 and 22 of the upper adjacent sub-pixel PXn of the first sub-pixel PX1 in the second direction DR2 in the cutting region CBA of the first sub-pixel PX1.

[0097] The first electrode 21 and the second electrode 22 can extend in the first sub-pixel PX1 along the second direction DR2. The first electrode 21 and the second electrode 22 can be separated from the corresponding first electrode 21 and second electrode 22 of the upper adjacent sub-pixel PXn of the first sub-pixel PX1 along the second direction DR2 within the cut region CBA of the first sub-pixel PX1. For example, the cut region CBA of the first sub-pixel PX1 can be located between the emission region EMA of the first sub-pixel PX1 and the emission region EMA of the upper adjacent sub-pixel PXn of the first sub-pixel PX1 along the second direction DR2. Within the cut region CBA of the first sub-pixel PX1, the first electrode 21 and the second electrode 22 of the first sub-pixel PX1 can be separated from the corresponding first electrode 21 and second electrode 22 of the upper adjacent sub-pixel PXn of the first sub-pixel PX1 along the second direction DR2. However, the embodiments are not limited to this. In other embodiments, electrodes 21 and 22 may extend beyond the first sub-pixel PX1 into other sub-pixels PXn arranged side-by-side with the first sub-pixel PX1 on the second direction DR2 without being divided between different sub-pixels PXn, or only one of the first electrode 21 and the second electrode 22 may be divided between different sub-pixels PXn.

[0098] Electrodes 21 and 22 can be obtained by forming electrode lines extending in the second direction DR2 and cutting the electrode lines after the light-emitting element 30 is arranged. During the manufacture of the display device 10, the electrode lines can be used during the fabrication of the electrode lines to align the light-emitting element 30 by forming an electric field in the first sub-pixel PX1. For example, the light-emitting element 30 can be sprayed onto the electrode lines via inkjet printing, and once the ink including the light-emitting element 30 is sprayed onto the electrode lines, an electric field is formed by applying an alignment signal to the electrode lines. The light-emitting element 30, dispersed in the ink, receives a dielectrophoretic force from the electric field and can therefore be arranged on the electrodes 21 and 22. After the light-emitting element 30 is arranged, the electrode lines are divided into a plurality of electrodes 21 and 22 to be disposed in each of the sub-pixels PXn.

[0099] Electrodes 21 and 22 can be electrically connected to the third conductive layer, allowing signals for emitting light from the light-emitting element 30 to be applied to electrodes 21 and 22. The first electrode 21 can contact the first conductive pattern CDP through a first contact hole CT1 penetrating the first planarization layer 19. The second electrode 22 can contact the second voltage line VL2 through a second contact hole CT2 penetrating the first planarization layer 19. The first electrode 21 can be electrically connected to the first transistor T1 via the first conductive pattern CDP, allowing a first power supply voltage to be applied to the first electrode 21, and the second electrode 22 can be electrically connected to the second voltage line VL2, allowing a second power supply voltage to be applied to the second electrode 22.

[0100] Electrodes 21 and 22 can be electrically connected to the light-emitting element 30. Electrodes 21 and 22 can be electrically connected to the two ends of the light-emitting element 30 via contact electrodes CNE1 and CNE2, and can transmit electrical signals received from the third conductive layer to the light-emitting element 30. Since electrodes 21 and 22 are configured to divide between different sub-pixels PXn, the light-emitting element 30 of one sub-pixel PXn can emit light separately (independently) from the light-emitting element 30 of another sub-pixel PXn.

[0101] The first contact hole CT1 and the second contact hole CT2 are shown to be formed at a location overlapping with the second dam BNL2, but the embodiment is not limited thereto. For example, the first contact hole CT1 and the second contact hole CT2 may be located in the emission region EMA of the first sub-pixel PX1 surrounded by the second dam BNL2.

[0102] Electrodes 21 and 22 may be disposed on a pair of first dams BNL1 spaced apart from each other. Electrodes 21 and 22 may be disposed on the side surface of the first dams BNL1 along the first direction DR1, arranged on the inclined side surface of the first dams BNL1. For example, the width of electrodes 21 and 22 in the first direction DR1 may be smaller than the width of the first dams BNL1 in the first direction DR1. Electrodes 21 and 22 may be configured to cover at least one side surface of each of the first dams BNL1 to reflect light emitted from the light-emitting element 30, but the embodiments are not limited thereto. Electrodes 21 and 22 may be formed to have a width larger than the first dams BNL1 to cover both inclined side surfaces of each of the first dams BNL1.

[0103] The distance between electrodes 21 and 22 in the first direction DR1 can be smaller than the distance between the first dams BNL1 in the first direction DR1. At least a portion of electrodes 21 and 22 can be directly disposed on the first planarization layer 19 in the same plane.

[0104] Electrodes 21 and 22 may comprise conductive materials with high reflectivity. For example, electrodes 21 and 22 may comprise metals with high reflectivity (such as silver (Ag), copper (Cu), or Al), or alloys of Al, nickel (Ni), or lanthanum (La). Electrodes 21 and 22 may reflect light emitted from the side of the light-emitting element 30 toward the first dam BNL1 in a direction upward from the first sub-pixel PX1.

[0105] However, the embodiments are not limited thereto, and electrodes 21 and 22 may also comprise transparent conductive materials. For example, electrodes 21 and 22 may comprise materials such as ITO, IZO, or indium tin zinc oxide (ITZO). In other embodiments, each of electrodes 21 and 22 may be formed into a structure in which the transparent conductive material and a highly reflective metal are stacked in more than one layer, or may be formed into a single layer comprising the transparent conductive material and a highly reflective metal. For example, each of electrodes 21 and 22 may comprise a stack of ITO / Ag / ITO, ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0106] A first insulating layer PAS1 is disposed on electrodes 21 and 22 and a first dam BNL1. The first insulating layer PAS1 may be configured to cover the first dam BNL1 and the first electrode 21 and the second electrode 22, but may expose portions of the top surfaces of the first electrode 21 and the second electrode 22. An opening OP may be formed in the first insulating layer PAS1 to expose portions of the top surfaces of electrodes 21 and 22 disposed on the first dam BNL1, and contact electrodes CNE1 and CNE2 may contact electrodes 21 and 22 through the opening OP.

[0107] For example, the first insulating layer PAS1 can be formed with a recessed top surface between the first electrode 21 and the second electrode 22. Since the first insulating layer PAS1 can be configured to cover the first electrode 21 and the second electrode 22, it can be formed recessed between them; however, the embodiments are not limited to this. The first insulating layer PAS1 can protect the first electrode 21 and the second electrode 22 and can insulate them from each other. Furthermore, the first insulating layer PAS1 can prevent the light-emitting element 30 from directly contacting other elements and thus being damaged by them.

[0108] A second dam BNL2 may be disposed on the first insulating layer PAS1. In a plan view, the second dam BNL2 may include portions extending in a first direction DR1 and portions extending in a second direction DR2, and thus may be arranged in a grid pattern. The second dam BNL2 may be disposed along the boundary of each of the sub-pixels PXn to define each of the sub-pixels PXn. Furthermore, the second dam BNL2 may be configured to surround the emission region EMA and the cut region CBA of each of the sub-pixels PXn, thereby separating the emission region EMA and the cut region CBA of each of the sub-pixels PXn. The portion of the second dam BNL2 extending along the second direction DR2 between the emission regions EMA of the sub-pixels PXn may have a larger width than the portion of the second dam BNL2 extending along the second direction DR2 between the cut regions CBA of the sub-pixels PXn, and the distance between the cut regions CBA of the sub-pixels PXn may be smaller than the distance between the emission regions EMA of the sub-pixels PXn. However, the embodiments are not limited thereto. The portion of the second dam BNL2 extending along the second direction DR2 between the emission regions EMA of the sub-pixel PXn may have a smaller width than the portion of the second dam BNL2 extending along the second direction DR2 between the cutting regions CBA of the sub-pixel PXn, and the distance between the cutting regions CBA of the sub-pixel PXn may be larger than the distance between the emission regions EMA of the sub-pixel PXn.

[0109] The second dam BNL2 can be formed to have a greater height than the first dam BNL1. The second dam BNL2 can prevent ink from overflowing between different sub-pixels PXn during the inkjet printing process in the manufacturing of the display device 10, and can divide the ink, in which the light-emitting element 30 is dispersed, between different sub-pixels PXn to prevent ink mixing. Like the first dam BNL1, the second dam BNL2 may include polyimide, but the embodiments are not limited thereto.

[0110] The light-emitting element 30 can be disposed on the first insulating layer PAS1. The light-emitting element 30 can be spaced apart from each other in the direction in which the electrodes 21 and 22 extend (i.e., in the second direction DR2) and can be aligned substantially parallel to each other. The light-emitting element 30 can extend in one direction, and the extension directions of the electrodes 21 and 22 can form approximately right angles with the extension direction of the light-emitting element 30. However, the embodiment is not limited to this. The light-emitting element 30 can be arranged diagonally relative to the extension directions of the electrodes 21 and 22.

[0111] The light-emitting element 30 may include semiconductor layers doped with different conductivity types. Since the light-emitting element 30 includes multiple semiconductor layers, it can be aligned such that its first end faces a specific direction depending on the direction of the electric field formed between electrodes 21 and 22. Furthermore, the light-emitting element 30 may include a light-emitting layer 36 (see reference 36). Figure 4 Therefore, it can emit light within a specific wavelength range. The light-emitting layer 36 of different light-emitting elements 30 can emit light within different wavelength ranges depending on their material, but the embodiments are not limited to this. Different light-emitting elements 30 can emit light of the same color.

[0112] Multiple layers can be arranged in the light-emitting element 30 in a direction perpendicular to the top surface of the first substrate 11. The light-emitting element 30 can be arranged such that the direction in which the light-emitting element 30 extends is parallel to the first substrate 11, and the semiconductor layers included in the light-emitting element 30 can be arranged sequentially in a direction parallel to the top surface of the first substrate 11. However, the embodiments are not limited to this. The multiple layers included in the light-emitting element 30 can be arranged in a direction perpendicular to the first substrate 11.

[0113] The light-emitting element 30 can be disposed on electrodes 21 and 22 between the first electrode 21 and the second electrode 22. For example, the first end of the light-emitting element 30 can be disposed on the first electrode 21, and the second end of the light-emitting element 30 can be disposed on the second electrode 22. The length of the light-emitting element 30 can be greater than the distance between the first electrode 21 and the second electrode 22, and both ends of the light-emitting element 30 can be disposed on the first electrode 21 and the second electrode 22.

[0114] The two ends of the light-emitting element 30 can contact the contact electrodes CNE1 and CNE2. Due to the insulating film 38 (see reference...) Figure 4 The semiconductor layer and / or electrode layer 37 of the light-emitting element 30 are not formed at both ends to expose the light-emitting element 30 (see reference). Figure 4The exposed semiconductor layer and / or electrode layer 37 can therefore contact the contact electrodes CNE1 and CNE2, but the embodiments are not limited thereto. At least a portion of the insulating film 38 can be removed, such that a portion of the side surface of the semiconductor layer of the light-emitting element 30 can be exposed. The exposed side surface of the semiconductor layer can directly contact the contact electrodes CNE1 and CNE2.

[0115] The light-emitting element 30 may include an insulating structure 39 formed at one end of the light-emitting element 30 (see reference). Figure 4 The light-emitting element 30 can extend in one direction and may include a first end and a second end opposite to each other in the direction of extension of the light-emitting element 30. The first end and the second end of the light-emitting element 30 can be respectively disposed on the first electrode 21 and the second electrode 22, and in cross-sectional view, the side surfaces of the first end and the second end of the light-emitting element 30 can contact the first contact electrode CNE1 and the second contact electrode CNE2, respectively. An insulating structure 39 can be formed at the first end of the light-emitting element 30. The first contact electrode CNE1 can contact not only the side surface of the first end of the light-emitting element 30 where the insulating structure 39 is formed, but also the insulating structure 39 itself. The second contact electrode CNE2 can contact the side surface of the second end of the light-emitting element 30 where the insulating structure 39 is not formed. The contact relationship between the light-emitting element 30 and the contact electrodes CNE1 and CNE2 will be described in detail below.

[0116] The second insulating layer PAS2 can be partially disposed on the first insulating layer PAS1 and the light-emitting element 30. For example, the second insulating layer PAS2 can be disposed around the outer surface of the light-emitting element 30, but does not cover the first and second ends of the light-emitting element 30. Furthermore, the second insulating layer PAS2 can even be disposed on the first dam BNL1 and the second dam BNL2. The second insulating layer PAS2 can be disposed not only on the light-emitting element 30, but also on the first dam BNL1 and the second dam BNL2, and is configured to expose the two ends of the light-emitting element 30 and the portion of the first insulating layer PAS1 where electrodes 21 and 22 are disposed. During the manufacture of the display device 10, the second insulating layer PAS2 can be initially disposed on the first insulating layer PAS1 and the second dam BNL2, and can then be partially removed to expose the two ends of the light-emitting element 30.

[0117] The portion of the second insulating layer PAS2 disposed on the light-emitting element 30 can extend above the first insulating layer PAS1 along the second direction DR2, thus forming a linear pattern or an island pattern in the first sub-pixel PX1. The second insulating layer PAS2 can protect and fix the light-emitting element 30 during the manufacturing of the display device 10 (e.g., fixing the light-emitting element 30 to the first insulating layer PAS1). Furthermore, the second insulating layer PAS2 can be configured to fill the space between the light-emitting element 30 and the first insulating layer PAS1.

[0118] Multiple contact electrodes CNE1 and CNE2 and a third insulating layer PAS3 can be disposed on the second insulating layer PAS2. The first contact electrode CNE1 and the second contact electrode CNE2 can be partially disposed on the first electrode 21 and the second electrode 22, respectively. The first contact electrode CNE1 can be disposed on the first electrode 21, and the second contact electrode CNE2 can be disposed on the second electrode 22, and both the first contact electrode CNE1 and the second contact electrode CNE2 can extend in the second direction DR2. The first contact electrode CNE1 and the second contact electrode CNE2 can be spaced apart from each other and face each other in the first direction DR1, and can form a linear pattern in the emission region EMA of the first sub-pixel PX1.

[0119] Contact electrodes CNE1 and CNE2 can make electrical contact with the light-emitting element 30 and electrodes 21 and 22. The light-emitting element 30 can have a semiconductor layer exposed at both ends thereof, and the first contact electrode CNE1 and the second contact electrode CNE2 can contact the light-emitting element 30 at the two ends where the semiconductor layer of the light-emitting element 30 is exposed. A first end of the light-emitting element 30 can be electrically connected to the first electrode 21 via the first contact electrode CNE1, and a second end of the light-emitting element 30 can be electrically connected to the second electrode 22 via the second contact electrode CNE2.

[0120] Figure 3 A first contact electrode CNE1 and a second contact electrode CNE2 are shown disposed in a first sub-pixel PX1, but the embodiment is not limited thereto. The number of first contact electrodes CNE1 and second contact electrodes CNE2 disposed in each of the sub-pixels PXn can vary depending on the number of first electrodes 21 and second electrodes 22 disposed in each of the sub-pixels PXn.

[0121] Contact electrodes CNE1 and CNE2 may comprise conductive materials. For example, contact electrodes CNE1 and CNE2 may comprise ITO, IZO, ITZO, or aluminum (Al). For example, contact electrodes CNE1 and CNE2 may comprise transparent conductive materials, and light emitted from the light-emitting element 30 may travel through contact electrodes CNE1 and CNE2 toward electrodes 21 and 22. However, the embodiments are not limited thereto.

[0122] In the region excluding the area where the first contact electrode CNE1 is disposed, the third insulating layer PAS3 can be disposed not only on the second contact electrode CNE2 but also on the second insulating layer PAS2. In the region excluding the area where the first contact electrode CNE1 is disposed, the third insulating layer PAS3 can be disposed on the entire surface of the second contact electrode CNE2 and the second insulating layer PAS2. The third insulating layer PAS3 insulates the first contact electrode CNE1 and the second contact electrode CNE2, preventing them from directly contacting each other. The first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on different layers. The second contact electrode CNE2 can be partially disposed directly on the second insulating layer PAS2, and the first contact electrode CNE1 can be partially disposed directly on the third insulating layer PAS3. In the regions exposed at both ends of the light-emitting element 30 due to the absence of the second insulating layer PAS2 and the third insulating layer PAS3, the first contact electrode CNE1 and the second contact electrode CNE2 can be directly disposed on the first insulating layer PAS1.

[0123] A third insulating layer, PAS3, can be disposed between the first contact electrode CNE1 and the second contact electrode CNE2, thereby insulating the first contact electrode CNE1 and the second contact electrode CNE2 from each other. As described above, in some embodiments, the third insulating layer, PAS3, may not be provided, in which case the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer.

[0124] Although not specifically shown, an insulating layer may also be disposed on the second insulating layer PAS2, the third insulating layer PAS3, and the contact electrodes CNE1 and CNE2 to cover the second insulating layer PAS2, the third insulating layer PAS3, and the contact electrodes CNE1 and CNE2. The insulating layer may be disposed on the entire surface of the first substrate 11 to protect the components disposed on the first substrate 11 from the influence of the external environment.

[0125] The first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 may comprise inorganic or organic insulating materials. For example, the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 may comprise inorganic insulating materials (such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide (AlOx), or aluminum nitride (AlNx)), but the embodiments are not limited thereto. In another example, the first insulating layer PAS1, the second insulating layer PAS2, and the third insulating layer PAS3 may comprise organic insulating materials (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, or polymethyl methacrylate-polycarbonate synthetic resin), but the embodiments are not limited thereto.

[0126] Figure 4 This is a perspective view of the light-emitting element 30 according to an embodiment. Figure 5 yes Figure 4 A top view of the light-emitting element 30. Figure 6 yes Figure 4 A cross-sectional view of the light-emitting element 30. Figure 4 A light-emitting element 30 is shown having a structure in which a portion of an insulating film 38 is cut away to expose a semiconductor layer surrounded by the insulating film 38.

[0127] Reference Figure 4 The light-emitting element 30 can be a light-emitting diode (LED), specifically an ILED having dimensions of a few micrometers or nanometers (e.g., several nanometers or several nanometers, or several micrometers or several micrometers) and formed of an inorganic material. If an electric field is formed in a specific direction between two opposing electrodes, the ILED can be aligned between the two polarized electrodes. The light-emitting element 30 can be aligned by the electric field formed between the two electrodes.

[0128] The light-emitting element 30 may have a shape extending in one direction. The light-emitting element 30 may have a cylindrical, rod, wire, or tube shape, but the embodiment is not particularly limited by the shape of the light-emitting element 30. The light-emitting element 30 may have a polygonal prism shape such as a cube, cuboid, or hexagonal prism, or it may have a shape extending in one direction but with a partially inclined outer surface. Multiple semiconductors included in the light-emitting element 30 may be sequentially arranged or stacked in the direction in which the light-emitting element 30 extends.

[0129] The light-emitting element 30 may include a semiconductor layer doped with impurities of any conductivity type (e.g., p-type or n-type). The semiconductor layer can receive electrical signals from an external power source to emit light within a specific wavelength range.

[0130] Reference Figures 4 to 6 The light-emitting element 30 may include a first semiconductor layer 31, a second semiconductor layer 32, a light-emitting layer 36, an electrode layer 37, an insulating film 38, and an insulating structure 39.

[0131] The first semiconductor layer 31 may include an n-type semiconductor. When the light-emitting element 30 emits light in the blue wavelength range, the first semiconductor layer 31 may include the semiconductor material Al. x Ga y In 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). Semiconductor material Al x Ga y In l-x-y N can be at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The first semiconductor layer 31 can be doped with an n-type dopant, and the n-type dopant can be Si, Ge, or Sn. For example, the first semiconductor layer 31 can be n-GaN doped with n-type Si. The first semiconductor layer 31 can have a length in the range of about 1.5 μm to about 5 μm, but the embodiments are not limited thereto.

[0132] The second semiconductor layer 32 may be disposed on the light-emitting layer 36. The second semiconductor layer 32 may include a p-type semiconductor. When the light-emitting element 30 emits light in the blue or green wavelength range, the second semiconductor layer 32 may include the semiconductor material Al. x Ga y In 1-x-y N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). For example, semiconductor material Al. x Ga y In 1-x-y N can be at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The second semiconductor layer 32 can be doped with a p-type dopant, and the p-type dopant can be Mg, Zn, Ca, Sr, or Ba. For example, the second semiconductor layer 32 can be p-GaN doped with p-type Mg. The second semiconductor layer 32 can have a length in the range of about 0.05 μm to about 0.10 μm, but the embodiments are not limited thereto.

[0133] Figure 4The first semiconductor layer 31 and the second semiconductor layer 32 are shown to be formed as a single layer, but the embodiments are not limited thereto. Depending on the material of the light-emitting layer 36, each of the first semiconductor layer 31 and the second semiconductor layer 32 may include more than one layer, such as a cladding layer or a tensile strain barrier reducing (TSBR) layer.

[0134] A light-emitting layer 36 may be disposed between a first semiconductor layer 31 and a second semiconductor layer 32. The light-emitting layer 36 may comprise a single quantum well structure material or a multi-quantum well structure material. When the light-emitting layer 36 comprises a material with a multi-quantum well structure, the light-emitting layer 36 may have a structure in which multiple quantum layers and multiple well layers are alternately stacked. The light-emitting layer 36 can emit light by causing electron-hole pairs to recombine according to an electrical signal applied to it via the first semiconductor layer 31 and the second semiconductor layer 32. When the light-emitting layer 36 emits light in the blue wavelength range, the quantum layers may comprise materials such as AlGaN or AlGaInN. Specifically, when the light-emitting layer 36 has a multi-quantum well structure in which multiple quantum layers and multiple well layers are alternately stacked, the quantum layers may comprise materials such as AlGaN or AlGaInN, and the well layers may comprise materials such as GaN or AlInN. For example, when the light-emitting layer 36 comprises AlGaInN as its quantum layer and AlInN as its well layer, the light-emitting layer 36 may emit blue light with a center wavelength range of approximately 450 nm to approximately 495 nm.

[0135] However, the embodiments are not limited thereto. Depending on the wavelength of the light to be emitted, the light-emitting layer 36 may have a structure in which semiconductor materials with large bandgap energy and semiconductor materials with small bandgap energy are stacked alternately, or may include group III semiconductor materials or group V semiconductor materials. The embodiments are not limited to the type of light emitted by the light-emitting layer 36. The light-emitting layer 36 may emit light in the red or green wavelength range as needed, instead of blue light. The light-emitting layer 36 may have a length in the range of about 0.05 μm to about 0.10 μm, but the embodiments are not limited thereto.

[0136] Light can be emitted not only from the circumferential surface along the length of the light-emitting element 30, but also from both sides of the light-emitting element 30. The embodiment is not limited by the direction of light emitted from the light-emitting layer 36.

[0137] Electrode layer 37 may be an ohmic contact electrode, but the embodiments are not limited thereto. In another example, electrode layer 37 may be a Schottky contact electrode. The light-emitting element 30 may include at least one electrode layer 37. Figure 4 The illustration shows a light-emitting element 30 including an electrode layer 37, but the embodiment is not limited thereto. The light-emitting element 30 may include more than one electrode layer 37, or may not have an electrode layer 37. The following description of the light-emitting element 30 can also be directly applied to elements having more than one electrode layer 37 or having an electrode layer 37. Figure 4 The light-emitting element 30 has different structures.

[0138] When the light-emitting element 30 is electrically connected to the electrodes (or contact electrodes CNE1 and CNE2), the electrode layer 37 can reduce the resistance between the light-emitting element 30 and the electrodes (or contact electrodes CNE1 and CNE2). The electrode layer 37 may include a conductive metal and / or a conductive metal oxide. For example, the electrode layer 37 may include at least one of Al, Ti, In, gold (Au), Ag, ITO, IZO, and ITZO. Furthermore, the electrode layer 37 may include a semiconductor material doped with an n-type dopant or a p-type dopant. However, the embodiments are not limited thereto.

[0139] The insulating film 38 may be configured to surround the first semiconductor layer 31, the second semiconductor layer 32, and the electrode layer 37. For example, the insulating film 38 may be configured to at least surround the light-emitting layer 36 and may extend in the direction in which the light-emitting element 30 extends. The insulating film 38 may protect the first semiconductor layer 31, the light-emitting layer 36, the second semiconductor layer 32, and the electrode layer 37. For example, the insulating film 38 may be formed around the sides of the first semiconductor layer 31, the sides of the light-emitting layer 36, the sides of the second semiconductor layer 32, and the sides of the electrode layer 37, but may expose the two ends of the light-emitting element 30 in the longitudinal direction.

[0140] Figure 4 The insulating film 38 is shown extending along the length of the light-emitting element 30 and covering the sides of the first semiconductor layer 31, the side of the light-emitting layer 36, the side of the second semiconductor layer 32, and the side of the electrode layer 37; however, the embodiment is not limited to this. The insulating film 38 may only cover the sides of the light-emitting layer 36 and some of the sides of the first semiconductor layer 31 and the second semiconductor layer 32, or it may only cover a portion of the sides of the electrode layer 37, such that the sides of the electrode layer 37 are partially exposed. In the region adjacent to at least one end of the light-emitting element 30, the insulating film 38 may be formed as a circle in cross-sectional view.

[0141] The thickness WB of the insulating film 38 can be from about 10 nm to about 1.0 μm, but the embodiments are not limited thereto. For example, the thickness WB of the insulating film 38 can be from about 10 nm to about 200 nm. Preferably, the thickness WB of the insulating film 38 can be in the range of about 40 nm to about 120 nm.

[0142] The insulating film 38 may comprise a material with insulating properties, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, zirconium oxide (ZrOx), or hafnium oxide (HfOx). For example, the insulating film 38 may be a single layer or multiple layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, zirconium oxide, and hafnium oxide. Therefore, the insulating film 38 can prevent short circuits that may occur when the light-emitting layer 36 is placed in direct contact with the electrodes that transmit electrical signals directly to the light-emitting element 30. Furthermore, since the insulating film 38 protects the outer surface of the light-emitting element 30, including the light-emitting layer 36, it can prevent degradation of the luminous efficiency (or emission efficiency) of the light-emitting element 30.

[0143] The outer surface of the insulating film 38 can be surface-treated. The light-emitting element 30 can be sprayed onto the electrode and simultaneously dispersed in the ink. Here, the surface of the insulating film 38 can be hydrophobically or hydrophilically treated to keep the light-emitting element 30 dispersed in the ink and prevent it from agglomerating with other adjacent light-emitting elements 30. For example, the insulating film 38 can be surface-treated with materials such as stearic acid or 2,3-naphthalenedicarboxylic acid.

[0144] The light-emitting element 30 may include an insulating structure 39 disposed on the electrode layer 37. The insulating structure 39 may be configured to expose a portion of the top surface of the electrode layer 37. For example, the maximum diameter (or width) WC of the insulating structure 39 may be smaller than the diameter of the electrode layer 37, and may expose portions of the electrode layer 37 where the insulating structure 39 is not disposed. The insulating structure 39 may have its maximum diameter WC at its bottom surface where it meets the top surface of the electrode layer 37, and the diameter of the insulating structure 39 may gradually decrease from the bottom to the top of the insulating structure 39. In a cross-sectional view, the insulating structure 39 may be formed as a conical shape with inclined side surfaces, or as a rod shape having a larger diameter at its bottom than at its top. In some embodiments, the maximum diameter WC of the insulating structure 39 may be in the range of about 100 nm to about 500 nm, and the height HC of the insulating structure 39 may be in the range of about 500 nm to about 1 μm. However, the embodiments are not limited thereto.

[0145] For example, the insulating structure 39 of the light-emitting element 30 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride as the insulating material. The electrode layer 37 of the light-emitting element 30 may contact and be electrically connected to the first contact electrode CNE1, but the insulating structure 39 disposed on the electrode layer 37 may contact the first contact electrode CNE1 but not be electrically connected to it. The maximum diameter WC of the insulating structure 39 may be smaller than the diameter of the electrode layer 37, allowing a portion of the top surface of the electrode layer 37 to be exposed.

[0146] The light-emitting element 30 can be obtained by growing multiple semiconductor layers on a target substrate via epitaxial growth and etching the grown semiconductor layers in a direction perpendicular to the top surface of the target substrate. The etching of the grown semiconductor layers can be performed by forming a mask layer on the grown semiconductor layers and dry or wet etching the grown semiconductor layers along the pattern of the mask layer. The light-emitting element 30 may include an electrode layer 37 formed of a material such as ITO, and a mask layer for etching the grown semiconductor layers is disposed on the electrode layer 37. After etching of the grown semiconductor layers, a chemical processing process is performed to remove the mask layer retained on the electrode layer 37. The etchant used in the chemical processing process may damage the material (such as ITO) of the electrode layer 37. Because the electrode layer 37 in contact with the contact electrodes CNE1 and CNE2 is damaged, the luminous efficiency or brightness of the light-emitting element 30 is reduced.

[0147] After etching the grown semiconductor layer, mask layer removal is not required, and the material of the mask layer remaining on the electrode layer 37 can form the insulating structure 39 of the light-emitting element 30. The insulating structure 39 can be disposed as a separate element on the electrode layer 37, can form a physical boundary with the electrode layer 37, and can protrude from the top surface of the electrode layer 37. By etching the grown semiconductor layer while controlling the etching duration and the type and concentration of the etchant used to partially expose the top surface of the electrode layer 37, sufficient contact surface area can be ensured between the electrode layer 37 of the light-emitting element 30 and the contact electrodes CNE1 and CNE2.

[0148] Figure 7 yes Figure 3 An enlarged sectional view of part A. Figure 8 It shows Figure 3 The first end of the light-emitting element 30 is in contact with the first contact electrode CNE1. Figure 8 This is a top view of the electrode layer 37 of the light-emitting element 30, and shows the contact surfaces SA1 and SA2 between the first contact electrode CNE1 and the light-emitting element 30.

[0149] Reference Figure 7 and Figure 8 And also refer to Figure 3 and Figure 6The light-emitting element 30 may include a first end and a second end. An electrode layer 37 and an insulating structure 39 are disposed at the first end, and the second end is opposite to the first end, with the lower portion of the first semiconductor layer 31 disposed at the second end. The light-emitting element 30 may be arranged such that the direction in which the light-emitting element 30 extends is parallel to the top surface of the first substrate 11, and the first end and the second end of the light-emitting element 30 may be disposed on the first electrode 21 and the second electrode 22, respectively. Furthermore, the first end and the second end of the light-emitting element 30 may contact the first contact electrode CNE1 and the second contact electrode CNE2, respectively. Since the insulating structure 39 is disposed on the electrode layer 37 of the light-emitting element 30, the first contact electrode CNE1 may not contact the entire top surface of the electrode layer 37, but may partially contact the insulating structure 39. Because there is no intermediate element between the second contact electrode CNE2 and the first semiconductor layer 31, the second contact electrode CNE2 may contact the entire bottom surface of the first semiconductor layer 31.

[0150] For example, the display device 10 may have a first contact surface SA1 where the first contact electrode CNE1 contacts the top surface of the electrode layer 37 of the light-emitting element 30, a second contact surface SA2 where the first contact electrode CNE1 contacts the insulating structure 39, and a third contact surface SA3 where the second contact electrode CNE2 contacts the bottom surface of the first semiconductor layer 31.

[0151] The first contact electrode CNE1 can be formed after the light-emitting element 30 is arranged on electrodes 21 and 22 and the second insulating layer PAS2, the second contact electrode CNE2, and the third insulating layer PAS3 are formed. Since the insulating structure 39 is provided at the portion of the first end of the light-emitting element 30 that is exposed due to the absence of the second insulating layer PAS2 and the third insulating layer PAS3, a space PS can be formed between the insulating structure 39 and the first insulating layer PAS1 on which the light-emitting element 30 is disposed. The first contact electrode CNE1 can surround the first end of the light-emitting element 30 and the outer surface of the insulating structure 39, and can contact the electrode layer 37, the insulating structure 39, and the insulating film 38 of the light-emitting element 30.

[0152] When the first contact electrode CNE1 is positioned around the first end of the light-emitting element 30, the entire top surface of the electrode layer 37, except for the portion covered by the insulating structure 39, can contact the first contact electrode CNE1. Even with the insulating structure 39 disposed on the electrode layer 37, the maximum diameter WC of the insulating structure 39 can be controlled to ensure a sufficiently large first contact surface SA1 for the first contact electrode CNE1 and the electrode layer 37 to contact each other for electrical connection.

[0153] The second contact surface SA2, which contacts the first contact electrode CNE1 and the insulating structure 39, can be formed on the upper part of the side surface of the insulating structure 39, and the first contact electrode CNE1 can surround the side surface of the insulating structure 39, but may not contact the lower part of the side surface of the insulating structure 39. Since the insulating structure 39 has a conical shape with inclined side surfaces, the second contact surface SA2 can be formed only on one half of the inclined side surface of the insulating structure 39, and not on the other half of the inclined side surface of the insulating structure 39.

[0154] The portion of the side surface of the insulating structure 39 facing the first insulating layer PAS1 and the portion of the top surface of the electrode layer 37 located below the insulating structure 39 in the cross-sectional view may not contact the first contact electrode CNE1. Since the space PS covered by the insulating structure 39 is formed between the insulating structure 39 and the first insulating layer PAS1 of the light-emitting element 30, portions of the top surface of the electrode layer 37 and portions of the side surface of the insulating structure 39 may not contact the first contact electrode CNE1. For example, a non-contact surface NS1 that does not contact the first contact electrode CNE1 may be formed in the portion of the exposed top surface of the electrode layer 37 adjacent to the space PS, and portions of the side surface of the insulating structure 39 may not contact the first contact electrode CNE1. The first contact electrode CNE1 is shown not disposed in the space PS between the first insulating layer PAS1 and the insulating structure 39, but the embodiment is not limited to this. During the formation of the first contact electrode CNE1, some of the material of the first contact electrode CNE1 may be formed in the space PS located below the insulating structure 39. For example, at least a portion of the insulating structure 39 of the light-emitting element 30 adjacent to the space PS may include a non-contact surface NS1 that does not contact the first contact electrode CNE1.

[0155] Since both the electrode layer 37 and the top surface of the insulating film 38 are exposed on the top surface of the light-emitting element 30, the first contact surface SA1 can be formed not only in a portion of the top surface of the electrode layer 37 but also in a portion of the top surface of the insulating film 38. Similarly, the non-contact surface NS1 can be formed in a portion of the top surface of the insulating film 38.

[0156] Since the insulating structure 39 of the light-emitting element 30 is not disposed on the bottom surface of the first semiconductor layer 31, the third contact surface SA3 where the first semiconductor layer 31 and the second contact electrode CNE2 of the light-emitting element 30 contact each other can be larger than the first contact surface SA1. The second contact electrode CNE2 can contact the entire bottom surface of the first semiconductor layer 31 as well as the bottom and side surfaces of the insulating film 38.

[0157] Light generated by the light-emitting layer 36 of the light-emitting element 30 can be emitted through both end surfaces of the light-emitting element 30. Since the insulating structure 39, unlike the electrode layer 37, comprises insulating material, the insulating structure 39 and the electrode layer 37 can have different refractive indices. As a result, light emitted by the light-emitting element 30 through the top surface of the electrode layer 37 can be scattered or diffused by the insulating structure 39.

[0158] Figure 9 It shows from Figure 4 An enlarged cross-sectional view of the path of the light emitted by the light-emitting element 30.

[0159] Reference Figure 9 Light generated by the light-emitting layer 36 of the light-emitting element 30 can be emitted from both ends of the light-emitting element 30 through the first semiconductor layer 31 and the second semiconductor layer 32. Some of the first light L1 emitted from the first end of the light-emitting element 30 through the second semiconductor layer 32 and the electrode layer 37 can be emitted through the insulating structure 39. The second light L2 passing through the first semiconductor layer 31 can be emitted from the second end of the light-emitting element 30 without passing through the insulating structure 39. The second light L2 can be reflected in the direction upward from the first substrate 11 by the second electrode 22 disposed on the side surface of one of the first dams BNL1.

[0160] Since electrode layer 37 comprises a transparent conductive material and insulating structure 39 comprises an insulating material, a difference in refractive index may occur between electrode layer 37 and insulating structure 39. Furthermore, a difference in refractive index may also occur between the first contact electrode CNE1 and insulating structure 39. The travel path of the first light L1 can be altered when it is refracted at the interface between electrode layer 37 and insulating structure 39, and at the interface between insulating structure 39 and first contact electrode CNE1. When light emitted from the first end of light-emitting element 30 travels toward the first electrode 21 on one of the first dams BNL1, light refracted from insulating structure 39 can also travel toward the upper part of the first electrode 21 near one of the first dams BNL1. As a result, the amount of first light L1 reflected from first electrode 21 and then traveling upwards from the first substrate 11 can be increased, and the luminous efficiency of display device 10 can be improved. The light generated by light-emitting layer 36 can be scattered depending on the material and crystal structure of insulating structure 39.

[0161] The length h of the entire light-emitting element 30, excluding the insulating structure 39, can be in the range of about 1 μm to about 10 μm, or in the range of about 2 μm to about 6 μm, preferably about 3 μm to about 5 μm. The length (e.g., h) of the stacked first semiconductor layer 31, light-emitting layer 36, second semiconductor layer 32, and electrode layer 37 can be in the range of about 1 μm to about 10 μm, or in the range of about 2 μm to about 6 μm, preferably about 3 μm to about 5 μm. The diameter WA of the light-emitting element 30 can be in the range of about 30 nm to about 700 nm, and the aspect ratio of the light-emitting element 30 can be in the range of about 1.2 to about 100. However, the embodiments are not limited to these. Different light-emitting elements 30 can have different diameters depending on the composition of their light-emitting layers 36. Preferably, the diameter WA of the light-emitting element 30 can be about 500 nm.

[0162] In the following text, reference will be made to Figure 10 The manufacturing process of the light-emitting element 30 is described.

[0163] Figure 10 This is a flowchart illustrating a method for manufacturing a light-emitting element 30 according to an embodiment.

[0164] Reference Figure 10 The method may include: forming a semiconductor structure on a target substrate (S100); forming a mask layer on the semiconductor structure (S200); forming an element rod by etching the semiconductor structure (S300); and forming an insulating film on the side surface of the element rod and separating the element rod from the target substrate (S400). As described above, the light-emitting element 30 can be fabricated by growing multiple semiconductor layers via epitaxial growth and etching the semiconductor layers in a direction perpendicular to the top surface of the target substrate. The mask layer can be used to perform etching of the semiconductor structure obtained by growing the semiconductor layers to form a separated element rod, and a portion of the mask layer can be retained on the element rod to form an insulating structure 39.

[0165] In the following text, reference will be made to Figures 11 to 18 The manufacture of the light-emitting element 30 is described in more detail.

[0166] Figures 11 to 18 It is shown Figure 10 A sectional view of the method.

[0167] First refer to Figure 11The preparation (processing) includes a substrate 110 and a buffer material layer 120 formed on the substrate 110. The substrate 110 may include a transparent substrate (such as a sapphire (Al2O3) substrate or a glass substrate), but the embodiments are not limited thereto. The substrate 110 may include a conductive substrate of GaN, SiC, ZnO, Si, GaP, or GaAs. Hereinafter, the substrate 110 will be described, for example, as a sapphire substrate. The embodiments are not limited by the thickness of the substrate 110. For example, the substrate 110 may have a thickness in the range of about 400 μm to about 1500 μm.

[0168] A semiconductor layer is formed on the substrate 110. The semiconductor layer can be formed by growing a seed crystal via epitaxial growth. Specifically, the semiconductor layer can be formed by electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition, dual-mode thermal evaporation, sputtering, or metal-organic chemical vapor deposition (MOCVD). Preferably, the semiconductor layer is formed by MOCVD, but the embodiments are not limited thereto.

[0169] The embodiments are not limited to the precursor material used to form the semiconductor layer. For example, the precursor material may include a metal precursor, which includes an alkyl group (such as methyl or ethyl). The metal precursor may be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), or triethyl phosphate ((C2H5)3PO4), but the embodiments are not limited thereto. The semiconductor layer can be formed by using deposition processes with both metal and non-metal precursors. The semiconductor layer can be formed under what conditions and in what circumstances it is described below. Furthermore, the sequence of fabrication of the light-emitting element 30 and the structure of the light-emitting element 30 will be described below.

[0170] A buffer material layer 120 is formed on the substrate 110. Figure 11 The illustration shows a single buffer material layer 120 formed on a substrate 110, but the embodiments are not limited thereto. Multiple buffer material layers 120 may be formed on the substrate 110. Buffer material layers 120 may be provided to reduce the difference in lattice constant between the first semiconductor material layer 310 formed on the buffer material layer 120 and the substrate 110.

[0171] For example, the buffer material layer 120 may include an undoped semiconductor and may include a material substantially the same as that of the first semiconductor material layer 310, but the material of the buffer material layer 120 may be an undoped material. The buffer material layer 120 may include at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but the embodiments are not limited thereto. Depending on the type of the substrate 110, the buffer material layer 120 may not be provided. Hereinafter, the buffer material layer 120 will be described as an undoped semiconductor layer formed on the substrate 110.

[0172] Reference Figure 12 A semiconductor structure 300 is formed on the target substrate 100. The semiconductor structure 300 may include a first semiconductor material layer 310, a light-emitting material layer 360, a second semiconductor material layer 320, and an electrode material layer 370. The first semiconductor material layer 310, the light-emitting material layer 360, the second semiconductor material layer 320, and the electrode material layer 370 may be formed by the above-described process and may correspond to the layers included in the light-emitting element 30 to be formed. The first semiconductor material layer 310, the light-emitting material layer 360, the second semiconductor material layer 320, and the electrode material layer 370 may each include the same material as the first semiconductor layer 31, the light-emitting layer 36, the second semiconductor layer 320, and the electrode layer 370 of the light-emitting element 30.

[0173] Reference Figures 13 to 15 The semiconductor structure 300 is etched to form spaced-apart element rods (RODs). For example, etching the semiconductor structure 300 may include forming a mask layer 400 on the semiconductor structure 300, performing a first etching process using the mask layer 400 to etch the semiconductor structure 300, and performing a second etching process after the first etching process.

[0174] Reference Figure 13 A mask layer 400 is formed on the semiconductor structure 300. The mask layer 400 may include an insulating mask layer 410 disposed on the electrode material layer 370 and a metal pattern layer 420 disposed on the insulating mask layer 410. The metal pattern layer 420 may include a plurality of patterns spaced apart from each other, and the insulating mask layer 410 and the semiconductor structure 300 may be etched along the gaps between the patterns of the metal pattern layer 420. In some embodiments, the patterns of the metal pattern layer 420 may have the same diameter or width. The portions of the semiconductor structure 300 that are superimposed on the patterns of the metal pattern layer 420 and thus remain unetched may form element rods (RODs). Therefore, the diameter of the patterns of the metal pattern layer 420 may be the same as the diameter of the electrode layer 37. Since the patterns of the metal pattern layer 420 have the same diameter or width, the light-emitting elements 30 may have substantially the same diameter.

[0175] The insulating mask layer 410 may include an insulating material, and the metal pattern layer 420 may include a metallic material. For example, the insulating mask layer 410 may include silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the insulating mask layer 410 may be from about 1.0 μm to about 2.0 μm, but the embodiments are not limited thereto. The metal pattern layer 420 may include a metal such as chromium (Cr) and may have a thickness from about 30 nm to about 150 nm, but the embodiments are not limited thereto.

[0176] Subsequently, refer to Figure 14 and Figure 15 A first etching process is performed to etch the insulating mask layer 410 and the semiconductor structure 300 along the pattern of the metal pattern layer 420 in a direction perpendicular to the top surface of the target substrate 100, and then a second etching process is performed.

[0177] The first and second etching processes can be performed using dry etching, wet etching, reactive ion etching (RIE), or inductively coupled plasma-reactive ion etching (ICP-RIE). For example, dry etching can be performed, particularly anisotropic dry etching, and dry etching can be adapted to vertically etch the semiconductor structure 300. Etching agents such as Cl2 or O2 can be used here, but the embodiments are not limited thereto.

[0178] For example, the first etching process can be a dry etching process, while the second etching process can be a wet etching process. As a result of the first etching process, portions of the insulating mask layer 410 and the semiconductor structure 300 can be etched away from the gaps between the patterns of the metal pattern layer 420. The insulating mask layer 410 can be partially etched away along the patterns of the metal pattern layer 420, and a hard mask layer 390 can be formed therefrom. The metal pattern layer 420 can be removed during the etching of the insulating mask layer 410.

[0179] The hard mask layer 390 can have a shape in which its width gradually increases from top to bottom. The shape of the insulating mask layer 410 can vary depending on the conditions of the first etching process. As long as the semiconductor structure 300 is not over-etched to the extent that the side surface of the portion of the hard mask layer 390 is perpendicular to the top surface of the semiconductor structure 300, the shape of the hard mask layer 390 can be substantially as follows: Figure 14 As shown in the figure. However, the embodiments are not limited thereto. The hard mask layer 390 can be used as a mask for etching the semiconductor structure 300, and the bottom width of a portion of the hard mask layer 390 can be the same as the diameter of the element rod ROD formed by etching the semiconductor structure 300.

[0180] The semiconductor structure 300 is etched along the gaps between portions of the hard mask layer 390 using a first etching process. Portions of the semiconductor structure 300 can be etched away from between portions of the hard mask layer 390 to obtain a stacked structure whose width increases from top to bottom, similar to the hard mask layer 390. Once the semiconductor structure 300 has been etched using the first etching process, the unetched portions of each of the semiconductor layers can have angled side surfaces. A second etching process can then be performed such that the side surfaces of the remaining portions of each of the semiconductor layers are perpendicular to the top surface of the target substrate 100, thereby straightening the side surfaces of the semiconductor structure 300.

[0181] The insulating mask layer 410 and the semiconductor structure 300 can be etched using a continuous etching process, but the embodiments are not limited thereto. The first etching process can be performed by partially etching the insulating mask layer 410 to form a hard mask layer 390 and then using the hard mask layer 390 to etch the semiconductor structure 300.

[0182] Subsequently, an insulating structure 39 is formed by performing a second etching process to partially etch the hard mask layer 390, and a component rod ROD is formed by etching a portion of the inclined side surface of each of the semiconductor layers. Holes can be formed in the semiconductor structure 300 by the first and second etching processes, and the layers of the semiconductor structure 300 can be etched to form a component rod ROD comprising a first semiconductor layer 31, a light-emitting layer 36, a second semiconductor layer 32, and an electrode layer 37. The component rods ROD can be spaced apart from each other through the holes. The buffer material layer 120 of the target substrate 100 can be partially exposed in the holes through which the component rods ROD are spaced apart from each other.

[0183] The portion of the semiconductor structure 300 that was not removed by the first etching process can be etched by a second etching process, which is a wet etching process, such that the side surface of this portion of the semiconductor structure 300 can be perpendicular to the top surface of the target substrate 100, and thus the side surface of the semiconductor structure 300 is straightened. As a result of the second etching process, the diameter and height of the hard mask layer 390 can be reduced, allowing the formation of the insulating structure 39. For example, a wet etching process can be performed as the second etching process, and the duration of the second etching process and the type and concentration of the etchant used in the second etching process can be controlled, allowing the formation of the insulating structure 39. The insulating structure 39 remaining on the electrode layer 37 of the component rod ROD can be the remaining portion of the hard mask layer 390, which was previously used as a mask for etching the semiconductor structure 300. If an additional etchant treatment is performed after the second etching process to completely remove the remaining portion of the hard mask layer 390, the surface of the electrode layer 37, including ITO, will be damaged. To prevent this, in this embodiment, after the etching process used to form the element rod ROD, the process of removing the remaining portion of the insulating structure 39, which serves as the insulating mask layer 410, may not be performed. Since the etchant treatment process for removing the insulating structure 39 is not performed, damage to the electrode layer 37 can be prevented, and the light-emitting element 30 can be properly electrically connected to the first contact electrode CNE1.

[0184] In this embodiment, an unremoved insulating structure 39 may be retained on the electrode layer 37 of the light-emitting element 30, and the insulating structure 39 may form a contact surface with the first contact electrode CNE1. The insulating structure 39 can be formed with dimensions that allow the electrode layer 37 of the light-emitting element 30 to make sufficient contact with the first contact electrode CNE1 by controlling the conditions of the second etching process. The light-emitting element 30 can make proper contact with the first contact electrode CNE1 while preventing damage to the electrode layer 37 by the chemical processing, thereby improving the luminous efficiency and brightness of the light-emitting element 30.

[0185] Although not specifically shown, a process of rinsing and drying the insulating structure 39 and the component rod ROD can be performed after a second etching process, which is a wet etching process. In some embodiments, rinsing of the insulating structure 39 and the component rod ROD can be performed for about five minutes to about ten minutes, and drying of the insulating structure 39 and the component rod ROD can be performed for about one minute to about five minutes. However, the embodiments are not limited thereto.

[0186] Reference Figure 16 and Figure 17An insulating film 38 can be formed to partially surround the side of the component rod ROD, which includes the insulating structure 39. The insulating film 38 can be formed by forming an insulating layer 380 on the outer surface of the insulating structure 39 and the outer surface of the component rod ROD and performing a third etching process to remove a portion of the insulating layer 380 to expose the end of the component rod ROD (e.g., the top surface of the electrode layer 37).

[0187] The insulating layer 380 can be formed by applying an insulating material to the outer surface of the vertically etched component rod ROD or by immersing the component rod ROD in an insulating material, but the embodiments are not limited thereto. For example, the insulating layer 380 can be formed by atomic layer deposition (ALD) or CVD.

[0188] The insulating layer 380 can be formed not only on the side and top surfaces of the component rod ROD, but also on the portion of the target substrate 100 exposed between the component rod RODs. The insulating layer 380 can be partially removed by a dry etching process (as an anisotropic etching process) or an etch-back process. The upper portion of the insulating layer 380 can be removed to expose the electrode layer 37 and the insulating structure 39, and in this process, the electrode layer 37 can be partially removed. The electrode layer 37 of the light-emitting element 30 can be thinner than the electrode material layer 370. Furthermore, the size of the insulating structure 39 in the light-emitting element 30 can be smaller than the size of the insulating structure 39 in the component rod ROD.

[0189] The top surface of electrode layer 37 is shown as partially exposed, and insulating film 38 is shown as flat at its top. However, the embodiments are not limited thereto. In some embodiments, insulating film 38 may be formed to be partially curved in the region surrounding electrode layer 37. During the removal of a portion of insulating layer 380, not only the top surface of insulating layer 380 is partially removed, but also the side surfaces of insulating layer 380 are partially removed, such that insulating film 38 may be formed with partially etched end surfaces. When the upper portion of insulating layer 380 is removed, the outer surface of insulating film 38 adjacent to electrode layer 37 may be formed to be partially removed.

[0190] Subsequently, refer to Figure 18 The element rod ROD, in which the insulating structure 39 and the insulating film 38 are formed, is separated from the target substrate 100 to obtain the light-emitting element 30.

[0191] The embodiments are not limited to those described above. Figure 4 The shape and material of the light-emitting element 30 are described. In other embodiments, the light-emitting element 30 may include more layers, or may have a shape similar to... Figure 4 The light-emitting elements have 30 different shapes.

[0192] Figure 19This is a schematic perspective view of the light-emitting element 30_1 according to an embodiment. Figure 20 This is a schematic cross-sectional view of the light-emitting element 30_1 taken along its length, and shows multiple semiconductor layers stacked in the light-emitting element 30_1.

[0193] Reference Figure 19 and Figure 20 The light-emitting element 30_1 may further include a third semiconductor layer 33_1 disposed between the first semiconductor layer 31_1 and the light-emitting layer 36_1, and a fourth semiconductor layer 34_1 and a fifth semiconductor layer 35_1 disposed between the light-emitting layer 36_1 and the second semiconductor layer 32_1. The light-emitting element 30_1 and... Figure 4 The difference in the light-emitting element 30 is that it further includes a third semiconductor layer 33_1, a fourth semiconductor layer 34_1, and a fifth semiconductor layer 35_1, as well as a first electrode layer 37A_1 and a second electrode layer 37B_1, and the light-emitting layer 36_1 includes... Figure 4 The luminescent layer contains 36 different elements. The following text will primarily focus on... Figure 4 The differences in the light-emitting element 30 are used to describe the light-emitting element 30_1.

[0194] Figure 4 The light-emitting layer 36 of the light-emitting element 30 includes nitrogen (N), thus emitting blue or green light. Conversely, Figure 19 The light-emitting layer 36_1 or other semiconductor layer of the light-emitting element 30_1 may be a phosphorus (P)-containing semiconductor. The light-emitting element 30_1 may emit red light having a center wavelength range of about 620 nm to about 750 nm. However, the embodiments are not limited to a specific center wavelength range of red light emitted by the light-emitting element 30_1, and may cover all wavelengths that can be perceived as red.

[0195] The first semiconductor layer 31_1 may be an n-type semiconductor layer, and may include layers having the chemical formula In. x Al y Ga 1-x-y The semiconductor material P (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1) may be a semiconductor material. The first semiconductor layer 31_1 may include any one of InAlGaP, GaP, AlGaP, InGaP, AlP, and InP doped with an n-type dopant. For example, the first semiconductor layer 31_1 may be n-AlGaInP doped with n-type Si.

[0196] The second semiconductor layer 32_1 may be a p-type semiconductor layer, and may include a semiconductor layer having the chemical formula In. x Al y Ga 1-x-yThe second semiconductor layer 32_1 may comprise any one of InAlGaP, GaP, AlGaNP, InGaP, AlP, and InP doped with a p-type dopant. For example, the second semiconductor layer 32_1 may be p-GaP doped with p-type Mg.

[0197] A light-emitting layer 36_1 may be disposed between a first semiconductor layer 31_1 and a second semiconductor layer 32_1. The light-emitting layer 36_1 may comprise a material having a single quantum well structure or a multiple quantum well structure, and thus may emit light within a specific wavelength range. In the case where the light-emitting layer 36_1 has a structure in which quantum layers and well layers are alternately stacked, the quantum layers may comprise AlGaP or AlInGaP, and the well layers may comprise GaP or AlInP. For example, the light-emitting layer 36_1 may comprise AlGaInP as the quantum layer and AlInP as the well layer, and thus may emit red light with a center wavelength range of approximately 620 nm to approximately 750 nm.

[0198] Figure 19 The light-emitting element 30_1 may include a cladding layer disposed adjacent to the light-emitting layer 36_1. The third semiconductor layer 33_1 and the fourth semiconductor layer 34_1 disposed between the first semiconductor layer 31_1 and the second semiconductor layer 32_1 may be cladding layers.

[0199] The third semiconductor layer 33_1 can be disposed between the first semiconductor layer 31_1 and the light-emitting layer 36_1. Like the first semiconductor layer 31_1, the third semiconductor layer 33_1 can be an n-type semiconductor and can include components having the chemical formula In. x Al y Ga 1-x-y A semiconductor material P (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). For example, the first semiconductor layer 31_1 can be n-AlGaInP, and the third semiconductor layer 33_1 can be n-AlInP. However, the embodiments are not limited to this.

[0200] A fourth semiconductor layer 34_1 can be disposed between the light-emitting layer 36_1 and the second semiconductor layer 32_1. Like the second semiconductor layer 32_1, the fourth semiconductor layer 34_1 can be a p-type semiconductor and can include components having the chemical formula In. x Al y Ga l-x-y A semiconductor material P (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ x + y ≤ 1). For example, the second semiconductor layer 32_1 can be p-GaP, while the fourth semiconductor layer 34_1 can be p-AlInP.

[0201] A fifth semiconductor layer 35_1 may be disposed between the second semiconductor layer 32_1 and the fourth semiconductor layer 34_1. Like the second semiconductor layer 32_1 and the fourth semiconductor layer 34_1, the fifth semiconductor layer 35_1 may be a semiconductor doped with a p-type dopant. In some embodiments, the fifth semiconductor layer 35_1 may be disposed to reduce the difference in lattice constant between the second semiconductor layer 32_1 and the fourth semiconductor layer 34_1. The fifth semiconductor layer 35_1 may be a tensile strain barrier reduction (TSBR) layer. For example, the fifth semiconductor layer 35_1 may include p-GaInP, p-AlInP, or p-AlGaInP, but the embodiments are not limited thereto. The third semiconductor layer 33_1, the fourth semiconductor layer 34_1, and the fifth semiconductor layer 35_1 may have lengths ranging from about 0.08 μm to about 0.25 μm, but the embodiments are not limited thereto.

[0202] The first electrode layer 37A_1 and the second electrode layer 37B_1 can be respectively disposed on the first semiconductor layer 31_1 and the second semiconductor layer 32_1. The first electrode layer 37A_1 can be disposed on the bottom surface of the first semiconductor layer 31_1, and the second electrode layer 37B_1 can be disposed on the top surface of the second semiconductor layer 32_1. However, the embodiments are not limited to this, and one of the first electrode layer 37A_1 and the second electrode layer 37B_1 may not be disposed. For example, the light-emitting element 30_1 may not have the first electrode layer 37A_1 on the bottom surface of the first semiconductor layer 31_1, but may only include the second electrode layer 37B_1 on the top surface of the second semiconductor layer 32_1. The light-emitting element 30_1 may also include, in addition to Figure 19 and Figure 20 Other semiconductor layers besides the semiconductor layer shown, and capable of emitting red light.

[0203] An insulating structure 39_1 can be disposed on the second electrode layer 37B_1. The light-emitting element 30_1 can be manufactured by depositing multiple semiconductor layers to form a semiconductor structure 300 and then etching the semiconductor structure 300. After sequentially depositing multiple semiconductor layers starting from the first semiconductor layer 31_1, the second electrode layer 37B_1 can be formed on the second semiconductor layer 32_1. Then, a mask layer 400 for etching the semiconductor structure 300 can be formed, and the insulating structure 39_1 can be formed on the second electrode layer 37B_1 by etching the semiconductor structure 300 using the mask layer 400. After separating the element rod ROD, in which the insulating structure 39_1 is formed, from the target substrate 100, the first electrode layer 37A_1 can be formed on the bottom surface of the first semiconductor layer 31_1. Therefore, even if the light-emitting element 30_1 includes a considerable number of semiconductor layers, the insulating structure 39_1 can be disposed only on the second electrode layer 37B_1 located on the second semiconductor layer 32_1.

[0204] Figure 21 This is a schematic cross-sectional view of the light-emitting element 30_2 according to an embodiment.

[0205] Reference Figure 21 According to the embodiment, the light-emitting element 30_2 may include an insulating structure 39_2 having an undercut UC formed thereon at its bottom. The insulating structure 39_2 may include a first portion 39A and a second portion 39B, the first portion 39A having an inclined side surface, and the second portion 39B being connected to the lower part of the first portion 39A and having an undercut UC formed thereon.

[0206] During the fabrication of the light-emitting element 30_2, the insulating structure 39_2 can be formed by partially etching the hard mask layer 390 using wet etching. When the insulating mask layer 410 is patterned along the pattern of the metal pattern layer 420, a hard mask layer 390 with inclined side surfaces can be formed, and an undercut UC can be formed at the lower portion of the hard mask layer 390 (i.e., at the portion of the hard mask layer 390 directly on the electrode layer 37) using etchant from wet etching. The insulating structure 39_2 can be configured to expose a portion of the top surface of the electrode layer 37, and the insulating structure 39_2 can have a [specific characteristic] due to the presence of the undercut UC formed by wet etching. Figure 6 The insulation structure has 39 different shapes.

[0207] For example, the insulating structure 39_2 may include a first portion 39A and a second portion 39B, the first portion 39A having a maximum width (or diameter) WC, and the second portion 39B having a smaller width than the first portion 39A and being disposed on the electrode layer 37. Figure 21 In the embodiments, different Figure 6 In one embodiment, the insulating structure 39_2 may not have its maximum width WC at its bottom surface directly on the electrode layer 37, but rather at a portion of its surface at a predetermined distance from the electrode layer 37. The side surface of the second portion 39B may be recessed inward from the lower part of the first portion 39A, and may have a relatively small width due to the presence of an undercut UC formed by wet etching.

[0208] Since the undercut UC is formed at the lower part of the insulating structure 39_2, the maximum width WC of the insulating structure 39_2 can be greater than that of the insulating structure 39_2. Figure 6 The maximum width WC of the insulating structure 39 is small. The light-emitting element 30_2 may include the insulating structure 39_2, which includes the undercut UC formed during the wet etching of the hard mask layer 390. Even if the shape of the insulating structure 39_2 changes, a portion of the top surface of the electrode layer 37 may be exposed, and one end of the light-emitting element 30_2 or the top surface of the electrode layer 37 may contact one of the contact electrodes CNE1 and CNE2.

[0209] In summarizing the specific embodiments, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention. Therefore, the disclosed preferred embodiments of the invention are used only in a general and descriptive sense and not for limiting purposes. Consequently, the actual scope of protection of the invention should be determined by the technical scope of the appended claims.

Claims

1. A light-emitting element, the light-emitting element comprising: The first semiconductor layer is doped with an n-type dopant; The second semiconductor layer is doped with a p-type dopant; A light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer; An electrode layer is disposed on the second semiconductor layer; An insulating structure is disposed on the electrode layer and has a maximum diameter smaller than the diameter of the electrode layer; as well as An insulating film surrounds the side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer. The insulating structure includes: The bottom surface contacts the electrode layer; and The inclined side surface is inclined relative to the bottom surface. The diameter of the insulating structure decreases from the bottom surface to the top surface.

2. The light-emitting element according to claim 1, wherein, The height of the insulating structure is in the range of 500 nm to 1 μm.

3. The light-emitting element according to claim 1, wherein, The maximum diameter of the insulating structure is in the range of 100 nm to 500 nm.

4. The light-emitting element according to claim 1, wherein, The insulating structure includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and The insulating film is a single layer or multiple layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, titanium oxide, zirconium oxide, and hafnium oxide.

5. The light-emitting element according to claim 4, wherein, The thickness of the insulating film is in the range of 10 nm to 200 nm.

6. The light-emitting element according to claim 1, further comprising: A third semiconductor layer is disposed between the first semiconductor layer and the light-emitting layer; A fourth semiconductor layer is disposed between the second semiconductor layer and the light-emitting layer; as well as A fifth semiconductor layer is disposed between the second semiconductor layer and the fourth semiconductor layer. The insulating film also surrounds the side surfaces of the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer.

7. A light-emitting element, the light-emitting element comprising: The first semiconductor layer is doped with an n-type dopant; The second semiconductor layer is doped with a p-type dopant; A light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer; An electrode layer is disposed on the second semiconductor layer; An insulating structure is disposed on the electrode layer and has a maximum diameter smaller than the diameter of the electrode layer; as well as An insulating film surrounds the side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer. The insulating structure includes: The first portion, having the maximum diameter of the insulating structure, includes an inclined side surface, and The second part is connected to the lower part of the first part and has a width smaller than the maximum diameter of the insulating structure.

8. The light-emitting element according to claim 7, wherein, The second part contacts the electrode layer.

9. A method for manufacturing a light-emitting element, the method comprising the following steps: A semiconductor structure is formed on a target substrate, the semiconductor structure comprising multiple semiconductor material layers; A mask layer is formed on the semiconductor structure; The semiconductor structure is etched in a direction perpendicular to the top surface of the target substrate to form component bars, each component bar including an insulating structure and a plurality of semiconductor layers, the insulating structure being formed from a portion of the mask layer; An insulating film is formed around a portion of the side surface of the component rod; as well as Separate the component rod from the insulating film from the target substrate.

10. The method according to claim 9, wherein, The step of forming the mask layer includes: An insulating mask layer is formed on the semiconductor structure; and A metal pattern layer is formed on the insulating mask layer, the metal pattern layer comprising patterns spaced apart from each other, and The insulating structure is formed by etching the insulating mask layer.

11. The method according to claim 10, wherein, The steps of forming the component rod include: Performing a first etching step, the first etching step comprising: etching the insulating mask layer along the metal pattern layer to form a hard mask layer; and etching the semiconductor structure along the hard mask layer; and Perform a second etching step, the second etching step comprising: etching the semiconductor structure etched along the hard mask layer to form the element bar including the insulating structure.

12. The method according to claim 11, wherein, The first etching step includes a dry etching process, and The second etching step includes a wet etching process.

13. The method according to claim 11, wherein, The semiconductor structure is etched to have exposed and angled side surfaces by the first etching step, and The plurality of semiconductor layers of the element rod are formed to have side surfaces perpendicular to the target substrate.

14. The method according to claim 9, wherein, The component rod includes: The first semiconductor layer is doped with an n-type dopant; The second semiconductor layer is doped with a p-type dopant; A light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer; and An electrode layer is disposed on the second semiconductor layer. The insulating structure is formed on the electrode layer, and The insulating film is formed around the side surface of the first semiconductor layer, the side surface of the light-emitting layer, the side surface of the second semiconductor layer, and the side surface of the electrode layer.

15. The method according to claim 13, wherein, The insulating structure is formed with inclined side surfaces, such that the diameter of the insulating structure decreases from the bottom surface to the top surface of the insulating structure.

16. A display device, the display device comprising: First base; The first electrode is disposed on the first substrate; The second electrode is disposed on the first substrate and spaced apart from the first electrode; A first insulating layer is disposed on the first substrate and covers the first electrode and the second electrode; Multiple light-emitting elements are disposed on the first insulating layer, and include a first end disposed on the first electrode and a second end disposed on the second electrode; The first contact electrode makes electrical contact with the first end of the first electrode and the plurality of light-emitting elements; as well as The second contact electrode electrically contacts the second end of the second electrode and the plurality of light-emitting elements. Each of the plurality of light-emitting elements includes: The first semiconductor layer is doped with an n-type dopant; The second semiconductor layer is doped with a p-type dopant; A light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer; An electrode layer is disposed on the second semiconductor layer; An insulating structure is disposed on the electrode layer and has a maximum diameter smaller than the diameter of the electrode layer; and An insulating film surrounds the side surfaces of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer. in, The insulating structure includes a bottom surface and inclined side surfaces, and The diameter of the insulating structure decreases from the bottom surface to the top of the insulating structure.

17. The display device according to claim 16, wherein, The insulating structure includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

18. The display device according to claim 16, further comprising: A first contact surface, a portion of the top surface of the electrode layer and the first contact electrode are in contact with each other at the first contact surface; A second contact surface, a portion of the side surface of the insulating structure and the first contact electrode are in contact with each other at the second contact surface; as well as The third contact surface is where the bottom surface of the first semiconductor layer and the second contact electrode come into contact with each other. The first contact surface is smaller than the third contact surface.

19. The display device according to claim 18, wherein, A space is formed between the insulating structure of each of the plurality of light-emitting elements and the first insulating layer, and The electrode layer includes a surface that is adjacent to the space but does not contact the first contact electrode.

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