Voltage divider circuit for battery voltage and electronic device having the same

Abstract

The present invention discloses a voltage divider circuit for battery voltage and a related electronic device. The voltage divider circuit includes a first and a second level shifter circuit and a controlled voltage divider. The first level shifter circuit selectively performs a first level shift operation on an original enable signal according to the respective voltage levels of a plurality of control signals to generate a first enable signal. The second level shifter circuit selectively performs a second level shift operation on the first enable signal according to the voltage level of the first enable signal to generate a second enable signal. The controlled voltage divider selectively performs a voltage division operation on the battery voltage according to the voltage level of the second enable signal to generate a divided voltage of the battery voltage as the output of the voltage divider circuit. Compared with the conventional architecture, the voltage divider circuit of the present invention is robust to various operating modes of a microcontroller, and does not require an external MOSFET and an external resistor when implemented as an integrated voltage divider circuit, and can achieve the goals of low cost and low leakage current.

Description

Technical Field

[0001] The present invention relates to voltage control, and more particularly to a voltage divider circuit for a battery voltage and an electronic device having the voltage divider circuit. Background Art

[0002] In the related art, various voltage divider circuits for battery voltage in portable electronic devices are proposed, but there are certain problems. For example, a first voltage divider circuit has at least one external metal-oxide-semiconductor field effect transistor (MOSFET) and at least one external resistor located outside a chip, and at least one additional current path is added, wherein the at least one external MOSFET and the at least one external resistor increase the relevant cost, and the current leakage caused by the at least one additional current path increases the power consumption. For another example, a second voltage divider circuit has components that have been integrated into a chip, but is not robust to the complex operating modes of a microcontroller. Therefore, an integrated voltage divider circuit that is robust to various operating modes of the microcontroller is needed to enhance the overall performance of the portable electronic device. Summary of the invention

[0003] An object of the present invention is to disclose a voltage divider circuit for a battery voltage and an electronic device having the voltage divider circuit to solve the above-mentioned problem.

[0004] Another object of the present invention is to disclose a voltage divider circuit for a battery voltage and an electronic device having the voltage divider circuit, so as to achieve optimal performance of the electronic device without side effects or with less possibility of side effects.

[0005] At least one embodiment of the present invention discloses a voltage divider circuit for a battery voltage, wherein the voltage divider circuit is located in an electronic device, and the battery voltage is the voltage of a battery of the electronic device. The voltage divider circuit may include a first level shifter circuit operated based on a first power supply voltage of the electronic device, and include a second level shifter circuit operated based on the battery voltage and a controlled voltage divider. The second level shifter circuit is coupled to the first level shifter circuit, and the controlled voltage divider is coupled to the second level shifter circuit. For example, the first level shifter circuit can be used to receive a plurality of control signals generated in the electronic device, and selectively perform a first level shifting operation on a voltage divider enabling signal according to the respective voltage levels of the plurality of control signals to generate a first enabling signal in the voltage domain of the first power supply voltage for enabling control of the voltage divider circuit. In addition, the second level shifter circuit can be used to receive the first enable signal, and selectively perform a second level shift operation on the first enable signal according to the voltage level of the first enable signal to generate a second enable signal in the voltage domain of the battery voltage for enabling control of the voltage divider circuit. In addition, the controlled voltage divider can be used to receive the second enable signal, and selectively perform a voltage dividing operation on the battery voltage according to the voltage level of the second enable signal to generate a divided voltage of the battery voltage as the output of the voltage divider circuit.

[0006] At least one embodiment of the present invention discloses an electronic device having the voltage divider circuit described above. The electronic device may further include: a microcontroller for controlling the operation of the electronic device; at least one control signal generator for generating the plurality of control signals; and at least one power supply circuit for generating at least the first power supply voltage.

[0007] Compared to the conventional architecture, the voltage divider circuit of the present invention is robust to various operating modes of the microcontroller, and does not require external MOSFETs and external resistors when implemented as an integrated voltage divider circuit. In addition, the implementation according to the embodiments of the present invention can achieve low cost, low leakage current and other goals. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 4 is a schematic diagram of a voltage divider circuit for a battery voltage according to an embodiment of the present invention.

[0009] Figure 2 According to an embodiment of the present invention, Figure 1 Implementation details of a first level shifter circuit in the voltage divider circuit are shown.

[0010] Figure 3 According to an embodiment of the present invention, Figure 1 Implementation details of a second level shifter circuit in the voltage divider circuit are shown.

[0011] Figure 4 According to an embodiment of the present invention, Figure 1 Implementation details of a controlled voltage divider in the voltage divider circuit shown.

[0012] Figure 5 According to an embodiment of the present invention, Figure 1 The relevant signals in the voltage divider circuit shown.

[0013] Figure 6 According to another embodiment of the present invention, Figure 1 The relevant signals in the voltage divider circuit shown.

[0014] Figure 7 According to another embodiment of the present invention, Figure 1 The relevant signals in the voltage divider circuit shown.

[0015] Figure 8 According to an embodiment of the present invention, a Figure 1 A schematic diagram of an electronic device showing a voltage divider circuit.

[0016] The reference numerals are described as follows:

[0017] 100 Voltage Divider Circuit

[0018] LVST1 first level shifter circuit

[0019] LVST2 Second Level Shifter Circuit

[0020] DIV controlled voltage divider

[0021] VCC1, VCCK supply voltage

[0022] VBAT battery voltage

[0023] POR_N_HV Power-on reset signal

[0024] ISO_N_HV isolated signal

[0025] EN_LV Raw enable signal

[0026] EN_HV First enable signal

[0027] ENB_VBAT Second enable signal

[0028] VBAT_DIV divided voltage

[0029] GND Ground voltage

[0030] INV1, INV2, INV3, INV4, INV7, 122 Inverter

[0031] 112 Logic Circuits

[0032] 112N NAND Gate

[0033] 114 Switch

[0034] 116 First level shifter

[0035] 126 Second level shifter

[0036] MP1, MP2, MP3, MP4, MP5, MP6, MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8 transistors

[0037] R1, R2, R3, R4, R5, R6 resistors

[0038] O1, O2, O3, O4 nodes

[0039] ENB inverted signal

[0040] RESET, RESET_N reset signal

[0041] I_add leakage current

[0042] Current_LVST2, Current_DIV Current

[0043] 10 Electronic devices

[0044] 12 Microcontroller

[0045] 14 Control signal generator

[0046] 16 Power supply circuit

[0047] 18 Batteries DETAILED DESCRIPTION

[0048] Figure 1 FIG. 1 is a schematic diagram of a voltage divider circuit 100 for a battery voltage VBAT according to an embodiment of the present invention, wherein the voltage divider circuit 100 may be located in an electronic device, and the battery voltage VBAT may be the voltage of a battery of the electronic device. Figure 1 As shown, the voltage divider circuit 100 may include a first level shifter circuit LVST1 operated based on a power voltage VCC1 of the electronic device, and include a second level shifter circuit LVST2 operated based on a battery voltage VBAT and a controlled voltage divider DIV. The second level shifter circuit LVST2 may be coupled to the first level shifter circuit LVST1, and the controlled voltage divider DIV may be coupled to the second level shifter circuit LVST2.

[0049] According to this embodiment, the first level shifter circuit LVST1 can receive a plurality of control signals generated in the electronic device, such as a power-on reset (POR) signal POR_N_HV of the electronic device and a microcontroller (not shown) of the electronic device. Figure 1 ), wherein the power-on reset signal POR_N_HV can be configured to control the power-on reset of the electronic device, and the isolation signal ISO_N_HV can be configured to control the power isolation of the microcontroller. The first level shifter circuit LVST1 can selectively shift a power supply voltage VCCK (not shown) according to the respective voltage levels of the plurality of control signals. Figure 1 ) performs a first level shift operation on an original enable signal EN_LV in the voltage domain DOMAIN_VCCK of the power supply voltage VCC1 to generate a first enable signal EN_HV in the voltage domain DOMAIN_VCC1 of the power supply voltage VCC1 for enabling control of the voltage divider circuit 100. For example, the voltage level of the first enable signal EN_HV may be limited by the voltage level of the power supply voltage VCC1, and in particular, the high voltage level of the first enable signal EN_HV may be equal to or slightly lower than the voltage level of the power supply voltage VCC1. In addition, the second level shifter circuit LVST2 may receive the first enable signal EN_HV, and selectively perform a second level shift operation on the first enable signal EN_HV according to the voltage level of the first enable signal EN_HV to generate a second enable signal ENB_VBAT in the voltage domain DOMAIN_VBAT of the battery voltage VBAT for enabling control of the voltage divider circuit 100. For example, the voltage level of the second enable signal ENB_VBAT may be limited by the voltage level of the battery voltage VBAT, and in particular, the high voltage level of the second enable signal ENB_VBAT may be equal to or slightly lower than the voltage level of the battery voltage VBAT. In addition, the controlled voltage divider DIV may receive the second enable signal ENB_VBAT, and selectively perform a voltage division operation on the battery voltage VBAT according to the voltage level of the second enable signal ENB_VBAT to generate a divided voltage VBAT_DIV of the battery voltage VBAT as the output of the voltage divider circuit 100.

[0050] For ease of understanding, the original enable signal EN_LV and the first enable signal EN_HV can be active high, and the high logic level "1" and the low logic level "0" of each of these signals (for example, its high voltage level and low voltage level) respectively represent enabling and disabling the function controlled by this signal, wherein the first level shifter circuit LVST1 can convert the high logic level "1" and the low logic level "0" of the original enable signal EN_LV in the voltage domain DOMAIN_VCCK into the high logic level "1" and the low logic level "0" of the first enable signal EN_HV in the voltage domain DOMAIN_VCC1, respectively, but the present invention is not limited to this. In addition, the second enable signal ENB_VBAT can be active low, and the low logic level "0" and the high logic level "1" (e.g., the low voltage level and the high voltage level) of the second enable signal ENB_VBAT respectively represent enabling and disabling the function controlled by this signal, wherein the second level shifter circuit LVST2 can convert the high logic level "1" and the low logic level "0" of the first enable signal EN_HV in the voltage domain DOMAIN_VCC1 into the low logic level "0" and the high logic level "1" of the second enable signal ENB_VBAT in the voltage domain DOMAIN_VBAT, respectively, but the present invention is not limited thereto. According to some embodiments, the original enable signal EN_LV, the first enable signal EN_HV, and the second enable signal ENB_VBAT can be changed. For example, any one of the original enable signal EN_LV and the first enable signal EN_HV can be implemented as active low. For another example, the second enable signal ENB_VBAT can be implemented as active high.

[0051] According to some embodiments, the voltage divider circuit 100 may operate according to a first reference voltage such as a ground voltage GND and a plurality of second reference voltages such as a battery voltage VBAT and power voltages VCC1, VCCK, etc. For example, the power voltages VCC1 and VCCK may represent the main power and the core power of the microcontroller, respectively, and the respective voltage domains DOMAIN_VCC1 and DOMAIN_VCCK of the power voltages VCC1 and VCCK may be respectively referred to as the main voltage domain and the core voltage domain, wherein the power voltage VCC1 is typically greater than the power voltage VCCK, and the electronic device may utilize a voltage regulator therein such as a low dropout (LDO) regulator to regulate the power voltage VCC1 to generate the power voltage VCCK as the core power for driving the digital domain of the microcontroller. In addition, the original enable signal EN_LV, the first enable signal EN_HV and the second enable signal ENB_VBAT can be regarded as voltage divider enable signals, and in particular, can be voltage divider enable signals corresponding to different voltage domains DOMAIN_VCCK, DOMAIN_VCC1 and DOMAIN_VBAT. For example, the original enable signal EN_LV can be a software command signal received from the microcontroller.

[0052] According to some embodiments, the voltage divider circuit 100 may include transistors of different types of channels, such as transistors of a first type and a second type. Figure 1 The illustrated architecture may employ certain types of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), such as P-type and N-type MOSFETs, but the present invention is not limited thereto.

[0053] Figure 2 According to an embodiment of the present invention, Figure 1Implementation details of the first level shifter circuit LVST1 in the voltage divider circuit 100 are shown. The first level shifter circuit LVST1 may include: at least one logic circuit (e.g., one or more logic circuits), which may be collectively referred to as logic circuit 112; at least one switch (e.g., one or more switches), which may be collectively referred to as switch 114, coupled to the logic circuit 112; and a first level shifter 116 coupled to the switch 114. For example, the logic circuit 112 may include a NAND gate 112N and an inverter INV3 coupled to the NAND gate 112N, the switch 114 may include transistors MN1 and MN2, and the first level shifter 116 may include transistors MP1, MP2, MN3 and MN4 and an inverter INV2, wherein respective control terminals such as gate terminals of the transistors MP2 and MP1 are respectively coupled to nodes O1 and O2 below the transistors MP1 and MP2, and respective control terminals such as gate terminals of the transistors MN4 and MN3 are respectively coupled to the input terminal and output terminal of the inverter INV2. The first level shifter circuit LVST1 may further include inverters INV1 and INV4 respectively coupled to the inverter INV1 and the original enable signal EN_LV, another switch such as transistor MN5, and a resistor R1. An input terminal of the first level shifter 116, such as an input terminal of inverter INV2, is coupled to an output terminal of inverter INV1, respective first terminals of transistor MN5 and resistor R1 are coupled to an output terminal of the first level shifter 116, such as a terminal located at or near node O2, and a control terminal of transistor MN5, such as a gate terminal, is coupled to an output terminal of inverter INV4.

[0054] The logic circuit 112 can be used to perform logic control according to the power-on reset signal POR_N_HV and the isolation signal ISO_N_HV to generate at least one logic signal such as a reset signal RESET, the above-mentioned at least one switch such as the transistors MN1 and MN2 can be used to operate according to the above-mentioned at least one logic signal such as the reset signal RESET to selectively turn on at least one signal path such as a first signal path between the transistors MP1 and MN3 and a second signal path between the transistors MP2 and MN4, and the first level shifter 116 can be used to selectively perform the first level shift operation on the original enable signal EN_LV under the control of the switch 114 to generate the first enable signal EN_HV, wherein whether the first level shifter 116 performs the first level shift operation on the original enable signal EN_LV corresponds to whether the switch 114 turns on the above-mentioned at least one signal path such as the first signal path and the second signal path. When the switch 114 conducts the at least one signal path, the first level shifter 116 performs the first level shift operation on the original enable signal EN_LV to generate the first enable signal EN_HV, such as the first enable signal EN_HV with a high logic level "1". For example, when the power-on reset signal POR_N_HV indicates a power-on reset stage of the electronic device, the logic circuit 112 can control the switch 114 to avoid conducting the at least one signal path through the at least one logic signal such as the reset signal RESET. When the isolation signal ISO_N_HV indicates a standby mode of the electronic device, the logic circuit 112 can control the switch 114 to avoid conducting the at least one signal path through the at least one logic signal such as the reset signal RESET.

[0055] In particular, in the logic circuit 112, the NAND gate 112N can generate a first logic signal according to the power-on reset signal POR_N_HV and the isolation signal ISO_N_HV, and the inverter INV3 can generate an inverted signal of the first logic signal according to the first logic signal as the at least one logic signal such as the reset signal RESET. In this way, if the power-on reset signal POR_N_HV indicates the power-on reset stage of the electronic device, or the isolation signal ISO_N_HV indicates the standby mode of the electronic device, the logic circuit 112 can control the switch 114 to avoid conducting the at least one signal path through the at least one logic signal such as the reset signal RESET to reset the first level shifter 116; otherwise, the logic circuit 112 can control the switch 114 to conduct the at least one signal path through the at least one logic signal such as the reset signal RESET to allow the first level shifter circuit LVST1 to perform the first level shift operation on the original enable signal EN_LV to generate the first enable signal EN_HV. For example, the power-on reset signal POR_N_HV, the isolation signal ISO_N_HV and the reset signal RESET can be active at a low voltage, and the low logic level "0" and the high logic level "1" (for example, the low voltage level and the high voltage level) of each of these signals respectively represent enabling and disabling the function controlled by this signal; and the reset signal RESET_N (such as an inverted signal of the reset signal RESET) can be active at a high voltage, and the high logic level "1" and the low logic level "0" (for example, the high voltage level and the low voltage level) of the reset signal RESET_N respectively represent enabling and disabling the function controlled by this signal. When the power-on reset signal POR_N_HV has a low logic level “0” (which indicates that the electronic device is in the power-on reset stage) and / or the isolation signal ISO_N_HV has a low logic level “0” (which indicates that the power supply of the microcontroller is isolated, for example, the electronic device is in the standby mode), the reset signals RESET and RESET_N respectively have a low logic level “0” and a high logic level “1” to reset the first level shifter 116. Otherwise, when both transistors MN1 and MN2 are turned on so that the respective lower terminals (or nodes O1 and O2) of transistors MP1 and MP2 are respectively conducted to the respective upper terminals of transistors MN3 and MN4, the first level shifter 116 can operate normally to allow the first level shifter circuit LVST1 to perform the first level shift operation on the original enable signal EN_LV to generate the first enable signal EN_HV in the voltage domain DOMAIN_VCC1 of the power supply voltage VCC1.

[0056] Figure 3 According to an embodiment of the present invention, Figure 1Implementation details of the second quasi-shifter circuit LVST2 in the voltage divider circuit 100 shown. The second quasi-shifter circuit LVST2 may include a second quasi-shifter 126 coupled to the first quasi-shifter circuit LVST1, and a resistor R2 disposed on the second quasi-shifter 126, and includes an inverter INV7 coupled to the second quasi-shifter 126. The second quasi-shifter 126 may include transistors MP4, MP5, MN7, and MN8, and includes a set of transistors MP3 and MN6 coupled to each other and coupled between the battery voltage VBAT and the ground voltage GND to form an inverter 122 in the second quasi-shifter 126, wherein respective control terminals such as gate terminals of transistors MP5 and MP4 are respectively coupled to nodes O3 and O4 below transistors MP4 and MP5, and respective control terminals such as gate terminals of transistors MN7 and MN8 are respectively coupled to the input terminal and the output terminal of the inverter 122 to receive the first enable signal EN_HV and its inverted signal ENB. The second quasi-shifter circuit LVST2 may selectively perform the second quasi-shift operation on the first enable signal EN_HV according to the voltage level of the first enable signal EN_HV by using the second quasi-shifter 126 to generate an intermediate enable signal on node O4, and perform an inversion operation on this intermediate enable signal by using the inverter INV7 to generate an inverted signal of the intermediate enable signal as the second enable signal ENB_VBAT. Additionally, the resistor R2 is disposed on a current path passing through the set of transistors MP3 and MN6 and between the battery voltage VBAT and the ground voltage GND. The resistor R2 may be used to limit any possible leakage current I_add on this current path for at least one of a plurality of operating modes of the electronic device. The parameters (e.g., size) of the resistor R2 and the transistor MP3 may be properly designed to block any possible leakage current I_add, especially in the case where VCC1 < VBAT. For example, the leakage current I_add can be represented by the following equation:

[0057] I_add = (VBAT - VCC1 - Vthp) / R2;

[0058] where Vthp represents the threshold voltage of the transistor MP3, such as 0.5 volts (V), but the present invention is not limited thereto. According to some embodiments, the threshold voltage may be varied.

[0059] Figure 4 According to an embodiment of the present invention, shown in Figure 1Implementation details of the controlled voltage divider DIV in the voltage divider circuit 100 shown. The controlled voltage divider DIV may include a set of resistors in series coupled between the battery voltage VBAT and the ground voltage GND, such as resistors {R3, R4, R5, R6}, and a switch, such as transistor MP6, disposed on a current path passing through the set of resistors and between the battery voltage VBAT and the ground voltage GND, wherein the respective resistance values ​​of the resistors {R3, R4, R5, R6} may be equal to each other, but the present invention is not limited thereto. For example, the type of the switch (such as transistor MP6), the number of resistors in the set of resistors, the resistance values ​​of the resistors in the set of resistors, and / or the position of the switch on the current path may be varied. In addition, the set of resistors, such as resistors {R3, R4, R5, R6}, may be used to selectively perform the voltage division operation on the battery voltage VBAT to generate a divided voltage VBAT_DIV of the battery voltage VBAT as the output of the voltage divider circuit 100. The switch, such as transistor MP6 , may be operable to selectively conduct the current path according to the second enable signal ENB_VBAT.

[0060] in accordance with Figures 2 to 4In the structure shown, when any one of the power-on reset signal POR_N_HV and the isolation signal ISO_N_HV has a low logic level "0", the reset signal RESET has a low logic level "0" to turn off the transistors MN1 and MN2, and the reset signal RESET_N has a high logic level "1" to turn on the transistor MN5, so that the first enable signal EN_HV has a low logic level "0" (for example, equal to or slightly greater than the ground voltage GND) to turn on the transistor MP3 and turn off the transistors MN6 and MN7, wherein the inverted signal ENB of the first enable signal EN_HV has a high logic level "1" to turn on the transistor MN8. In this case, the respective voltage levels of the nodes O3 and O4 are a high logic level "1" and a low logic level "0", respectively. Since the intermediate enable signal on the node O4 has a low logic level "0", the second enable signal ENB_VBAT has a high logic level "1" to turn off the transistor MP6, and thus turns off the controlled voltage divider DIV. In addition, when each of the power-on reset signal POR_N_HV and the isolation signal ISO_N_HV has a high logic level "1", the reset signal RESET has a high logic level "1" to turn on the transistors MN1 and MN2, and the reset signal RESET_N has a low logic level "0" to turn off the transistor MN5, so that the logic level of the first enable signal EN_HV corresponds to the logic level of the original enable signal EN_LV. For example, in the case where the original enable signal EN_LV has a high logic level "1", the first enable signal EN_HV also has a high logic level "1" (for example, equal to or slightly less than the power supply voltage VCC1) to turn off the transistor MP3 and turn on the transistors MN6 and MN7, wherein the inverted signal ENB of the first enable signal EN_HV has a low logic level "0" to turn off the transistor MN8. In this case, the voltage levels of the nodes O3 and O4 are respectively a low logic level "0" and a high logic level "1". Since the intermediate enable signal on the node O4 has a high logic level “1”, the second enable signal ENB_VBAT has a low logic level “0” to turn on the transistor MP6, and thus turn on the controlled voltage divider DIV. For another example, in the case where the original enable signal EN_LV has a low logic level “0”, the first enable signal EN_HV also has a low logic level “0” (e.g., equal to or slightly greater than the ground voltage GND) to turn on the transistor MP3 and turn off the transistors MN6 and MN7, wherein the inverted signal ENB of the first enable signal EN_HV has a high logic level “1” to turn on the transistor MN8. In this case, the respective voltage levels of the nodes O3 and O4 are a high logic level “1” and a low logic level “0”, respectively. Since the intermediate enable signal on the node O4 has a low logic level “0”, the second enable signal ENB_VBAT has a high logic level “1” to turn off the transistor MP6, and thus turn off the controlled voltage divider DIV.

[0061] based on Figures 1 to 4 In the illustrated embodiment, the multi-stage architecture formed by the first level shifter circuit LVST1, the second level shifter circuit LVST2, and the controlled voltage divider DIV allows the entire voltage divider circuit 100 to be implemented in a chip without any external components located outside the chip. Compared to the conventional architecture, the voltage divider circuit of the present invention is robust to various operating modes of the microcontroller, and does not require external MOSFETs and external resistors when implemented as an integrated voltage divider circuit, and can achieve low cost, low leakage current, etc.

[0062] Figure 5 According to an embodiment of the present invention, Figure 1 The related signals in the voltage divider circuit are shown, wherein the horizontal axis t represents time, and its unit is millisecond (ms). In this embodiment, the battery voltage VBAT and the original enabling signal EN_LV are respectively shown in volts (V), and the divided voltage VBAT_DIV, the current Current_LVST2 consumed by the second level shifter circuit LVST2, and the current Current_DIV consumed by the controlled voltage divider DIV are respectively shown in millivolts (mV), picoamperes (pA), and microamperes (μA). For example, VBAT = 1.8V and VCC1 = 3.6V. After the original enable signal EN_LV is pulled high from 0.0V at t=1.0ms, the battery voltage VBAT, the original enable signal EN_LV, the divided voltage VBAT_DIV, the current Current_LVST2 and the current Current_DIV at t=1.00080142ms may be 1.8V, 1.2V, 449.747mV, -14.0367pA and 44.6961μA respectively.

[0063] Figure 6 According to another embodiment of the present invention, Figure 1The relevant signals in the voltage divider circuit shown, where the horizontal axis t represents time and its unit is millisecond (ms). In this embodiment, the battery voltage VBAT and the original enable signal EN_LV are respectively plotted in volts (V), and the divided voltage VBAT_DIV, the current Current_LVST2, and the current Current_DIV are respectively plotted in millivolts (mV), picoamperes (pA), and microamperes (μA). For example, VBAT = 3.3V and VCC1 = 3.3V. After the original enable signal EN_LV is pulled high from 0.0V at t = 1.0 ms, the magnitudes of the battery voltage VBAT, the original enable signal EN_LV, the divided voltage VBAT_DIV, the current Current_LVST2, and the current Current_DIV at t = 1.00081697 ms can be 3.3V, 1.2V, 824.759 mV, 134.282 pA, and 81.9766 μA respectively.

[0064] Figure 7 According to another embodiment of the present invention, shown in Figure 1 The relevant signals in the voltage divider circuit shown, where the horizontal axis t represents time and its unit is millisecond (ms). In this embodiment, the battery voltage VBAT and the original enable signal EN_LV are respectively plotted in volts (V), the divided voltage VBAT_DIV is plotted in millivolts (mV), and the currents Current_LVST2 and Current_DIV are respectively plotted in microamperes (μA). For example, VBAT = 3.6V and VCC1 = 1.8V. After the original enable signal EN_LV is pulled high from 0.0V at t = 1.0 ms, the magnitudes of the battery voltage VBAT, the original enable signal EN_LV, the divided voltage VBAT_DIV, the current Current_LVST2, and the current Current_DIV at t = 1.00080142 ms can be 3.6V, 1.2V, 899.652 mV, 1.1281 μA, and 89.4375 μA respectively.

[0065] According to some embodiments, the current Current_LVST2 may represent the leakage current I_add, where Figure 5 in the case where VBAT < VCC1 and Figure 6 in the case where VBAT = VCC1, the leakage current I_add can be ignored and regarded as zero, and only Figure 7There is a slight leakage current I_add (e.g., I_add=Current_LVST2=1.1281μA) when VBAT>VCC1 in the conventional architecture. Even in the case of VBAT>VCC1, the leakage current I_add can be easily limited by the resistor R2 having a smaller resistance value than the conventional architecture. For example, the resistance value of the resistor R2 can be only 100kΩ (kilo-ohm). However, in the conventional architecture, if such a small leakage current such as I=1.1281μA is to be achieved with the same battery voltage VBAT=3.6V, the resistance value of the resistor required by the conventional architecture can be expressed as follows:

[0066] VBAT / I = ((3.6V) / (1.1281μA))≈3.2MΩ (mega-ohm);

[0067] The resistance value is large, which means that an external resistor is required. In addition, the conventional architecture still has significant leakage current when VBAT≤VCC1. Therefore, the voltage divider circuit 100 of the present invention is much better than the conventional architecture, especially, it has the advantages of low cost, low leakage current, etc.

[0068] Figure 8 According to an embodiment of the present invention, a Figure 1Schematic diagram of an electronic device 10 with a voltage divider circuit 100 is shown. The electronic device 10 may include a microcontroller 12, at least one control signal generator such as a control signal generator 14, at least one power supply circuit such as a power supply circuit 16, a battery 18, and the voltage divider circuit 100, wherein the electronic device 10, the microcontroller 12, and the battery 18 may be used as examples of the above-mentioned electronic device, the above-mentioned microcontroller, and the above-mentioned battery, respectively. The microcontroller 12 may be used to control the operation of the electronic device 10, the control signal generator 14 may be used to generate the plurality of control signals such as a power-on reset signal POR_N_HV and an isolation signal ISO_N_HV, and the power supply circuit 16 may be used to generate power supply voltages VCC1, VCCK, etc. For example, when the microcontroller 12 enables the voltage divider circuit 100, the voltage divider circuit 100 outputs a voltage divider voltage VBAT_DIV of the battery voltage VBAT, so as to allow the electronic device 10 to use an analog-to-digital converter (ADC) therein to receive and monitor the voltage divider voltage VBAT_DIV to monitor the battery voltage VBAT without any input signal saturation problem, but the present invention is not limited thereto. In addition, the voltage divider circuit 100 and the microcontroller 12 can be integrated into the same chip (or die), without the need to implement any external MOSFET or any external resistor located outside the chip (or die) for the voltage divider circuit 100. For the sake of simplicity, similar contents in this embodiment are not repeated here.

[0069] The voltage divider circuit of the present invention can avoid any significant leakage current as commonly seen in the related art in various situations. Regardless of any of the above multiple situations of the electronic device, such as power-on / power-on reset (e.g., when the power-on reset signal POR_N_HV has a low logic level "0", the first enable signal EN_HV has a low logic level "0"), standby mode (e.g., when the isolation signal ISO_N_HV has a low logic level "0", the first enable signal EN_HV has a low logic level "0"), battery voltage (VBAT) mode (e.g., when the power supply voltage VCC1 is turned off or not ready, the resistor R1 pulls down the first enable signal EN_HV to the ground voltage GND, as if it has a low logic level "0"), etc., the voltage divider circuit 100 can safely set its output to zero without any significant leakage current.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A voltage divider circuit for a battery voltage, characterized in that: The voltage divider circuit is located in an electronic device, the battery voltage is the voltage of a battery of the electronic device, and the voltage divider circuit comprises: a first level shifter circuit operated based on a first power supply voltage of the electronic device, for receiving a plurality of control signals generated in the electronic device, and selectively performing a first level shift operation on an original enable signal according to respective voltage levels of the plurality of control signals to generate a first enable signal in a voltage domain of the first power supply voltage for enabling control of the voltage divider circuit; a second level shifter circuit operated based on the battery voltage, coupled to the first level shifter circuit, for receiving the first enable signal and selectively performing a second level shift operation on the first enable signal according to the voltage level of the first enable signal to generate a second enable signal in the voltage domain of the battery voltage for enabling control of the voltage divider circuit; as well as A controlled voltage divider operated based on the battery voltage is coupled to the second level shifter circuit, and is used to receive the second enable signal and selectively perform a voltage division operation on the battery voltage according to the voltage level of the second enable signal to generate a divided voltage of the battery voltage as an output of the voltage divider circuit.

2. The voltage divider circuit according to claim 1, wherein: The first power supply voltage represents the main power supply of a microcontroller of the electronic device.

3. The voltage divider circuit according to claim 1, wherein: The multiple control signals include a power-on reset signal of the electronic device and an isolation signal of a microcontroller of the electronic device, wherein the power-on reset signal is configured to control power-on reset of the electronic device, and the isolation signal is configured to control power isolation of the microcontroller.

4. The voltage divider circuit according to claim 3, characterized in that The first level shifter circuit comprises: At least one logic circuit, used for performing logic control according to the power-on reset signal and the isolation signal to generate at least one logic signal; at least one switch, coupled to the at least one logic circuit, for operating according to the at least one logic signal to selectively conduct at least one signal path; as well as A first level shifter is coupled to the at least one switch, and is used to selectively perform the first level shift operation on the original enable signal under the control of the at least one switch to generate the first enable signal, wherein whether the first level shifter performs the first level shift operation on the original enable signal corresponds to whether the at least one switch turns on the at least one signal path.

5. The voltage divider circuit according to claim 4, characterized in that When the power-on reset signal indicates a power-on reset stage of the electronic device, the at least one logic circuit controls the at least one switch through the at least one logic signal to avoid conducting the at least one signal path.

6. The voltage divider circuit according to claim 4, characterized in that When the isolation signal indicates a standby mode of the electronic device, the at least one logic circuit controls the at least one switch via the at least one logic signal to avoid conducting the at least one signal path.

7. The voltage divider circuit according to claim 4, characterized in that If the power-on reset signal indicates a power-on reset stage of the electronic device, or the isolation signal indicates a standby mode of the electronic device, the at least one logic circuit controls the at least one switch through the at least one logic signal to avoid conducting the at least one signal path; otherwise, the at least one logic circuit controls the at least one switch through the at least one logic signal to conduct the at least one signal path.

8. The voltage divider circuit according to claim 4, characterized in that The at least one logic circuit comprises: a NAND gate, used for generating a first logic signal according to the power-on reset signal and the isolation signal; and An inverter is coupled to the NAND gate and is used for generating the at least one logic signal according to the first logic signal.

9. The voltage divider circuit according to claim 4, characterized in that The first level shifter circuit further comprises: an inverter, coupled to the at least one logic circuit, for generating another logic signal according to the at least one logic signal; and Another switch is coupled to the inverter and is used to operate according to the another logic signal to selectively conduct a signal path between the output of the first level shifter circuit and a ground voltage.

10. The voltage divider circuit according to claim 4, wherein: When the at least one switch turns on the at least one signal path, the first level shifter performs the first level shift operation on the original enabling signal to generate the first enabling signal.

11. The voltage divider circuit according to claim 1, wherein: The second level shifter circuit comprises: a second level shifter, coupled to the first level shifter circuit, for selectively performing the second level shift operation on the first enable signal according to the voltage level of the first enable signal to generate the second enable signal, wherein the second level shifter comprises a group of transistors coupled to each other and coupled between the battery voltage and a ground voltage to form an inverter in the second level shifter; as well as A resistor is provided in a current path passing through the set of transistors and between the battery voltage and the ground voltage, for limiting any possible leakage current in the current path for at least one operation mode among a plurality of operation modes of the electronic device.

12. The voltage divider circuit according to claim 11, wherein: The plurality of control signals include a power-on reset signal of the electronic device and an isolation signal of a microcontroller of the electronic device, wherein the power-on reset signal is configured to control a power-on reset of the electronic device, and the isolation signal is configured to control power isolation of the microcontroller; and the first level shifter circuit includes: At least one logic circuit, used for performing logic control according to the power-on reset signal and the isolation signal to generate at least one logic signal; at least one switch, coupled to the at least one logic circuit, for operating according to the at least one logic signal to selectively conduct at least one signal path; as well as a first level shifter, coupled to the at least one switch, for selectively performing the first level shift operation on the original enable signal under the control of the at least one switch to generate the first enable signal; The multi-stage architecture formed by the first level shifter circuit, the second level shifter circuit, and the controlled voltage divider allows the entire voltage divider circuit to be implemented in a chip without requiring any external components outside the chip.

13. The voltage divider circuit according to claim 1, wherein: The controlled voltage divider comprises: a group of resistors connected in series, coupled between the battery voltage and a ground voltage, for selectively performing the voltage division operation on the battery voltage to generate the divided voltage of the battery voltage as the output of the voltage divider circuit; as well as A switch is provided on a current path passing through the resistor group and between the battery voltage and the ground voltage, and is used to operate according to the second enabling signal to selectively conduct the current path.

14. The electronic device comprising the voltage divider circuit according to claim 1, wherein: The electronic device further comprises: a microcontroller for controlling the operation of the electronic device; at least one control signal generator, configured to generate the plurality of control signals; and At least one power supply circuit is used to generate at least the first power supply voltage.

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