Semiconductor device integrated with temperature detection diode, battery system and electrical equipment

Abstract

The present disclosure provides a semiconductor device integrated with a temperature detection diode, comprising: a first cell region in which a charge control field effect transistor is formed, and a gate of the charge control field effect transistor is configured to receive a control signal to be in an on state; and a second cell region in which a temperature detection diode is formed, and the temperature detection diode is configured to detect a current temperature of the semiconductor device; wherein, the first cell region and the second cell region are disposed adjacent to each other. The present disclosure further provides a battery system and an electrical device.

Description

Technical Field

[0001] The present disclosure relates to the technical field of current detection / measurement, and particularly to a semiconductor device integrated with a temperature detection diode, a battery system, and an electrical device. Background Art

[0002] In the prior art, electric vehicles, mobile phones, etc. use battery packs (or battery cells, battery modules) to provide electrical energy. It is necessary to discharge the battery pack to provide electrical energy for the load, and it is also necessary to connect an external charger to charge the battery pack.

[0003] During the charging and discharging processes of the battery pack, it is necessary to detect the charging current and the discharging current, and it is also necessary to detect the temperature inside the battery module to avoid safety accidents.

[0004] In the prior art, the method of current detection usually sets a detection resistor in the battery pack circuit. However, the setting of the detection resistor will inevitably cause energy loss, heat generation, etc., resulting in many adverse consequences.

[0005] In addition, the magnitude of the charging and discharging current often changes, and it is necessary to accurately measure the charging and discharging current.

[0006] In the prior art, the charging and discharging current is generally measured by using a current detection resistor R sns However, due to the use of R sns higher requirements are imposed on the on-resistance of the charging and discharging control FET, making the manufacture of the charging and discharging control FET more complicated. Summary of the Invention

[0007] To solve at least one of the above technical problems, the present disclosure provides a semiconductor device integrated with a temperature detection diode, a battery system, and an electrical device.

[0008] According to one aspect of the present disclosure, there is provided a semiconductor device integrated with a temperature detection diode, including:

[0009] A first cell region that forms a charging control field effect transistor, and the gate of the charging control field effect transistor is used to receive a control signal to be in a conducting state; and a second cell region that forms a temperature detection diode, and the temperature detection diode detects the current temperature of the semiconductor device; wherein, the first cell region and the second cell region are disposed adjacent to each other.

[0010] In the semiconductor device integrated with a temperature detection diode according to at least one embodiment of the present disclosure, the first cell region further forms a discharging control field effect transistor, and the gate of the discharging control field effect transistor is used to receive a control signal to be in a conducting state.

[0011] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The first cell region and the second cell region have a common metal substrate. The second cell region further forms a first metal electrode, and the first metal electrode serves as the anode of the temperature detection diode. The metal substrate can serve as the cathode of the temperature detection diode.

[0012] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The second cell region further includes a P-type silicon layer and an N-type silicon layer. The P-type silicon layer is disposed adjacent to the first metal electrode, and the N-type silicon layer is disposed adjacent to the metal substrate.

[0013] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The first metal electrode is in contact with the P-type silicon layer via more than two contact holes.

[0014] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. A P-type heavily doped region is formed at the bottom of the contact hole.

[0015] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The second cell region is functionally separated from the first cell region via at least one isolation trench.

[0016] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The isolation trench extends from an oxide dielectric layer under the first metal electrode, passes through the P-type silicon layer and extends into the N-type silicon layer.

[0017] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The isolation trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0018] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The first cell region further includes a P-type silicon layer and an N-type silicon layer. The first cell region and the second cell region share the P-type silicon layer and the N-type silicon layer. The metal substrate can serve as the drain of the charge control field effect transistor. A second metal electrode and a third metal electrode are disposed on a side of the P-type silicon layer away from the metal substrate. The second metal electrode can serve as the source of the charge control field effect transistor, and the third metal electrode can serve as the gate of the charge control field effect transistor.

[0019] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure. The third metal electrode is in contact with a third trench extending into the N-type silicon layer via a P-type silicon layer through one contact hole.

[0020] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the third trench is filled with an oxide layer dielectric or an oxide - polysilicon dielectric.

[0021] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the second metal electrode contacts the P - type silicon layer via four contact holes, two of the contact holes are arranged along a first direction, and the other two contact holes are arranged along a second direction, the first direction is perpendicular to the second direction, P - type heavily doped regions are formed at the bottoms of all four contact holes, and N - type heavily doped regions are formed on the sides of the two contact holes arranged along the first direction.

[0022] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein each of the contact holes under the second metal electrode is separated by a second trench.

[0023] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the second trench is filled with an oxide layer dielectric or an oxide - polysilicon dielectric.

[0024] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the first metal electrode, the second metal electrode, and the third metal electrode are spaced apart by a PAD dielectric layer.

[0025] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the first cell region and the second cell region have a common metal substrate, and the second cell region further forms two first metal electrodes, and the two first metal electrodes serve as the anode and cathode of the temperature detection diode respectively.

[0026] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the second cell region further includes a P - type silicon layer and an N - type silicon layer, the P - type silicon layer is disposed adjacent to the first metal electrode, and the N - type silicon layer is disposed adjacent to the metal substrate.

[0027] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the first metal electrode serving as the anode contacts the P - type silicon layer via one contact hole, and the first metal electrode serving as the cathode contacts the N - type silicon layer via one contact hole and an N - type heavily doped region.

[0028] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the N - type silicon layer has a convex portion, the convex portion extends into the P - type silicon layer, and the N - type heavily doped region is formed at the top of the convex portion.

[0029] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, an N-type heavily doped base layer is formed between the metal substrate and the N-type silicon layer.

[0030] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the second cell region is functionally spaced from the first cell region via at least one isolation trench.

[0031] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the isolation trench extends from an oxide dielectric layer under the first metal electrode, passes through the P-type silicon layer and extends into the N-type silicon layer.

[0032] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the isolation trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0033] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the first cell region and the second cell region have a common metal substrate, the second cell region further forms two first metal electrodes, and the two first metal electrodes serve as the anode and cathode of the temperature detection diode respectively;

[0034] The anode and the cathode are respectively in contact with the polysilicon layer through contact holes, a P-type doped region is formed in the region of the polysilicon layer adjacent to the contact hole of the anode, and an N-type doped region is formed in the region of the polysilicon layer adjacent to the contact hole of the cathode.

[0035] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the first cell region further includes a P-type silicon layer and an N-type silicon layer, and both the P-type silicon layer and the N-type silicon layer extend to the second cell region; the polysilicon layer and the P-type silicon layer are spaced by at least one spacer layer.

[0036] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the second cell region is functionally spaced from the first cell region via at least one isolation trench.

[0037] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the isolation trench extends from an oxide dielectric layer under the first metal electrode, passes through the P-type silicon layer and extends into the N-type silicon layer.

[0038] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, the polysilicon layer is disposed in the oxide dielectric layer.

[0039] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein the isolation trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0040] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein an oxide dielectric layer is provided between the second metal electrode of the first cell region and the layer where the third metal electrode is located and the P - type silicon layer, and the first cell region and the second cell region share the oxide dielectric layer.

[0041] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein at least one charging current auxiliary detection field - effect transistor is further formed in the first cell region, the drain of the charging current auxiliary detection field - effect transistor is connected to the drain of the charging control field - effect transistor, and the gate of the charging current auxiliary detection field - effect transistor is used to receive a control signal to be in a conducting state.

[0042] A semiconductor device with an integrated temperature detection diode according to at least one embodiment of the present disclosure, wherein at least one discharging current auxiliary detection field - effect transistor is further formed in the first cell region, the drain of the discharging current auxiliary detection field - effect transistor is connected to the drain of the discharging control field - effect transistor, and the gate of the discharging current auxiliary detection field - effect transistor is used to receive a control signal to be in a conducting state.

[0043] According to another aspect of the present disclosure, a battery system is provided, including: the semiconductor device according to any one of the above embodiments, and the semiconductor device controls the charging / discharging of the battery device.

[0044] In a battery system according to at least one embodiment of the present disclosure, the semiconductor device further detects the charging current / discharging current of the battery device.

[0045] According to still another aspect of the present disclosure, an electrical device is provided, including: a battery device; and, the battery system according to any one of the above embodiments, and the battery system at least controls the charging / discharging of the battery device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, are used to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are included in this specification and form a part of this specification.

[0047] Figure 1 It is a schematic structural diagram of a semiconductor device with an integrated temperature detection diode according to an embodiment of the present disclosure.

[0048] Figure 2 is Figure 1Top view.

[0049] Figure 3 It is a schematic structural diagram of a semiconductor device with an integrated temperature detection diode according to another embodiment of the present disclosure.

[0050] Figure 4 is Figure 3 Top view.

[0051] Figure 5 It is a schematic structural diagram of a semiconductor device with an integrated temperature detection diode according to another embodiment of the present disclosure.

[0052] Figure 6 is Figure 5 Top view.

[0053] Figure 7 It is a schematic circuit diagram of a battery system according to an embodiment of the present disclosure.

[0054] Figure 8 It is one of the schematic diagrams of the working principle of a battery system according to an embodiment of the present disclosure.

[0055] Figure 9 It is another schematic diagram of the working principle of a battery system according to an embodiment of the present disclosure.

[0056] Figure 10 It is a schematic block diagram of the structure of an electrical device according to an embodiment of the present disclosure. Specific embodiments

[0057] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant content and are not intended to limit the present disclosure. Additionally, it should be noted that for the sake of description, only the parts related to the present disclosure are shown in the drawings.

[0058] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and embodiments.

[0059] Unless otherwise specified, the exemplary embodiments / examples shown will be understood to provide exemplary features of various details of some ways that can implement the technical concept of the present disclosure in practice. Therefore, unless otherwise specified, without departing from the technical concept of the present disclosure, the features of various embodiments / examples can be additionally combined, separated, interchanged, and / or rearranged.

[0060] In the drawings, the use of cross-hatching and / or shading is generally used to make the boundaries between adjacent components clear. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for the specific material, material properties, dimensions, proportions, commonality between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be exaggerated. When an exemplary embodiment can be implemented differently, the specific process order may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals denote the same components.

[0061] When a component is referred to as being "on" or "above" another component, "connected to" or "coupled to" another component, the component can be directly on the other component, directly connected to or directly coupled to the other component, or there can be intervening components. However, when a component is referred to as being "directly on" another component, "directly connected to" or "directly coupled to" another component, there are no intervening components. For this reason, the term "connected" can refer to a physical connection, an electrical connection, etc., and can have or not have intervening components.

[0062] For descriptive purposes, the present disclosure may use spatial relative terms such as "under", "below", "beneath", "lower", "above", "upper", "on", "over", "higher", and "side (e.g., in "sidewall")" to describe the relationship of one component to another (other) component as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as being "under" or "beneath" another component or feature will then be positioned "above" the other component or feature. Thus, the exemplary term "under" can encompass both the "above" and "under" orientations. In addition, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0063] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms. In addition, when the terms "comprise" and / or "include" and their variants are used in this specification, it is stated that there are the stated features, integers, steps, operations, components, assemblies and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, assemblies and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and thus they are used to explain the inherent deviations of measured, calculated and / or provided values that would be recognized by a person of ordinary skill in the art.

[0064] In the following, in conjunction with Figures 1 to 10 a semiconductor device, a battery system and an electrical device of an integrated temperature detection diode according to the present disclosure will be described in detail.

[0065] First, with reference to Figures 1 to 6 a semiconductor device 10 / 20 / 30 of an integrated temperature detection diode according to the present disclosure will be described in detail.

[0066] A semiconductor device 10 / 20 / 30 of an integrated temperature detection diode according to an embodiment of the present disclosure includes:

[0067] a first cell region in which a charge control field effect transistor Ma is formed, and a gate of the charge control field effect transistor Ma is configured to receive a control signal to be in an on state; and a second cell region in which a temperature detection diode is formed, and the temperature detection diode is configured to detect a current temperature of the semiconductor device; wherein, the first cell region and the second cell region are disposed adjacent to each other.

[0068] Figure 1 , Figure 3 , Figure 5 are all longitudinal sectional views, showing the structures of semiconductor devices of integrated temperature detection diodes according to different embodiments of the present disclosure.

[0069] In a semiconductor device of an integrated temperature detection diode according to a preferred embodiment of the present disclosure, a discharge control field effect transistor Mb is further formed in the first cell region, and a gate of the discharge control field effect transistor Mb is configured to receive a control signal to be in an on state.

[0070] Wherein, the charge control field effect transistor Ma and the discharge control field effect transistor Mb may adopt the same semiconductor structure.

[0071] Figures 1 to 6 In, reference numeral 109 is an electrostatic isolation layer, which preferably adopts polysilicon.

[0072] Reference Figure 1 and Figure 2 For the semiconductor device 10 of an integrated temperature detection diode according to a preferred embodiment of the present disclosure, the first cell region and the second cell region have a common metal substrate 101, and the second cell region further forms a first metal electrode 108. The first metal electrode 108 serves as the anode of the temperature detection diode, and the metal substrate 101 can serve as the cathode of the temperature detection diode.

[0073] For the semiconductor device 10 of the integrated temperature detection diode in the above embodiment, preferably, the second cell region further includes a P-type silicon layer 104 and an N-type silicon layer 103. The P-type silicon layer 104 is disposed adjacent to the first metal electrode 108, and the N-type silicon layer 103 is disposed adjacent to the metal substrate 101.

[0074] Wherein, an N-type heavily doped silicon layer 102 is disposed between the N-type silicon layer 103 and the metal substrate 101.

[0075] For the semiconductor device 10 of the integrated temperature detection diode in the above embodiment, reference Figure 1 and Figure 2 Preferably, the first metal electrode 108 is in contact with the P-type silicon layer 104 via more than two contact holes 110. Figure 1 and Figure 2 Both show two contact holes 110 corresponding to the first metal electrode 108.

[0076] Wherein, P-type heavily doped regions are formed at the bottoms of the contact holes 110 corresponding to the first metal electrode 108.

[0077] Preferably, for the semiconductor device 10 of the integrated temperature detection diode in each of the above embodiments, the second cell region is functionally separated from the first cell region via at least one isolation trench.

[0078] Figure 1 and Figure 2 Show the functional isolation of the first cell region and the second cell region via three isolation trenches.

[0079] Reference Figure 1 For the semiconductor device 10 of the integrated temperature detection diode in each of the above embodiments, preferably, the isolation trench extends from the oxide dielectric layer 105 under the first metal electrode 108, passes through the P-type silicon layer 104 and extends into the N-type silicon layer 103.

[0080] For the semiconductor device 10 of the integrated temperature detection diode in each of the above embodiments, the isolation trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0081] For the semiconductor device with an integrated temperature detection diode of the present disclosure, refer to Figures 1 to 6 , the first cell region further includes a P-type silicon layer 104 and an N-type silicon layer 103, and the first cell region shares the P-type silicon layer 104 and the N-type silicon layer 103 with the second cell region.

[0082] Refer to Figures 1 to 6 , the metal substrate 101 can serve as the drain of the charge control field effect transistor Ma, and a second metal electrode 106 and a third metal electrode 107 are provided on the side of the P-type silicon layer 103 away from the metal substrate 101. The second metal electrode 106 can serve as the source of the charge control field effect transistor Ma, and the third metal electrode 107 can serve as the gate of the charge control field effect transistor Ma.

[0083] For the semiconductor device with an integrated temperature detection diode of the present disclosure, preferably, refer to Figures 1 to 6 , the third metal electrode 107 is in contact with a third trench extending into the N-type silicon layer 103 through the P-type silicon layer 104 via a contact hole. The third trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0084] For the semiconductor device with an integrated temperature detection diode of the present disclosure, preferably, the second metal electrode 106 is in contact with the P-type silicon layer 103 via four contact holes, where two contact holes are arranged along a first direction, and the other two contact holes are arranged along a second direction. The first direction is perpendicular to the second direction. P-type heavily doped regions are formed at the bottoms of all four contact holes, and N-type heavily doped regions are formed on the sides of the two contact holes arranged along the first direction (the horizontal direction shown in the figure).

[0085] For the semiconductor device with an integrated temperature detection diode of the present disclosure, preferably, refer to Figures 1 to 6 , the contact holes under the second metal electrode 106 are separated by second trenches.

[0086] Among them, the second trenches are filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0087] For the semiconductor device with an integrated temperature detection diode of the present disclosure, the first metal electrode 108, the second metal electrode 106, and the third metal electrode 107 are spaced apart by a PAD dielectric layer.

[0088] For the semiconductor device 20 with an integrated temperature detection diode according to another preferred embodiment of the present disclosure, refer to Figure 3 and Figure 4 , the first cell region and the second cell region have a common metal substrate 201, and the second cell region further forms two first metal electrodes 208, and the two first metal electrodes 208 respectively serve as the anode and cathode of the temperature detection diode.

[0089] Preferably, refer toFigure 3 and Figure 4 Moreover, the second cell region further includes a P-type silicon layer 204 and an N-type silicon layer 203. The P-type silicon layer 204 is disposed adjacent to the first metal electrode 208, and the N-type silicon layer 203 is disposed adjacent to the metal substrate 201.

[0090] For the semiconductor device 20 of the integrated temperature detection diode in the above embodiment, the first metal electrode 208 as the anode is in contact with the P-type silicon layer 204 via a contact hole, and the first metal electrode 208 as the cathode is in contact with the N-type silicon layer 203 via a contact hole and an N-type heavily doped region.

[0091] For the semiconductor device 20 of the integrated temperature detection diode in the above embodiment, the N-type silicon layer 203 has a convex portion that extends into the P-type silicon layer 204, and the top of the convex portion forms an N-type heavily doped region.

[0092] For the semiconductor device 20 of the integrated temperature detection diode in the above embodiment, an N-type heavily doped base layer 202 is formed between the metal substrate 201 and the N-type silicon layer 203.

[0093] Reference Figure 3 and Figure 4 Moreover, the second cell region is functionally separated from the first cell region via at least one isolation trench.

[0094] Figure 3 and Figure 4 In [[ ]] and [[ ]], the second cell region is functionally separated from the first cell region via three isolation trenches.

[0095] Preferably, for the semiconductor device 20 of the integrated temperature detection diode, the isolation trench extends from the oxide dielectric layer 205 under the first metal electrode 208, passes through the P-type silicon layer 204, and extends into the N-type silicon layer 203. Among them, the isolation trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0096] For the semiconductor device 30 of the integrated temperature detection diode according to another preferred embodiment of the present disclosure, reference Figure 5 and Figure 6 Moreover, the first cell region and the second cell region share a common metal substrate 301, and the second cell region further forms two first metal electrodes 308, and the two first metal electrodes 308 serve as the anode and cathode of the temperature detection diode respectively;

[0097] The anode and the cathode are respectively in contact with the polysilicon layer 314 via contact holes. A P-type doped region is formed in the region of the polysilicon layer 314 adjacent to the contact hole of the anode, and an N-type doped region is formed in the region of the polysilicon layer 314 adjacent to the contact hole of the cathode.

[0098] For the semiconductor device 30 of the integrated temperature detection diode in the above embodiments, preferably, the first cell region further includes a P-type silicon layer 304 and an N-type silicon layer 303, and both the P-type silicon layer 304 and the N-type silicon layer 303 extend to the second cell region; a polysilicon layer 314 and the P-type silicon layer 304 are spaced apart by at least one spacer layer ( Figure 5 as shown in Figure 5

[0099] For the semiconductor device 30 of the integrated temperature detection diode in the above respective embodiments, preferably, the second cell region is functionally spaced apart from the first cell region via at least one isolation trench. Figure 5 and Figure 6 as shown in Figure 6

[0100] Referring to Figure 5 and Figure 6 , the isolation trench extends from an oxide dielectric layer 305 under the first metal electrode 308, passes through the P-type silicon layer 304 and extends into the N-type silicon layer 303.

[0101] For the semiconductor device 30 of the integrated temperature detection diode in the above respective embodiments, preferably, the polysilicon layer 314 is disposed in the oxide dielectric layer 305.

[0102] Preferably, the isolation trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

[0103] For the semiconductor device 30 of the integrated temperature detection diode in the above respective embodiments, preferably, an oxide dielectric layer 305 is disposed between the layer where the second metal electrode 306 and the third metal electrode 307 of the first cell region are located and the P-type silicon layer 304, and the oxide dielectric layer 305 is shared by the first cell region and the second cell region.

[0104] For the semiconductor device of the integrated temperature detection diode in the above respective embodiments, preferably, at least one charge current auxiliary detection field effect transistor Sa is further formed in the first cell region. The drain of the charge current auxiliary detection field effect transistor is connected to the drain of the charge control field effect transistor, and the gate of the charge current auxiliary detection field effect transistor is used to receive a control signal to be in a conducting state.

[0105] For the semiconductor device of the integrated temperature detection diode in the above respective embodiments, preferably, at least one discharge current auxiliary detection field effect transistor Sb is further formed in the first cell region. The drain of the discharge current auxiliary detection field effect transistor is connected to the drain of the discharge control field effect transistor, and the gate of the discharge current auxiliary detection field effect transistor is used to receive a control signal to be in a conducting state.

[0106] The semiconductor device of the integrated temperature detection diode described above can be applied to the battery system of the present disclosure.

[0107] The following will combine with Figures 7 to 9 to describe the battery system of the present disclosure in detail.

[0108] The following will combine with Figures 7 to 9 to describe the battery system and the electrical equipment of the present disclosure in detail.

[0109] First, refer to Figure 7 , the battery system according to an embodiment of the present disclosure includes:

[0110] A semiconductor device 10 / 20 / 30 integrating a temperature detection diode and an acquisition and processing chip 50; the semiconductor device 10 / 20 / 30 integrating a temperature detection diode includes:

[0111] A charging control field-effect transistor Ma, the gate of the charging control field-effect transistor Ma is used to receive a control signal to be in a conducting state;

[0112] At least one charging current auxiliary detection field-effect transistor Sa, the drain of the charging current auxiliary detection field-effect transistor Sa is connected to the drain of the charging control field-effect transistor Ma, the gate of the charging current auxiliary detection field-effect transistor Sa is used to receive a control signal to be in a conducting state; and, a temperature detection diode Diode, the temperature detection diode Diode detects the current temperature T of the semiconductor device 10 / 20 / 30; the acquisition and processing chip 50 includes:

[0113] An auxiliary current generating device (including a current source device 520), the auxiliary current generating device generates an auxiliary current to at least flow through the charging current auxiliary detection field-effect transistor Sa in a conducting state;

[0114] A voltage acquisition device, the voltage acquisition device at least acquires the voltage between the source and drain of the charging current auxiliary detection field-effect transistor Sa through which the auxiliary current flows and the voltage between the source and drain of the charging control field-effect transistor Ma through which the charging current flows; and, a logic processing circuit 530, the logic processing circuit 530 obtains the magnitude of the charging current at least based on the voltage between the source and drain of the charging current auxiliary detection field-effect transistor Sa, the voltage between the source and drain of the charging control field-effect transistor Ma, and the auxiliary current.

[0115] Among them, the logic processing circuit 530 may include a multiplication and division operation circuit to execute a preset operation processing logic to obtain the magnitude of the charging current.

[0116] The logic processing circuit 530 may be in the form of a chip or a part of a chip, and the circuit structure of the multiplication and division operation circuit may adopt the prior art.

[0117] Figure 7In the semiconductor device 10 / 20 / 30, there are multiple ports such as D1, S3, S3R, S1, S1R, G1, G2, S2R, S2, etc.

[0118] Figure 7 In the semiconductor device 10 / 20 / 30, there are also a first sampling and filtering resistor Res1 (set between the source of the Sa transistor and the port S1R), a second sampling and filtering resistor Res2 (set between the source of the Sb transistor and the port S2R), and a third sampling and filtering resistor Res3 (set between the source of the Ma transistor and the port S3R). The semiconductor device 10 also includes a first sampling and filtering capacitor C1 (set between the port S3R and the port S1R) and a second sampling and filtering capacitor C2 (set between the port S1R and the port S2R).

[0119] Figure 7 In the acquisition and processing chip 50, there are multiple ports such as S3H, D1H, S3RH, S1H, S1RH, CHG, DSG, S2RH, S2H, RT.

[0120] For the connection manner between each port of the semiconductor device 10 / 20 / 30 and each port of the acquisition and processing chip 50, refer to Figure 7 .

[0121] Figure 7 In it, PACK+ is the positive terminal of the battery pack, and PACK- is the negative terminal of the battery pack.

[0122] The battery device 40 can be a battery cell or a battery pack composed of multiple battery cells.

[0123] For the battery system of the above embodiments, the semiconductor device 10 / 20 / 30 further includes:

[0124] A discharge control field effect transistor Mb, the gate of the discharge control field effect transistor Mb is used to receive a control signal to be in a conducting state; and at least one discharge current auxiliary detection field effect transistor Sb, the drain of the discharge current auxiliary detection field effect transistor Sb is connected to the drain of the discharge control field effect transistor Mb, and the gate of the discharge current auxiliary detection field effect transistor Sb is used to receive a control signal to be in a conducting state.

[0125] Figure 7 In it, each field effect transistor Ma, Mb, Sa, Sb of the battery system of the present disclosure is exemplarily an N-type FET, and those skilled in the art can adjust it, and all fall within the protection scope of the present disclosure.

[0126] As Figure 7 shown, the charge control field effect transistor Ma and the discharge control field effect transistor Mb of the battery system are connected in series so that the charge control field effect transistor Ma and the discharge control field effect transistor Mb can be arranged in the charge and discharge loop.

[0127] The drain of the charging control field effect transistor Ma is connected to the drain of the discharging control field effect transistor Mb. The drain of the charging current auxiliary detection field effect transistor Sa is connected to the drain of the charging control field effect transistor Ma. The drain of the discharging current auxiliary detection field effect transistor Sb is connected to the drain of the discharging control field effect transistor Mb.

[0128] For the battery systems of the above various embodiments, the temperature detection diode Diode detects the current temperature of the charging control field effect transistor Ma.

[0129] Figure 7 Exemplarily, the setting position and setting manner of the temperature detection diode are shown. Those skilled in the art can adjust its setting position, setting manner, etc. on the basis of the technical solution of the present disclosure to detect the temperature of the charging control field effect transistor Ma and / or the discharging control field effect transistor Mb, or detect the temperature of the adjacent areas of both.

[0130] For the battery systems of the above various embodiments, preferably, the charging control field effect transistor Ma and the discharging control field effect transistor Mb are arranged between the positive extreme PACK+ of the battery pack and the positive extreme B+ of the battery device 40 in the battery pack.

[0131] For the battery systems of the above various embodiments, the acquisition and processing chip 50 further includes an FET driver 510. The FET driver 510 is used to provide a control signal to the gate of the charging control field effect transistor Ma, provide a control signal to the gate of the discharging control field effect transistor Mb, provide a control signal to the gate of the charging current auxiliary detection field effect transistor Sa, and provide a control signal to the gate of the discharging current auxiliary detection field effect transistor Sb.

[0132] Generating a control signal (driving signal) by the FET driver belongs to the prior art. The FET driver can generate a control signal (driving signal) based on a preset driving logic. The FET driver can be a semiconductor chip or a part of a semiconductor chip. The present disclosure does not intend to particularly limit the circuit structure of the FET driver.

[0133] As Figure 7 shown, the FET driver can provide a control signal to the gates of the Ma transistor and the Sa transistor through the port CHG and the port G1, and provide a control signal to the gates of the Mb transistor and the Sb transistor through the port DSG and the port G2.

[0134] For the battery systems of the above various embodiments, it further includes a zero temperature coefficient resistor Rext; the auxiliary current (which can be 1 mA both during testing and actual use) generated by the auxiliary current generating device 520 can respectively flow through the zero temperature coefficient resistor Rext and the charging current auxiliary detection field effect transistor Sa in the conducting state;

[0135] The voltage acquisition device includes a first voltage acquisition unit 501, which acquires the voltage V across the zero temperature coefficient resistor Rext when the auxiliary current flows through the zero temperature coefficient resistor Rext. Rext .

[0136] For the battery system of each of the above-mentioned embodiments, preferably, the voltage acquisition device includes a second voltage acquisition unit 502 and a third voltage acquisition unit 503, the second voltage acquisition unit 502 at least acquires the voltage between the source and the drain (Vds_SaT) when the auxiliary current flows through the charging current auxiliary detection field effect transistor Sa, and the third voltage acquisition unit 503 at least acquires the voltage between the source and the drain (Vds_MaT) when the charging current flows through the charging control field effect transistor Ma.

[0137] like Figure 7 As shown, the auxiliary current generating device 520 is a current mirror, and the current mirror is preferably a 1:1 current mirror.

[0138] For the battery system of each embodiment above, preferably, the logic processing circuit 530 is based on the resistance value of the zero temperature coefficient resistor Rext, the voltage V across the zero temperature coefficient resistor Rext, and the voltage V Rext and the voltage Vds_SaT between the source and drain of the charging current auxiliary detection field effect tube Sa when the auxiliary current flows through it, to obtain the on-resistance Ron_SaT of the charging current auxiliary detection field effect tube Sa at the current temperature T;

[0139] The logic processing circuit 530 obtains the proportionality coefficient of the on-resistance of the field effect tube with temperature βT=Ron_SaT / Ron_Sa0 based on the on-resistance Ron_SaT of the charging current auxiliary detection field effect tube Sa at the current temperature T and the on-resistance Ron_Sa0 of the charging current auxiliary detection field effect tube Sa at the reference temperature (T0, i.e., FT);

[0140] The logic processing circuit 530 obtains the on-resistance Ron_MaT of the charging control field effect transistor Ma at the current temperature T based on the proportional coefficient βT and the on-resistance Ron_Ma0 of the charging control field effect transistor Ma at the reference temperature (T0, i.e., FT);

[0141] Ron_MaT=βT×Ron_Ma0.

[0142] The present invention manufactures or forms the charge control field effect transistor Ma, the charge current auxiliary detection field effect transistor Sa, the discharge control field effect transistor Mb and the discharge current auxiliary detection field effect transistor Sb with the same material and manufacturing process, so that the proportional coefficient βT measured by the Sa tube is applicable to the Ma tube.

[0143] That is, the logic processing circuit 530 (multiplication and division circuit) obtains the on-impedance Ron_MaT of the charging control field effect transistor Ma at the current temperature T based on the on-impedance Ron_SaT of the charging current auxiliary detection field effect transistor Sa at the current temperature T, the on-impedance Ron_Sa0 at the reference temperature, and the on-impedance Ron_Ma0 of the charging control field effect transistor Ma at the reference temperature (T0, i.e., FT).

[0144] Furthermore, the logic processing circuit 530 (multiplication and division operation circuit) obtains the charging current Ids_Ma flowing through the charging control field effect transistor Ma based on the source-drain voltage Vds_MaT when the charging current flows through the charging control field effect transistor Ma and the on-resistance Ron_MaT at the current temperature T.

[0145] For the battery system of each of the above embodiments, the on-resistance Ron_Ma0 of the charge control field effect transistor Ma at the reference temperature (T0, i.e., FT) is a pre-obtained on-resistance, which can be obtained, for example, during the packaging test (FT).

[0146] For the battery system of each of the above-mentioned embodiments, preferably, the FET driver 510 provides a control signal to the gate of the charging control field effect transistor Ma, the gate of the discharging control field effect transistor Mb, the gate of the charging current auxiliary detection field effect transistor Sa and the gate of the discharging current auxiliary detection field effect transistor Sb, so that the charging control field effect transistor Ma, the discharging control field effect transistor Mb, the charging current auxiliary detection field effect transistor Sa and the discharging current auxiliary detection field effect transistor Sb are all in the on state, and the test charging current (for example, 1A) is injected into the positive terminal PACK+ of the battery pack, and the third voltage acquisition unit 503 acquires the source-drain voltage Vds_Ma0_1A of the charging control field effect transistor Ma at this time, and the logic processing circuit 530 obtains the on-resistance Ron_Ma0 of the charging control field effect transistor Ma at the reference temperature (T0, i.e., FT) based on the source-drain voltage Vds_Ma0_1A when the test charging current 1A flows through the charging control field effect transistor Ma and the test charging current (1A), i.e., Ron_Ma0=Vds_Ma0_1A / 1A.

[0147] Figure 8 It is a schematic diagram showing the direction of the test charging current in the form of a bold line and the collection of the voltage Vds_Ma0_1A between the source and drain of the Ma tube by the third voltage collection unit 503 via the port S3RH, the port S3R, the third sampling filter resistor Res3, and via the port S1RH, the port S1R, the first sampling filter resistor Res1, and the Sa tube.

[0148] For the battery systems of the above various embodiments, preferably, the on-resistance Ron_Sa0 of the charging current auxiliary detection field effect transistor Sa at the reference temperature T0 is a pre-obtained on-resistance, which can be obtained during package testing.

[0149] As Figure 9 shown, the logic processing circuit 530 of the battery system obtains the on-resistance Ron_Sa0 of the charging current auxiliary detection field effect transistor Sa at the reference temperature T0 based on the resistance value of the zero temperature coefficient resistor Rext, the voltage V at both ends of the zero temperature coefficient resistor Rext Rext0 and the voltage Vds_Sa0 between the source and drain of the charging current auxiliary detection field effect transistor Sa when the auxiliary current flows through it, that is, Ron_Sa0 = Rext × Vds_Sa0 / V Rext0 .

[0150] Figure 9 The direction of the auxiliary current (1 mA) shown in thick lines and the voltage V at both ends of the zero temperature coefficient resistor Rext are collected through the first voltage acquisition unit 501 via the port RT Rext0 , and the voltage Vds_Sa0 between the source and drain of the Sa transistor is collected through the second voltage acquisition unit 502 via the ports S1RH, S1R, the first sampling and filtering resistor Res1, and via the ports S2RH, S2R, the second sampling and filtering resistor Res2, and the Sb transistor.

[0151] The auxiliary current (1 mA) is generated by the current source device 520, so that the auxiliary current flows through the Sa transistor, and the mirrored auxiliary current flows through the zero temperature coefficient resistor Rext.

[0152] As Figures 7 to 9 shown, the voltage acquisition device preferably includes a first voltage acquisition unit 501, a second voltage acquisition unit 502, and a third voltage acquisition unit 503. Figures 7 to 9 The process of measuring the charging current assisted by the Ma transistor is described above. Those skilled in the art can adjust the number of voltage acquisition units to detect the discharge current assisted by the Mb transistor, which will not be elaborated here.

[0153] As Figures 7 to 9 shown, each voltage acquisition unit has the same circuit structure, which includes a charge transfer capacitor, a switch group (4 switches), an amplifier, and an ADC converter. It should be noted that Figures 7 to 9 the circuit structure of the voltage acquisition unit shown is only the preferred circuit structure of the present disclosure. Those skilled in the art can adjust the circuit structure of the voltage acquisition unit under the inspiration of the technical solution of the present disclosure, and all fall within the protection scope of the present disclosure.

[0154] For the battery systems of the above respective embodiments, preferably, the ratio of the channel width-to-length ratio of the charging current auxiliary detection field effect transistor Sa to the channel width-to-length ratio of the charging control field effect transistor Ma is 1:M, where M is greater than or equal to 1.

[0155] In the present disclosure, the channel width-to-length ratio of the charging current auxiliary detection field effect transistor Sa is preferably equal to the channel width-to-length ratio of the charging control field effect transistor Ma.

[0156] Preferably, the ratio of the channel width-to-length ratio of the discharging current auxiliary detection field effect transistor Sb to the channel width-to-length ratio of the discharging control field effect transistor Mb is 1:M, where M is greater than or equal to 1.

[0157] In the present disclosure, the channel width-to-length ratio of the discharging current auxiliary detection field effect transistor Sb is preferably equal to the channel width-to-length ratio of the discharging control field effect transistor Mb.

[0158] The battery system according to an embodiment of the present disclosure includes: the semiconductor device of any one of the above embodiments, and the semiconductor device controls charging / discharging of the battery device 40.

[0159] Preferably, the semiconductor device also detects the charging current / discharging current of the battery device 40.

[0160] The electrical equipment according to at least one embodiment of the present disclosure, refer to Figure 10 , includes: a battery device 40; and, the above battery system, and the battery system at least controls charging / discharging of the battery device 40.

[0161] In the description of this specification, the description with reference to terms such as "one embodiment / way", "some embodiments / ways", "example", "specific example" or "some examples", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments / ways or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments / ways or examples described in this specification and the features of different embodiments / ways or examples.

[0162] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0163] Those skilled in the art should understand that the above-described embodiments are merely for clearly illustrating the present disclosure and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications can be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A semiconductor device integrated with a temperature detection diode, characterized in that, Comprising: A first cell region, wherein a charge control field effect transistor is formed in the first cell region, and a gate of the charge control field effect transistor is configured to receive a control signal to be in an on state; And A second cell region, wherein a temperature detection diode is formed in the second cell region, and the temperature detection diode is configured to detect a current temperature of the semiconductor device; Wherein, the first cell region and the second cell region are disposed adjacent to each other; The first cell region and the second cell region have a common metal substrate, an N-type heavily doped silicon layer, an N-type silicon layer, and a P-type silicon layer, and the N-type heavily doped silicon layer, the N-type silicon layer, and the P-type silicon layer are sequentially disposed above the metal substrate; The metal substrate can serve as a drain of the charge control field effect transistor, the first cell region is provided with a second metal electrode and a third metal electrode on a side of the P-type silicon layer away from the metal substrate, the second metal electrode can serve as a source of the charge control field effect transistor, and the third metal electrode can serve as a gate of the charge control field effect transistor; The second metal electrode is in contact with the P-type silicon layer via four contact holes, wherein two contact holes are arranged along a first direction, and the other two contact holes are arranged along a second direction, and the first direction is perpendicular to the second direction. P-type heavily doped regions are formed at bottoms of the four contact holes, and N-type heavily doped regions are formed at sides of the two contact holes arranged along the first direction.

2. The semiconductor device integrated with a temperature detection diode according to claim 1, wherein The first cell region further forms a discharge control field effect transistor, and a gate of the discharge control field effect transistor is configured to receive a control signal to be in an on state.

3. The semiconductor device with an integrated temperature detection diode according to claim 1 or 2, characterized in that, The second cell region further forms a first metal electrode, the first metal electrode is disposed adjacent to the P-type silicon layer, the first metal electrode serves as an anode of the temperature detection diode, and the metal substrate can serve as a cathode of the temperature detection diode.

4. The semiconductor device integrated with a temperature detection diode according to claim 3, characterized in that, The first metal electrode is in contact with the P-type silicon layer via more than two contact holes.

5. The semiconductor device integrated with a temperature detection diode according to claim 4, wherein, P-type heavily doped regions are formed at bottoms of the contact holes.

6. The semiconductor device with an integrated temperature detection diode according to claim 1 or 2, characterized in that, The second cell region further forms two first metal electrodes, and the two first metal electrodes respectively serve as an anode and a cathode of the temperature detection diode.

7. The semiconductor device integrated with a temperature detection diode according to claim 6, characterized in that, The anode and the cathode are respectively in contact with a polysilicon layer via contact holes, a P-type doped region is formed in a region of the polysilicon layer adjacent to the contact hole of the anode, and an N-type doped region is formed in a region of the polysilicon layer adjacent to the contact hole of the cathode.

8. The semiconductor device integrated with a temperature detection diode according to claim 7, characterized in that, The polysilicon layer and the P-type silicon layer are spaced apart by at least one spacer layer.

9. The semiconductor device integrated with a temperature detection diode according to claim 3, characterized in that, The second cell region is functionally spaced apart from the first cell region via at least one isolation trench.

10. The semiconductor device with an integrated temperature detection diode according to claim 9, characterized in that, The isolation trench extends from an oxide dielectric layer under the first metal electrode, passes through the P-type silicon layer and extends into the N-type silicon layer.

11. The semiconductor device with an integrated temperature detection diode according to claim 10, characterized in that, The isolation trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

12. The semiconductor device integrated with a temperature detection diode according to claim 1, wherein The third metal electrode is in contact with a third trench extending into the N-type silicon layer via a P-type silicon layer via one contact hole.

13. The semiconductor device integrated with a temperature detection diode according to claim 12, characterized in that, The third trench is filled with an oxide layer dielectric or an oxide layer - polysilicon dielectric.

14. A battery system, characterized in that, Comprising: The semiconductor device according to any one of claims 1 to 13, which controls charging / discharging of a battery device.

15. An electrical device, characterized in that, Comprising: A battery device; And The battery system according to claim 14, which controls at least charging / discharging of the battery device.

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