A write verify circuit applied to STT-MRAM

Abstract

The application discloses a write verification circuit applied to STT-MRAM and belongs to the technical field of computer storage. The circuit comprises a write operation completion detection circuit and a write self-termination circuit; the write operation completion detection circuit is used for judging whether a write operation is completed or not and generating a detection feedback signal COP; and the write self-termination circuit generates a write operation signal and a termination write operation signal according to the detection feedback signal COP. The write operation completion detection circuit of the application monitors the state of the write operation in real time according to the change of the state of the STT-MRAM in the write operation process, generates a detection feedback signal acting on the write self-termination circuit, and once the write operation is detected to be completed, the write self-termination circuit generates a write driving circuit termination signal in time, closes the write driving and ends the write operation. The write verification circuit of the application simplifies the write operation process and can close the write driving in time after the write operation is completed, and compared with the traditional write operation, the power consumption can be reduced by 50%.

Description

Technical Field

[0001] This invention relates to a write verification circuit for STT-MRAM, belonging to the field of computer storage technology. Background Technology

[0002] Spin-transfer torque random access magnetic memory (STT-MRAM) is a novel type of non-volatile memory, considered one of the most promising alternatives to flash memory. When writing data to an STT-MRAM, the direction of the write current is determined by whether the data being written is "0" or "1". The write current is then injected into a specific memory cell, causing the free layer in the MRAM cell to deflect, thus changing the memory state. Because the write operation mechanism of STT-MRAM is inherently random, the toggle delay of its crucial component, the STT-MTJ cell, differs with each write attempt, even with constant physical characteristics. Furthermore, for a constant current density, the write process requires an indeterminate delay each time. Therefore, an additional time margin is needed to ensure successful write operation, resulting in significant additional power consumption. Moreover, in traditional write operations, a read operation is required after writing data to verify success, a process that demands an even larger write time margin, further increasing the power consumption of the write operation.

[0003] like Figure 3 The diagram shows a common write operation flowchart for STT-MRAM, where the write verification function is performed by the read operation. For example, when writing information "0" to STT-MRAM, the write drive signal is first made valid (BL connected to V). DD (SL connected to GND) Start writing information, and then perform a read verification after the specified write current duration ends. If the read storage information is the same as the written information "0", the write operation is complete. Otherwise, if it is different from the written information, the write is unsuccessful, and return to the initial stage to adjust the size and duration of the write current, and then perform a new round of writing until the read verification information is the same as the written information, and the write operation is complete.

[0004] Traditional write operations require read operations to verify their success, which is complex and increases power consumption. Furthermore, the write operation cannot be stopped immediately after completion, requiring an additional time margin to ensure successful completion, further increasing power consumption. Summary of the Invention

[0005] To address the problem that current write operations require read operation verification and have excessive write operation time margin, leading to increased power consumption, this invention provides a write verification circuit for STT-MRAM.

[0006] The first object of the present application is to provide a write verification circuit applied to STT-MRAM, which comprises:

[0007] a write operation completion detection circuit and a write self-termination circuit; the write operation completion detection circuit is used to determine whether the write operation is completed and to generate a detection feedback signal COP; the write self-termination circuit generates a write operation signal and a termination write operation signal according to the detection feedback signal COP.

[0008] Optionally, the write operation completion detection circuit comprises a current mirror, a reference resistor, a comparator and a buffer.

[0009] The current mirror is used to copy the write current flowing through the STT-MRAM and to generate a copied write current; the copied write current is converted into a copied write voltage through the reference resistor; the copied write voltage and the reference voltage generate the detection feedback signal COP through the comparator and the buffer.

[0010] Optionally, the write self-termination circuit generates a driving enable signal through the calculation of the enable signal and the detection feedback signal COP, and the driving enable signal controls the write driving circuit to perform different write operations on the STT-MRAM.

[0011] Optionally, the write verification process of the write verification circuit comprises:

[0012] When the write operation is completed, the state of the STT-MTJ is reversed, the resistance changes, and the write current flowing through the STT-MRAM changes.

[0013] The copied write current generated by the current mirror changes, and thus the copied write voltage input into the comparator changes.

[0014] The copied write voltage generates a new detection feedback signal COP through the comparator and the buffer.

[0015] The self-termination circuit generates a termination write operation signal according to the level of the detection feedback signal COP and the enable signal, the write driving circuit is closed, and the write operation is completed.

[0016] Optionally, the write operation completion detection circuit further comprises a path control module, and the write operation completion detection circuit provides different operation paths for different write operations through the path control module.

[0017] Optionally, the path control module comprises a first switch tube M W1 , a second switch tube M W2 , a third switch tube M W3 , a fourth switch tube M W4 , a fifth switch tube M W5 , and a sixth switch tube MW6 The write operation completion detection circuit provides different operation paths for different write operations by controlling the opening and closing of the switch tubes.

[0018] When the STT-MRAM writes "0", the first switch tube M W1 , the third switch tube M W3 , the fifth switch tube M W5 is turned on, the second switch tube M W2 , the fourth switch tube M W4 , the sixth switch tube M W6 is turned off, the reference write voltage is connected to the positive input end of the comparator, and the reference voltage V REF is connected to the negative input end of the comparator.

[0019] When the STT-MRAM writes "1", the first switch tube M W1 , the third switch tube M W3 , the fifth switch tube M W5 is turned off, the second switch tube M W2 , the fourth switch tube M W4 , the sixth switch tube M W6 is turned on, the reference write voltage is connected to the negative input end of the comparator, and the reference voltage V REF is connected to the positive input end of the comparator.

[0020] Optionally, in the initial state, the STT-MTJ is in the AP state, the first enable signal W RE and the second enable signal W E of the write self-termination circuit are both low; the process of writing data "0" by the STT-MRAM includes:

[0021] The write current flows from the bit line BL of the STT-MRAM to the source line SL, and the STT-MRAM starts to write data "0";

[0022] The write current passes through the current mirror to generate a copy write "0" current I W0_AP ;

[0023] The copy write "0" current I W0_AP is converted into a copy write "0" voltage V X0 by the reference write "0" resistance R X0_AP , and the copy write "0" voltage V X0_AP is connected to the positive input end of the comparator.

[0024] When the write current duration is less than the STT-MTJ flip delay time, the STT-MTJ does not occur flip behavior, at this time, its resistance state is still in the AP state, the copy write "0" current is I W0_AP , and the voltage at the positive input end of the comparator is VX0_AP ;

[0025] When the write current duration is greater than or equal to the STT-MTJ flip delay time, the STT-MTJ flips from the AP state to the P state, at which time the copy write "0" current becomes I W0_P , the positive input terminal voltage of the comparator becomes V X0_P ;

[0026] The change of the negative input terminal voltage of the comparator causes the output level of the comparator to change, causing the detection feedback signal COP level value to change, and the write self-termination circuit generates a driving enable signal according to the change of the detection feedback signal COP, and the write drive is closed, and the write "0" operation is completed.

[0027] Optionally, the reference voltage of the comparator is V REF0 , and the value range is: V X0_AP <V REF0 <V X0_P ;

[0028] The copy write "0" voltage V X0_AP satisfies:

[0029]

[0030]

[0031] Where V W represents the write drive voltage; R AP represents the resistance of the STT-MTJ in the AP state; R ON0 represents the sum of the resistances of the other transistors in the write operation structure except the STT-MTJ when writing "0"; R X0 is the write "0" reference resistance;

[0032] The STT-MTJ flips from the AP state to the P state, the copy write "0" current becomes I W0_P , and the copy write "0" voltage also changes to V X0_P . The current I W0_P and the voltage V X0_P can be represented by the following formulas (3) and (4):

[0033]

[0034]

[0035] Where, R P represents the resistance of the STT-MTJ in the P state.

[0036] Optionally, in the initial state, STT-MTJ is in the P state, and the first enable signal W of the write-to-terminate circuit... RE With the second enable signal W E All are high level; the process of writing data "1" into STT-MRAM includes:

[0037] The write current flows from the source line SL of the STT-MRAM to the bit line BL, and the STT-MRAM begins to write the data "1";

[0038] The write current generates a copy write current I through the current mirror to write "1". W1_P ;

[0039] The copy-write "1" current I W0_AP Write "1" for resistor R by reference. X1 Convert to copy and write "1" voltage V X1_P The voltage V for copying and writing "1" X1_P Connect to the negative input terminal of the comparator;

[0040] When the write current duration is less than the STT-MTJ toggle delay time, the STT-MTJ does not toggle; at this time, its resistance state remains P, and the current for copying and writing "1" is I. W1_P The voltage at the negative input terminal of the comparator is V. X1_P ;

[0041] When the write current duration is greater than or equal to the STT-MTJ toggle delay time, the STT-MTJ toggles from the P state to the AP state. At this time, the copy write "1" current becomes I. W1_AP The voltage at the negative input terminal of the comparator becomes V. X1_AP ;

[0042] The change in voltage at the negative input terminal of the comparator causes a change in the output level of the comparator, which in turn causes a change in the level value of the detection feedback signal COP. The write self-termination circuit generates a drive enable signal that changes according to the detection feedback signal COP, the write drive is turned off, and the write "1" operation is completed.

[0043] Optionally, the reference voltage of the comparator is V. REF1 The value range is: V X1_AP <V REF1 <V X1_P ;

[0044] The voltage V for copying and writing "1" X1_P satisfy:

[0045]

[0046]

[0047] wherein, R P represents resistance of STT-MTJ in P state; R ON1 represents sum of resistances of transistors other than STT-MTJ in write operation structure when writing "1"; R X1 is reference resistance for writing "1";

[0048] When STT-MTJ flips from P state to AP state, STT-MRAM successfully writes data "1", at this time, copy writing "1" current and copy writing "1" voltage respectively become I W1_AP , V X1_AP , satisfying:

[0049]

[0050]

[0051] wherein, R AP represents resistance of STT-MTJ in AP state.

[0052] A second object of the present application is to provide an STT-MRAM memory comprising a plurality of memory cells, said memory cells being connected with the write verification circuit as described above, when information is written into said memory cells, the memory uses the write verification circuit as described above to verify the write operation.

[0053] The present application has the following advantages:

[0054] By providing a write operation completion detection circuit, according to the change of STT-MRAM state in the write operation process, the state of the write operation is monitored in real time, and a detection feedback signal is generated; and a write self-termination circuit is provided, the detection feedback signal acts on the write self-termination circuit, once the write operation is detected to be completed, the write self-termination circuit generates a write drive circuit termination signal in time, closes the write drive, and ends the write operation; the write verification circuit of the present application simplifies the write operation process, and can close the write drive in time after the write operation is completed, and end the write operation, compared with the traditional write operation, the power consumption can be reduced by 50%. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0056] Figure 1 The structure diagram of the write verification circuit for STT-MRAM designed by the present application;

[0057] Figure 2 The application is applied to the write verification circuit of STT-MRAM designed by the application;

[0058] Figure 3 The application is applied to the write verification circuit of STT-MRAM designed by the application;

[0059] Figure 4 The application is applied to the write verification circuit of STT-MRAM designed by the application; DETAILED DESCRIPTION

[0060] In order to make the purpose, technical scheme and advantages of the application more clear, the embodiments of the application will be further described in detail below with reference to the drawings.

[0061] Embodiment one:

[0062] The embodiment provides a write verification circuit applied to STT-MRAM, the circuit comprises a write operation completion detection circuit and a write self-termination circuit; the write operation completion detection circuit is used for judging whether the write operation is completed or not and generating a detection feedback signal COP; and the write self-termination circuit generates a write operation signal and a termination write operation signal according to the detection feedback signal COP.

[0063] The write verification circuit of the embodiment is composed of a write operation completion detection circuit and a write self-termination circuit. The change of the write circuit in the STT-MRAM unit is detected through the write operation completion detection circuit, the state of the write operation is monitored in real time, once the write operation is detected to be completed, the write drive is closed through the feedback signal COP acting on the write self-termination circuit, the write operation is ended, and the power consumption of the write operation is greatly reduced.

[0064] Embodiment two:

[0065] The embodiment provides a write verification circuit applied to STT-MRAM, the write operation verification function of the STT-MRAM is realized through a write operation completion detection circuit and a write self-termination circuit.

[0066] Figure 1 The application is applied to the write verification circuit structure block diagram of STT-MRAM designed by the embodiment. RE is an input enable signal, through the control of W RE , W E signal, different write operations can be performed on the STT-MRAM at will. The write operation completion detection circuit in the figure performs real-time detection on the current flowing through the STT-MTJ, and transmits the detected processing signal COP to the write self-termination circuit. The write self-termination generates enable signals W RE and W H through the calculation and processing of signals COP and W L , and WH and W L The signal-controlled write drive circuit performs different write operations on the STT-MRAM.

[0067] For example, when the STT-MRAM needs to write a "0" message, and assuming the original state of the STT-MTJ is AP, the write operation needs to transition from the AP state to the P state of the STT-MTJ. At this time, signal W... H W is a high level. L When the voltage level is low, the bit line BL of the STT-MRAM is connected to a high level, the source line SL is grounded, and current flows from the free layer to the fixed layer of the STT-MTJ. At this time, the resistance of the STT-MTJ is R. AP The current is I W_AP When the duration of the write current reaches the toggle time, the resistance of the STT-MTJ changes from R. AP Flip to R P The current becomes I W_P Data was successfully written. Changes in the current flowing through the STT-MTJ cause changes in the signal COP, thereby altering the signal W. H When the stored data and the written data have the same voltage level, the write driver is disabled. This scheme ensures that the write driver is immediately disabled when the stored data and the written data have the same value, which also reduces write energy consumption.

[0068] like Figure 2 This is the circuit diagram for the write operation verification proposed in this paper. The circuit achieves its automatic verification function during the write operation through a write operation completion detection circuit and a write self-termination circuit. The write operation completion detection circuit mainly detects the current change flowing through the STT-MTJ to determine whether the write operation is complete. The write self-termination circuit is responsible for generating the write operation signal and the write operation termination signal.

[0069] The write operation completion detection circuit consists of a current mirror, a comparator, and a buffer. When a write operation begins, the write current flowing through the STT-MRAM is copied from the left half of the current mirror to the right half, generating current I. X and through the reference resistor R X , will current I X Converted to voltage V X V X With reference voltage V REF A feedback signal COP is generated through a comparator CP and a buffer. The COP signal controls the write operation of the STT-MRAM via a write self-termination circuit. This is because the write current I required when writing a "1" to the STT-MRAM is... W1 The write current I is greater than the write current when writing "0". W0 Therefore, the current I X0 Less than I X1 .

[0070] To use the same V REF As a comparison reference voltage, the STT-MRAM writing "0" and writing "1" operation sets different paths. When the STT-MRAM needs to write "0", the switch tube M W1 , M W3 , M W5 is turned on, and the switch tube M W2 , M W4 , M W6 is turned off, at this time, V X0 = I X0 × R XO connects the positive input end of the comparator CP, V REF connects the negative input end; when writing "1", the switch tube M W2 , M W4 , M W6 is turned on, and the switch tube M W1 , M W3 , M W5 is turned off, at this time, V X1 = I X1 × R X1 connects the reverse input end of the comparator CP, V REF connects the positive input end.

[0071] Figure 2 The write operation verification process of the STT-MRAM in the middle is as follows: assuming that the initial state of the STT-MTJ is the AP state, when the enable signals W RE and W E are low, W D and W H are high, and W L is low, the current flows from the bit line BL of the STT-MRAM to the source line SL, and the STT-MRAM starts to write data "0". When the resistance of the STT-MTJ flips from the AP state to the P state, it indicates that the data "0" is written successfully. During the writing of "0", when the writing current duration is less than the STT-MTJ flip delay time, the STT-MTJ does not flip, at this time, its resistance state is still in the AP state, and the current flowing through the STT-MRAM is I W0_AP , and the voltage V X is V X0_AP . The current I W0_AP and the voltage V X0_AP can be represented by the following formulas (1) and (2):

[0072]

[0073]

[0074] where V W represents the write driving voltage, RON0 This indicates that when writing "0", the sum of the resistances of all transistors in the write operation structure except STT-MTJ is used. When the write current duration is greater than or equal to the STT-MTJ toggle delay time, STT-MTJ toggles from the AP state to the P state, and the current flowing through STT-MRAM becomes I. W0_P Voltage V X It also changes with the current as V X0_P Current I W0_P With voltage V X0_P This can be expressed by the following formulas (3) and (4):

[0075]

[0076]

[0077] From formulas (2) and (4), we can know that the voltage V X0_P Greater than voltage V X0_AP The comparator CP uses a reference voltage V for comparison. REF Set it to something in between.

[0078] Therefore, at the instant the drive voltage for the write "0" operation is turned on, the voltage V X For V X0_AP Less than the reference voltage V REF When the comparator output is low, meaning the feedback signal COP is low, COP acts on the enable signal W generated by the self-termination circuit. H Still at high level W L The STT-MRAM remains at a low level and continues writing "0" operations until the resistance of the STT-MTJ changes from the AP state to the P state, at which point the current through the STT-MRAM changes from I... W0_AP Become I W0_P Voltage V X By V X0_AP Change to V X0_P This indicates that the write operation is complete.

[0079] Due to V X0_P The comparison reference voltage V is greater than that of comparator CP. REF When the comparator outputs a high level, meaning the feedback signal COP changes from low to high, the enable signal W generated by the self-termination circuit, under the action of COP,... H With W L Both are low level, the write driver is off, and the write operation is over.

[0080] Similarly, when the STT-MRAM needs to write data "1", the enable signal W is set. RE With W E If it is high, then WH W D is low, W L is high. The write current flows from the source line SL to the bit line BL of the STT-MRAM, and when the STT-MTJ does not flip, the write current and the voltage V X are I W1_P and V X1_P , respectively, which can be represented by the following equations (5) and (6):

[0081]

[0082]

[0083] where R ON1 represents the sum of the resistances of the transistors in the write operation structure except the STT-MTJ when writing data "1". When the STT-MTJ flips from the P state to the AP state, the STT-MRAM successfully writes data "1", at which time the current I W1_P and the voltage V X1_P become I W1_AP and V X1_AP , respectively, which can be defined by the following equations (4.7) and (4.8):

[0084]

[0085]

[0086] It can be seen from equations (6) and (8) that V X1_P is greater than V X1_AP . By adjusting the sizes of the resistances R X0 and R X1 , the comparison reference voltage V REF of the comparator CP is also between the two. Therefore, when the resistance of the STT-MTJ changes from the P state to the AP state, the feedback signal COP changes from low to high, and the enable signals W H and W L generated by the write self-termination circuit are both low, the write drive of the STT-MRAM is closed, and the write operation is completed.

[0087] In order to further verify that the present application can effectively reduce the power consumption of the circuit, a series of simulations are performed, Figure 4 which show the comparison diagram of the transient simulation of the write operation of the STT-MRAM. The write voltage duration margin of each write operation is set to 10 ns, and the initial state is "0" state.

[0088] At 10 ns, the STT-MRAM starts to write "1" from "0", and at about 11.6 ns, the write "1" operation is completed, at this time, the write operation with the verification circuit of the application verifies the completion of the write "1" operation through the change of current, and at 14 ns, the write drive is closed to end the write operation, while the conventional write operation without the verification circuit of the application ends the write operation only when the initially set write time margin is met.

[0089] At 20 ns, the STT-MRAM starts to write "0" from "1", and at 21.9 ns, the write "0" operation is completed. The write operation with the verification circuit of the application verifies the completion of the write "0" operation through the verification circuit, and at 24.3 ns, the write drive is closed to end the write operation, while the conventional write operation without the verification circuit of the application still ends the write operation only when the initially set write time margin is met.

[0090] Therefore, the write verification circuit of the application saves 6 ns of time in the write "1" operation and saves 5.7 ns of time in the write "0" operation. Therefore, the write operation process of the application saves at least 50% of energy consumption compared with the conventional write operation process.

[0091] Part of the steps in the embodiment of the application can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0092] The above description is only the preferred embodiment of the application, and is not intended to limit the application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A write verify circuit for an STT-MRAM, the write verify circuit comprising: The circuit comprises a write operation completion detection circuit and a write self-termination circuit; the write operation completion detection circuit is used for judging whether a write operation is completed and generating a detection feedback signal COP; the write self-termination circuit generates a write operation signal and a termination write operation signal according to the detection feedback signal COP; The write operation completion detection circuit comprises a current mirror, a reference resistance, a comparator and a buffer; The current mirror is used for copying a write current flowing through the STT-MRAM and generating a copied write current; the copied write current is converted into a copied write voltage through the reference resistance; the copied write voltage and a reference voltage generate the detection feedback signal COP through the comparator and the buffer; The write self-termination circuit generates a driving enable signal through calculation of an enable signal and the detection feedback signal COP, and the driving enable signal controls a write driving circuit to perform different write operations on the STT-MRAM; The write operation verification process of the write verification circuit comprises: When the write operation is completed, the state of the STT-MTJ is reversed, the resistance value is changed, and the write current flowing through the STT-MRAM is changed; The copied write current generated by the current mirror is changed, so that the copied write voltage input into the comparator is changed; The copied write voltage generates a new detection feedback signal COP through the comparator and the buffer; The self-termination circuit generates a termination write operation signal according to the level of the detection feedback signal COP and the enable signal, and the write driving circuit is closed, so that the write operation is completed; The write operation completion detection circuit further comprises a path control module, and the write operation completion detection circuit provides different operation paths for different write operations through the path control module; The path control module comprises a first switch tube M W1 , a second switch tube M W2 , a third switch tube M W3 , a fourth switch tube M W4 , a fifth switch tube M W5 , and a sixth switch tube M W6 ; the write operation completion detection circuit provides different operation paths for different write operations by controlling the opening and closing of the switch tubes. When the STT-MRAM writes "0", the first switch tube M W1 , the third switch tube M W3 , the fifth switch tube M W5 is turned on, the second switch tube M W2 , the fourth switch tube M W4 , the sixth switch tube M W6 is turned off, the copy write voltage is connected to the positive input end of the comparator, and the reference voltage V REF is connected to the negative input end of the comparator; When the STT-MRAM writes "1", the first switch tube M W1 , the third switch tube M W3 , the fifth switch tube M W5 , the second switch tube M W2 , the fourth switch tube M W4 , the sixth switch tube M W6 is turned on, the copy write voltage is connected to the negative input end of the comparator, and the reference voltage V REF is connected to the positive input end of the comparator.

2. The write verify circuit of claim 1, wherein, In the initial state, the STT-MTJ is in the AP state, the first enable signal W RE of the write self-termination circuit is low, and the second enable signal W E is also low; the process of writing data "0" in the STT-MRAM includes: The write current flows from a bit line BL of the STT-MRAM to a source line SL, and the STT-MRAM starts to write data "0"; The write current generates a copy write "0" current I through the current mirror W0_AP ; copy write "0" current I W0_AP by reference write "0" resistance R X0 converts into copy write "0" voltage V X0_AP , said copy write "0" voltage V X0_AP a positive input of said comparator; When the write current duration is less than the STT-MTJ flipping delay time, the STT-MTJ does not flip, and its resistance state remains in the AP state, and the copy write "0" current is I W0_AP , and the positive input voltage of the comparator is V X0_AP . When the write current duration is greater than or equal to the STT-MTJ flipping delay time, the STT-MTJ flips from the AP state to the P state, at which time the copy write "0" current becomes I W0_P , and the positive input voltage of the comparator becomes V X0_P . The change of the voltage at the negative input end of the comparator causes the change of the output level of the comparator, which causes the change of the level of the detection feedback signal COP, and the write self-termination circuit generates a driving enable signal according to the change of the detection feedback signal COP, so that the write driving is closed and the write "0" operation is completed.

3. The write verify circuit of claim 2, wherein, The reference voltage of the comparator is V REF0 , and the value range is: V X0_AP <V REF0 <V X0_P ; The copy write "0" voltage V X0_AP satisfies: where V W represents the write drive voltage; R AP represents the resistance of the STT-MTJ in the AP state; R ON0 represents the sum of the resistances of the transistors in the write operation structure other than the STT-MTJ when writing a "0"; R X0 is the reference resistance for writing a "0"; STT-MTJ flips from AP state to P state, copy-write "0" current becomes I W0_P , copy-write "0" voltage also changes to V X0_P ; current I W0_P and voltage V X0_P can be represented by the following equations (3) and (4): wherein R P represents the resistance of the STT-MTJ in the P state.

4. The write verify circuit of claim 1, wherein, In the initial state, the STT-MTJ is in P state, the first enable signal W RE of the write self-termination circuit is high level; the second enable signal W E is also high level; the process of writing data "1" of the STT-MRAM includes: The write current flows from the source line SL of the STT-MRAM to the bit line BL, and the STT-MRAM starts to write data "1"; The write current generates a copy write "1" current I through the current mirror W1_P ; the copy write "1" current I W1_P by the reference write "1" resistance R X1 converted into the copy write "1" voltage V X1_P , the copy write "1" voltage V X1_P a negative input of the comparator; When the write current duration is less than the STT-MTJ flipping delay time, the STT-MTJ does not occur flipping behavior, at this time, its resistance state is still P state, copy write "1" current is I W1_P , the negative input voltage of the comparator is V X1_P ; When the write current duration is greater than or equal to the STT-MTJ flip delay time, the STT-MTJ flips from the P state to the AP state, at which point the copy write "1" current becomes I W1_AP , and the negative input voltage of the comparator becomes V X1_AP . The change of the voltage at the negative input end of the comparator causes the change of the output level of the comparator, which causes the change of the level of the detection feedback signal COP, and the write self-termination circuit generates a driving enable signal according to the change of the detection feedback signal COP, so that the write driving is closed and the write "1" operation is completed.

5. The write verify circuit of claim 4, wherein, The reference voltage of the comparator is V REF1 , and the value range is: V X1_AP < V REF1 < V X1_P ; The copy write "1" voltage V X1_P satisfies: wherein R P represents the resistance of the STT-MTJ in the P state; R ON1 represents the sum of the resistances of the transistors other than the STT-MTJ in the write operation structure when writing "1"; R X1 is the reference resistance for writing "1"; V W represents the write drive voltage; When the STT-MTJ flips from the P state to the AP state, the STT-MRAM successfully writes the data "1", at which time the copy write "1" current and the copy write "1" voltage respectively become I W1_AP , V X1_AP , satisfying: wherein R AP represents the resistance of the STT-MTJ in the AP state.

6. An STT-MRAM memory comprising a plurality of memory cells, characterized in that, The storage unit is connected with the write verification circuit as claimed in any one of claims 1-5, and when information is written into the storage unit, the memory adopts the write verification circuit to verify the write operation. The write operation completion detection circuit comprises a current mirror, a reference resistance, a comparator and a buffer; The current mirror is used for copying a write current flowing through the STT-MRAM and generating a copied write current; the copied write current is converted into a copied write voltage through the reference resistance; the copied write voltage and a reference voltage generate the detection feedback signal COP through the comparator and the buffer; The write self-termination circuit generates a driving enable signal through calculation of an enable signal and the detection feedback signal COP, and the driving enable signal controls a write driving circuit to perform different write operations on the STT-MRAM; The write operation verification process of the write verification circuit comprises: When the write operation is completed, the state of the STT-MTJ is reversed, the resistance value is changed, and the write current flowing through the STT-MRAM is changed; The copied write current generated by the current mirror is changed, so that the copied write voltage input into the comparator is changed; The copied write voltage generates a new detection feedback signal COP through the comparator and the buffer; The self-termination circuit generates a termination write operation signal according to the level of the detection feedback signal COP and the enable signal, and the write driving circuit is closed, so that the write operation is completed; The write operation completion detection circuit further comprises a path control module, and the write operation completion detection circuit provides different operation paths for different write operations through the path control module; The write current flows from a bit line BL of the STT-MRAM to a source line SL, and the STT-MRAM starts to write data "0"; The change of the voltage at the negative input end of the comparator causes the change of the output level of the comparator, which causes the change of the level of the detection feedback signal COP, and the write self-termination circuit generates a driving enable signal according to the change of the detection feedback signal COP, so that the write driving is closed and the write "0" operation is completed. The write current flows from the source line SL of the STT-MRAM to the bit line BL, and the STT-MRAM starts to write data "1"; The change of the voltage at the negative input end of the comparator causes the change of the output level of the comparator, which causes the change of the level of the detection feedback signal COP, and the write self-termination circuit generates a driving enable signal according to the change of the detection feedback signal COP, so that the write driving is closed and the write "1" operation is completed. The storage unit is connected with the write verification circuit as claimed in any one of claims 1-5, and when information is written into the storage unit, the memory adopts the write verification circuit to verify the write operation.

Images