A non-volatile D flip-flop circuit

Abstract

The application relates to a non-volatile D flip-flop circuit. The non-volatile D flip-flop circuit formed by adopting the architecture mode of a latch circuit module, a self-enabled write circuit module, a non-volatile storage unit module, a read circuit module and a multiplexer module has only one working mode, so that the application has the characteristic of simple control timing. The self-enabled write circuit module and the non-volatile storage unit module arranged in the non-volatile D flip-flop circuit can realize real-time backup while reducing energy consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and in particular to a non-volatile D flip-flop circuit. Background Technology

[0002] As semiconductor process nodes continue to shrink, traditional D flip-flops face increasingly severe static power consumption problems. To address this issue, power gating technology has been widely adopted in recent years. When a computing system is about to enter standby mode, because the traditional D flip-flops used in the system are volatile, they cannot retain data after power loss. Therefore, it is necessary to back up the runtime data latched in the computing system to memory. When the computing system resumes operation, the backed-up runtime data needs to be restored to the traditional D flip-flops, thus achieving the "on-off" function. In the classic von Neumann architecture, data computation and storage are physically separated; therefore, power gating technology faces serious data transmission power consumption and latency problems.

[0003] Non-volatile D flip-flops have attracted significant attention in power-gated applications due to their low power consumption and low latency. The essence of a non-volatile D flip-flop is integrating a new type of non-volatile memory cell into a traditional D flip-flop. Among these new non-volatile memory cells, magnetic tunnel junctions (MTJs) are widely used in the design of non-volatile D flip-flops because they combine non-volatility, fast access speed, long lifetime, and ease of 3D integration. Currently, various non-volatile D flip-flops based on MTJs have been proposed, and their operating modes are mainly divided into four types: 1) Latch mode, the same as the traditional D flip-flop; 2) Backup mode, backing up the running data to the non-volatile memory cell before power failure; 3) Standby mode, turning off the power supply to reduce standby power consumption; 4) Recovery mode, turning on the power supply to restore the running data stored in the non-volatile memory cell to the non-volatile D flip-flop.

[0004] However, existing non-volatile D flip-flop schemes still have some problems:

[0005] 1) Compared with traditional D flip-flops, existing non-volatile D flip-flops have more complex control timing due to their four operating modes;

[0006] 2) When the computing system experiences frequent power outages, the data backup and recovery operations during runtime will result in significant energy consumption.

[0007] 3) Existing non-volatile D flip-flops do not have real-time backup capabilities and cannot cope with sudden power outages in the computing system. Summary of the Invention

[0008] To address the problems of existing non-volatile D flip-flops, the purpose of this invention is to design a non-volatile D flip-flop circuit with simple control timing, low power consumption, and real-time backup capability.

[0009] To achieve the above objectives, the present invention provides the following solution:

[0010] A non-volatile D flip-flop circuit includes: an input signal terminal, a clock signal terminal, a latch circuit module, a self-enable write circuit module, a non-volatile memory cell module, a read circuit module, a multiplexer module, and an output signal terminal;

[0011] The first input terminal of the latch circuit module is connected to the input signal terminal; the second input terminal of the latch circuit module is connected to the clock signal terminal; the first output terminal of the latch circuit module is connected to the first input terminal of the multiplexer module; the second output terminal of the latch circuit module is connected to the second input terminal of the self-enable write circuit module; the first input terminal of the self-enable write circuit module is connected to the clock signal terminal; the output terminal of the self-enable write circuit module is connected to the first input terminal of the non-volatile memory cell module; the input terminal of the read circuit module is connected to the clock signal terminal; the first output terminal of the read circuit module is connected to the second input terminal of the non-volatile memory cell module; the second output terminal of the read circuit module is connected to the second input terminal of the multiplexer module; the third output terminal of the read circuit module is connected to the third input terminal of the self-enable write circuit module; the third input terminal of the multiplexer module is connected to the clock signal terminal; and the output terminal of the multiplexer module is connected to the output signal terminal.

[0012] Preferably, the latching circuit module includes: a first inverter, a second inverter, and a third inverter;

[0013] The input terminal of the first inverter is connected to the input signal terminal; the output terminal of the first inverter is connected to the input terminal of the second inverter; the output terminal of the second inverter is connected to the input terminal of the third inverter and the first input terminal of the multiplexer module; the output terminal of the third inverter is connected to the connection path between the output terminal of the first inverter and the input terminal of the second inverter to output the inverted signal of the second inverter output signal; the inverted signal is input to the self-enabled write circuit module.

[0014] The first inverter and the third inverter are controlled by the clock signal input at the clock signal terminal.

[0015] Preferably, both the first inverter and the third inverter include: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0016] The source of the first PMOS transistor is connected to the power supply voltage; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the source of the first NMOS transistor; the drain of the first NMOS transistor is connected to the source of the second NMOS transistor; the drain of the second NMOS transistor is grounded; the gate of the first PMOS transistor is connected to the gate of the second NMOS transistor, and both the gates of the first PMOS transistor and the second NMOS transistor are connected to the input signal terminal; wherein, in the first inverter, the gate of the second PMOS transistor is connected to the clock signal, and the gate of the first NMOS transistor is connected to the inverted signal of the clock signal; in the third inverter, the gate of the second PMOS transistor is connected to the inverted signal of the clock signal, and the gate of the first NMOS transistor is connected to the clock signal.

[0017] Preferably, the non-volatile memory cell module includes: a first magnetic tunnel junction, a second magnetic tunnel junction, a third NMOS transistor, a fourth NMOS transistor, an A terminal, a B terminal, an H terminal, and an M terminal;

[0018] One end of the antiferromagnetic layer of the first magnetic tunnel junction is connected to the M terminal; the other end of the antiferromagnetic layer of the first magnetic tunnel junction is connected to the source of the third NMOS transistor; the drain of the third NMOS transistor is connected to the H terminal; the drain of the fourth NMOS transistor is connected to the M terminal; the source of the fourth NMOS transistor is connected to the other end of the antiferromagnetic layer of the second magnetic tunnel junction; one end of the antiferromagnetic layer of the second magnetic tunnel junction is connected to the H terminal; the upper end of the first magnetic tunnel junction is connected to the A terminal, and the upper end of the second magnetic tunnel junction is connected to the B terminal.

[0019] Preferably, the self-enabled write circuit module includes: a write logic control circuit and a write current generation circuit;

[0020] The first input terminal of the write logic control circuit and the first input terminal of the write current generation circuit are both connected to the second output terminal of the latch circuit module; the second input terminal of the write logic control circuit is connected to the third output terminal of the read circuit module; the third input terminal of the write logic control circuit is connected to the clock signal terminal; the output terminal of the write logic control circuit is connected to the second input terminal of the write current generation circuit; the output terminal of the write current generation circuit is the output terminal of the self-enabled write circuit module.

[0021] Preferably, the write logic control circuit includes: a fourth inverter, a fifth inverter, a first transmission gate, an XOR gate, a first NAND gate, and a sixth inverter;

[0022] The input terminal of the fourth inverter is connected to the third output terminal of the read circuit module; the output terminal of the fourth inverter is connected to the input terminal of the fifth inverter; the output terminal of the fifth inverter is connected to the input terminal of the first transmission gate; the output terminal of the first transmission gate is connected to the input terminal of the fourth inverter; the low-level signal control terminal of the first transmission gate is connected to the inverse signal terminal of the clock signal; the high-level signal control terminal of the first transmission gate is connected to the clock signal terminal; the first input terminal of the XOR gate is connected to the output terminal of the fifth inverter; the second input terminal of the XOR gate is connected to the output terminal of the second inverter; the output terminal of the XOR gate is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is connected to the clock signal terminal, and the output terminal of the first NAND gate outputs a write logic control signal; the output terminal of the first NAND gate is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter outputs the inverse signal of the write logic control signal.

[0023] Preferably, the write current generating circuit includes: a second NAND gate, a seventh inverter, a third NAND gate, an eighth inverter, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

[0024] The first input terminal of the second NAND gate is connected to the output terminal of the second inverter, and the second input terminal of the second NAND gate is connected to the output terminal of the sixth inverter. That is, the two input signals of the second NAND gate are the inverted signals of the second inverter output signal and the write logic control signal, respectively. The output signal of the second inverter is the output signal of the latch circuit module. The output terminal of the second NAND gate is connected to the input terminal of the seventh inverter. The first input terminal of the third NAND gate is connected to the connection path between the output terminal of the first inverter and the input terminal of the second inverter. The second input terminal of the third NAND gate is connected to the output terminal of the sixth inverter. The two input signals are the inverted signals of the first inverter output signal and the write logic control signal, respectively. The first inverter output signal is the inverted signal of the latch circuit module output signal. The output terminal of the third NAND gate is connected to the input terminal of the eighth inverter. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fifth NMOS transistor is grounded. The gate of the third PMOS transistor is connected to the third NMOS transistor. The output of the NOT gate is connected; the gate of the fifth NMOS transistor is connected to the output of the seventh inverter; the drain of the third PMOS transistor is connected to the M terminal of the non-volatile memory cell module; the source of the fourth PMOS transistor is connected to the power supply voltage; the drain of the fourth PMOS transistor is connected to the drain of the sixth NMOS transistor; the source of the sixth NMOS transistor is grounded; the gate of the fourth PMOS transistor is connected to the output of the second NAND gate; the gate of the sixth NMOS transistor is connected to the output of the eighth inverter; the drain of the fourth PMOS transistor is connected to the H terminal of the non-volatile memory cell module; the source of the fifth PMOS transistor is connected to the power supply voltage; the drain of the fifth PMOS transistor is connected to the A terminal of the non-volatile memory cell module; the gate of the fifth PMOS transistor is connected to the output of the first NAND gate; the source of the sixth PMOS transistor is connected to the power supply voltage; the drain of the sixth PMOS transistor is connected to the B terminal of the non-volatile memory cell module; the gate of the sixth PMOS transistor is connected to the output of the first NAND gate.

[0025] Preferably, the read circuit module includes: a second transmission gate, a seventh NMOS transistor, a third transmission gate, an eighth NMOS transistor, and a first buffer;

[0026] The input terminal of the second transmission gate is connected to the power supply voltage; the output terminal of the second transmission gate is connected to the M terminal of the non-volatile memory cell; the low-level signal control terminal of the second transmission gate is connected to the clock signal terminal; the high-level signal control terminal of the second transmission gate is connected to the inverted signal terminal of the clock signal; the drain of the seventh NMOS transistor is connected to the A terminal of the non-volatile memory cell module; the source of the seventh NMOS transistor is connected to the H terminal of the non-volatile memory cell module; the gate of the seventh NMOS transistor is connected to the inverted signal terminal of the clock signal; the eighth NMOS... The drain of the S transistor is connected to the B terminal of the non-volatile memory cell module; the source of the eighth NMOS transistor is grounded; the gate of the eighth NMOS transistor is connected to the inverse signal terminal of the clock signal; the input terminal of the third transmission gate is connected to the H terminal of the non-volatile memory cell module; the low-level signal control terminal of the third transmission gate is connected to the clock signal terminal; the high-level signal control terminal of the third transmission gate is connected to the inverse signal terminal of the clock signal; the input of the first buffer is connected to the output terminal of the third transmission gate; the output terminal of the first buffer serves as the output terminal of the read circuit module.

[0027] Preferably, the multiplexer module includes: a fourth transmission gate and a fifth transmission gate;

[0028] The input terminal of the fourth transmission gate is connected to the first output terminal of the latch circuit module; the input terminal of the fifth transmission gate is connected to the output terminal of the first buffer; the output terminal of the fourth transmission gate is connected to the output terminal of the fifth transmission gate; the low-level control signal terminal of the fourth transmission gate is connected to the opposite signal terminal of the clock signal, and the high-level control signal terminal of the fourth transmission gate is connected to the clock signal terminal; the low-level control signal terminal of the fifth transmission gate is connected to the clock signal terminal, and the high-level control signal terminal of the fifth transmission gate is connected to the opposite signal terminal of the clock signal.

[0029] Preferably, the multiplexer module is a 2-to-1 multiplexer.

[0030] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] The non-volatile D flip-flop circuit provided by this invention, through its architecture consisting of a latch circuit module, a self-enable write circuit module, a non-volatile memory cell module, a read circuit module, and a multiplexer module, allows the non-volatile D flip-flop circuit to have only one operating mode. Therefore, this invention features simple control timing. Furthermore, the use of the self-enable write circuit module and the non-volatile memory cell module can achieve real-time backup while reducing energy consumption. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 The structural block diagram of the non-volatile D flip-flop circuit provided by the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of a non-volatile memory unit module provided in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of the first non-volatile D flip-flop circuit provided in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of a second non-volatile D flip-flop circuit provided in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the structure of the third non-volatile D flip-flop circuit provided in the embodiments of the present invention;

[0038] Figure 6 This is a schematic diagram of the structure of the fourth non-volatile D flip-flop circuit provided in the embodiments of the present invention;

[0039] Figure 7 This is a schematic diagram of the fifth non-volatile D flip-flop circuit provided in an embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the sixth non-volatile D flip-flop circuit provided in an embodiment of the present invention;

[0041] Figure 9 This is a timing diagram provided for an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] The purpose of this invention is to provide a non-volatile D flip-flop circuit that features simple control timing, low energy consumption, and real-time backup capability.

[0044] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] like Figure 1 As shown, the non-volatile D flip-flop circuit provided by the present invention includes: an input signal terminal, a clock signal terminal, a latch circuit module 01, a self-enable write circuit module 02, a non-volatile memory cell module 03, a read circuit module 04, a multiplexer module 05, and an output signal terminal.

[0046] The first input terminal of latch circuit module 01 is connected to the input signal terminal. The second input terminal of latch circuit module 01 is connected to the clock signal terminal. The first output terminal of latch circuit module 01 is connected to the first input terminal of multiplexer module 05. The second output terminal of latch circuit module 01 is connected to the second input terminal of self-enable write circuit module 02. The first input terminal of self-enable write circuit module 02 is connected to the clock signal terminal. The second input terminal of self-enable write current module 02 is connected to the second output terminal of latch circuit module 01. The output terminal of self-enable write circuit module 02 is connected to the first input terminal of non-volatile memory cell module 03. The input terminal of read circuit module 04 is connected to the clock signal terminal. The first output terminal of read circuit module 04 is connected to the second input terminal of non-volatile memory cell module 03. The second output terminal of read circuit module 04 is connected to the second input terminal of multiplexer module 05. The third output terminal of read circuit module 04 is connected to the third input terminal of self-enable write circuit module 02. The third input terminal of multiplexer module 05 is connected to the clock signal terminal. The output terminal of multiplexer module 05 is connected to the output signal terminal.

[0047] The implementation method of the non-volatile D flip-flop circuit provided by the present invention mainly includes two steps:

[0048] Step 1: Under the control of a low-level clock signal, the read circuit module reads data from the non-volatile memory cell. Then, the read data is output through a 2-to-1 multiplexer module as the output of the non-volatile D flip-flop circuit. The read data at this time represents the data sampled by the flip-flop in the previous clock cycle. Simultaneously, under the control of a low-level clock signal, the latch circuit module samples the input signal of the non-volatile D flip-flop circuit.

[0049] Step Two: Under the control of a high-level clock signal, the latch circuit module latches the data sampled under a low-level clock control signal and outputs it through a 2-to-1 multiplexer module. The data latched by the latch circuit module is then transmitted to the self-enabling write circuit module as the data to be written to the non-volatile memory module. The data read by the read circuit module under a low-level clock signal is transmitted and latched to the self-enabling write circuit module; this data is the data stored in the non-volatile memory module. Simultaneously, the self-enabling write circuit module compares the data to be written with the data stored in the non-volatile memory module to determine whether to perform a write operation. If the data to be written is the same as the data stored in the non-volatile memory module, the self-enabling write circuit module will not perform a write operation. If the two data are different, the self-enabling write circuit module will perform a write operation on the non-volatile memory module.

[0050] The advantages of the non-volatile D flip-flop circuit provided above are explained below with specific embodiments.

[0051] like Figure 2 As shown, the non-volatile memory cell module 03 used in this invention consists of two voltage-regulated spin-orbit torque (VGSOT) magnetic tunnel junctions (MTJs) and two NMOS transistors, with a total of four input / output ports (M, H, A, B). The use of voltage-regulated spin-orbit torque (VGSOT) magnetic tunnel junctions in the non-volatile memory cell module enables the aforementioned non-volatile D flip-flop circuit to possess advantages such as non-volatility, low write current, low write power consumption, fast access speed, and deterministic flip-flop capability without an external magnetic field.

[0052] In this configuration, the VGSOT-MTJ at the top is defined as MTJ1, and the VGSOT-MTJ at the bottom is defined as MTJ2. The specific connections are as follows: the M terminal is connected to the T2 port of MTJ1, and the T3 port of MTJ1 is connected to the source of the first NMOS transistor. The drain of the first NMOS transistor is connected to the H terminal. The T1 terminal of MTJ1 is connected to the A terminal. The M terminal is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to the T3 port of MTJ2. The T2 port of MTJ2 is connected to the H terminal. The T1 terminal of MTJ2 is connected to the B terminal.

[0053] The following uses MTJ1 as an example to illustrate the effect of current flow direction on the MTJ's magnetoresistive state. To reliably change the magnetoresistive state of MTJ1, two conditions must be met: a forward bias voltage must be applied to port T1 of MTJ1, and current must be applied to either port T2 or T3. When a forward bias voltage is applied to port T1, and current is applied to port T2, flowing from port T2 to port T3, if this current exceeds the critical current required for the MTJ1's magnetoresistive state to reverse, the MTJ1's magnetoresistive state is written as a high-resistance state. When a forward bias voltage is applied to port T1, and current is applied to port T3, flowing from port T3 to port T2, if this current exceeds the critical current required for the MTJ1's magnetoresistive state to reverse, the MTJ1's stored state is written as a low-resistance state. For MTJ2, the effect of current flow direction on the MTJ's magnetoresistive state is the same as for MTJ1. Figure 2 As can be seen, MTJ1 and MTJ2 are connected in anti-parallel. That is, when the current in MTJ1 flows from port T2 to port T3, the current in MTJ2 flows from port T3 to port T2. It is important to note that the initial magnetoresistive states of MTJ1 and MTJ2 are set to opposite magnetoresistive states. Assuming the magnetoresistive state of MTJ1 is magnetoresistive 1 and the magnetoresistive state of MTJ2 is magnetoresistive 2, then the initial states (magnetoresistive 1, magnetoresistive 2) of MTJ1 and MTJ2 are either (high resistance, low resistance) or (low resistance, high resistance). The data storage state of the non-volatile memory cell is determined by this pair of opposite magnetoresistive states. Furthermore, because MTJ1 and MTJ2 are connected in anti-parallel, under opposite initial states and the same write current, the magnetoresistive 1 and magnetoresistive 2 of MTJ1 and MTJ2 are always opposite. When (magnetoresistive 1, magnetoresistive 2) is in (high resistance state, low resistance state), the data stored in the non-volatile memory cell is "0". When (magnetoresistive 1, magnetoresistive 2) is in (low resistance state, high resistance state), the data stored in the non-volatile memory cell is "1".

[0054] The traditional non-volatile D flip-flop structure is constructed by adding a non-volatile memory cell without changing the conventional D flip-flop structure. This embodiment of the invention proposes a non-volatile D flip-flop circuit that differs from the traditional non-volatile D flip-flop structure, as shown in... Figure 1 As shown.

[0055] The non-volatile D flip-flop circuit of the present invention includes: a latch circuit module 01, a self-enable write circuit module 02, a non-volatile memory cell module 03, a read circuit module 04, and a multiplexer module 05. In the present invention, the multiplexer module 05 can be a 2-to-1 multiplexer.

[0056] Under the control of a low-level clock signal, the read circuit module 04 reads data from the non-volatile memory module 03 and transmits the result to the multiplexer module 05 for output. Simultaneously, the latch circuit module 01 samples the input signal. Under the control of a high-level clock signal, the latch circuit module 01 latches the sampled signal obtained under the low clock control signal and transmits it to the multiplexer module 05 for output. At the same time, the output signal of the read circuit module under the low-level clock signal (i.e., the data stored in the non-volatile memory module 03) is transmitted to the self-enabled write circuit module 02 and compared with the output signal of the latch circuit module under the high-level clock signal (i.e., the data to be written). If they are the same, the self-enabled write circuit module 02 will not perform a write operation. If they are different, the self-enabled write circuit module 02 is activated, and the new data will be backed up to the non-volatile memory module 03. In the above structure, other circuits capable of implementing the functions of related modules are also within the scope of protection of this invention; the accompanying drawings are only one preferred embodiment.

[0057] Another embodiment of the non-volatile D flip-flop circuit in this invention is, for example... Figure 3 As shown. Optionally, the latch circuit module 01 may include a first inverter IN1 controlled by a clock, a second inverter IN2, and a third inverter IN3 controlled by a clock. The circuit that implements the function of the latch circuit module in the above structure also falls within the protection scope of this invention; the accompanying drawings are merely one preferred embodiment.

[0058] In this inverter, the input terminal of the clock-controlled first inverter IN1 is connected to the input signal D, and the output terminal of IN1 is connected to the input terminal of the second inverter IN2. The output terminal of the second inverter IN2 is connected to the input terminal of the clock-controlled IN3, and the output terminal of IN3 is connected to the input terminal of the second inverter IN2. The clock-controlled inverter structure includes two PMOS transistors and two NMOS transistors. The specific connection method is as follows: the source of the first PMOS transistor in the clock-controlled inverter is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the second PMOS transistor is connected to the source of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor. The drain of the second NMOS transistor is connected to the ground signal GND. The gates of the first PMOS transistor and the second NMOS transistor are connected and are both controlled by a certain input signal. The gates of the second PMOS transistor and the first NMOS transistor are controlled by a clock signal (clock signal inverted) and a clock signal inverted (clock signal), respectively. The terms "first," "second," etc., used here only describe the device order within the clock-controlled inverter structure and do not participate in the device ordering when describing other structures below. Therefore, the first inverter IN1 is controlled by the clock signal CLK (i.e., the gate of the second PMOS transistor in IN1 is connected to the clock signal CLK, and the gate of the first NMOS transistor is connected to CLKB), while the third inverter IN3 is controlled by the clock signal CLKB (i.e., the gate of the second PMOS transistor in IN3 is connected to the clock signal CLKB, and the gate of the first NMOS transistor is connected to CLK). The output QM of the second inverter serves as the output of the latch circuit module.

[0059] Another embodiment of the non-volatile D flip-flop circuit in this invention is, for example... Figure 4 As shown. Optionally, the self-enabled write circuit module 02 may include a write logic control circuit 021 and a write current generation circuit 022. The output of the latch circuit module 01 is simultaneously transmitted to both the write logic control circuit 021 and the write current generation circuit 022. The output of the read circuit module 04 is transmitted to the write logic control circuit 021 under the control of an appropriate clock signal. Circuits capable of implementing the self-enabled write circuit module function in the above structure are also within the scope of protection of this invention; the accompanying drawings are merely one preferred embodiment.

[0060] The write logic control circuit 021 compares the output of the read circuit module 04 (data stored in the non-volatile memory cell) with the output of the latch circuit module 01 (data to be written) to generate the corresponding write logic control signal required by the write current generation circuit 022. When the two data are different, the write logic control signal is activated, thereby controlling the write current generation circuit 022 to perform a write operation on the non-volatile memory cell 03.

[0061] Another embodiment of the non-volatile D flip-flop circuit in this invention is, for example... Figure 5 As shown, the write logic control circuit 021 may include a fourth inverter IN4, a first transmission gate TG1, a fifth inverter IN5, an XOR gate, a first NAND gate NAND1, and a sixth inverter IN6. Circuits capable of implementing the write logic control circuit function in the above structure also fall within the scope of protection of this invention. The accompanying drawings are merely one preferred embodiment.

[0062] In this circuit, the input of the fourth inverter IN4 is connected to the output QN of the read circuit module 04, and the output of the fourth inverter IN4 is connected to the input of the fifth inverter IN5. The output of the fifth inverter IN5 is connected to the first transmission gate TG1 and also to one input of the XOR gate. The other end of the first transmission gate TG1 is connected to the input of the fourth inverter IN4. The other input of the XOR gate is connected to the output QM of the latch circuit module. The output of the XOR gate, together with the clock signal CLK, serves as the input of the first NAND gate NAND1. The output of the first NAND gate NAND1 is the write logic control signal WE. The write logic control signal WE serves as the input of the sixth inverter IN6, and the output of the sixth inverter IN6 is the inverse of the write logic control signal.

[0063] The write current generation circuit may include a second NAND gate NAND2, a third NAND gate NAND3, a seventh NAND gate IN7 and an eighth NAND gate IN8, PMOS transistors P1 to P4, and NMOS transistors N1 to N2.

[0064] In this circuit, the output QM of the latch circuit module and the inverted signal WEB of the write logic signal generated by the write logic control circuit are used together as the input of the second NAND gate NAND2. The output of the second NAND gate NAND2 is the write current signal V1. The write current signal V1 is used as the input of the seventh NAND gate IN7, and the output of the seventh NAND gate is the write current signal V4. The output QMB of the latch circuit module and the inverted signal WEB of the write logic signal generated by the write logic control circuit are used together as the input of the third NAND gate NAND3, and the output of the third NAND gate NAND3 is the write current signal V2. The write current signal V2 is used as the input of the eighth NAND gate IN8, and the output of the eighth NAND gate IN8 is the write current signal V3. The source of the PMOS transistor P1 is connected to the power supply voltage VDD, the drain of the PMOS transistor P1 is connected to the M terminal of the non-volatile memory cell, and the gate of the PMOS transistor P1 is connected to the write current signal V2. The source of NMOS transistor N1 is connected to ground (GND), the drain of NMOS transistor N1 is connected to the M terminal of the non-volatile memory cell, and the gate of NMOS transistor N1 is connected to the write current signal V4. The source of PMOS transistor P2 is connected to the power supply voltage VDD, the drain of PMOS transistor P2 is connected to the H terminal of the non-volatile memory cell, and the gate of PMOS transistor P2 is connected to the write current signal V1. The source of NMOS transistor N2 is connected to ground (GND), the drain of NMOS transistor N2 is connected to the H terminal of the non-volatile memory cell, and the gate of NMOS transistor N2 is connected to the write current signal V3. Terminals A and B of the non-volatile memory cell are connected to the drains of PMOS transistors P3 and P4, respectively. The sources of PMOS transistors P3 and P4 are connected to the power supply voltage, and the gates of PMOS transistors P3 and P4 are connected to the write logic control signal WE. Specifically, the gates of the two NMOS transistors used to control the current path in the non-volatile memory cell module are connected to the WEB signal, which is the inverse of the write logic control signal.

[0065] Another embodiment of the non-volatile D flip-flop circuit in this invention is, for example... Figure 6 As shown, the read circuit module 04 may include a second transmission gate TG2 and a third transmission gate TG3, NMOS transistors N4 and N3, and a buffer. The circuit that enables the read circuit module function in the above structure is also within the scope of protection of this invention; the accompanying drawings are merely one preferred embodiment.

[0066] In this circuit, one end of the second transmission gate TG2 is connected to the power supply voltage VDD, and the other end is connected to the M terminal of the non-volatile memory cell. The drain of NMOS transistor N4 is connected to the A terminal of the non-volatile memory cell, and the source of NMOS transistor N4 is connected to the H terminal of the non-volatile memory cell. The drain of NMOS transistor N3 is connected to the B terminal of the non-volatile memory cell, and the source of NMOS transistor N3 is connected to the ground signal GND. The H terminal of the non-volatile memory cell is connected to the third transmission gate TG3. The other end of the third transmission gate TG3 is connected to the buffer, and the output QN of the other end of the buffer serves as the output of the read circuit module. Specifically, the low-level enable signals of the second transmission gate TG2 and the third transmission gate TG3 are controlled by the clock signal CLK, and the high-level enable signals are controlled by the inverse of the clock signal CLKB.

[0067] Another embodiment of the non-volatile D flip-flop circuit in this invention is, for example... Figure 7 As shown, the 2-to-1 multiplexer 05 may include a fourth transmission gate TG4 and a fifth transmission gate TG5. The low-level enable signal of the fourth transmission gate TG4 is controlled by the inverted clock signal CLKB, and its high-level enable signal is controlled by the clock signal CLK. Similarly, the low-level enable signal of the fifth transmission gate TG5 is controlled by the clock signal CLK, and its high-level enable signal is controlled by the inverted clock signal CLKB. The output QM of the latch circuit module serves as the input of the fourth transmission gate TG4, and the output QN of the read circuit module serves as the input of the fifth transmission gate TG5. The outputs of the fourth transmission gate TG4 and the fifth transmission gate TG5 are connected together to form the output Q of the non-volatile D flip-flop circuit.

[0068] Another embodiment of the non-volatile D flip-flop circuit in this invention is, for example... Figure 8 As shown, with Figure 8 The working mode of the non-volatile D flip-flop circuit proposed in this invention will be explained in detail using examples.

[0069] When the clock signal CLK is low, the input signal D is input to the latch circuit module through the first inverter IN1, which is controlled by the low-level clock of CLK. The output signal of the first inverter is QMB. Simultaneously, the second inverter IN2 in the latch circuit module is turned on, and its output signal is QM. This operation is the sampling process of the input signal. At the same time, the read circuit module reads the data stored in the non-volatile memory cell module, obtaining the output signal QN. Under the control of the low-level clock signal CLK, the second transmission gate TG2 is turned on, and current flows from TG2 to the M terminal of the non-volatile memory cell. Inside the non-volatile memory cell module, the inverted signal WEB of the write logic control signal WE is low, therefore the two NMOS transistors controlled by the WEB signal are turned off during the operation of the read circuit module. Current flows from the M terminal through the T2 and T1 terminals of MTJ1 and exits from the A terminal of the non-volatile memory cell. The clock signal CLKB is currently high, turning on the third NMOS transistor N3. Since the source of the third NMOS transistor N3 is connected to the H terminal of the non-volatile memory cell, current flows through the third NMOS transistor N3 and then to the H terminal of the non-volatile memory cell. After flowing in from the H terminal, the current flows through the T2 and T1 terminals of MTJ2 and exits from the B terminal of the non-volatile memory cell module. With the clock signal CLKB currently high, the fourth NMOS transistor N4 turns on, and the current ultimately flows to GND. The third transmission gate TG3 is connected to the H terminal of the non-volatile memory cell, and its output is connected to the buffer. The output QN of the buffer serves as the output of the read circuit module. This read circuit is essentially equivalent to a voltage divider. When the magnetoresistances of MTJ1 and MTJ2 are in low and high resistance states respectively, the voltage at point H is high, and the output through the buffer is data "1". When the magnetoresistances of MTJ1 and MTJ2 are in high and low resistance states respectively, the voltage at point H is low, and the output through the buffer is data "0". In the 2-to-1 multiplexer, transmission gate TG5 is turned on, and the output signal QN obtained from the detection circuit is used as the output Q of the non-volatile D flip-flop circuit. When the clock signal is high, the latch latches the signal sampled when CLK is low, and the output signals at this time are still QM and QMB. Transmission gate TG4 in the 2-to-1 multiplexer is turned on, and the output signal QM obtained from the latching circuit module is used as the output Q of the non-volatile D flip-flop circuit. Simultaneously, QM and QMB determine the current direction of the adaptive write circuit, thus determining the data storage state of the non-volatile memory cell during a write operation.

[0070] The specific steps of the write operation are as follows:

[0071] (1) Since the output signal QN obtained when the CLK clock signal is low represents the data storage state of the non-volatile memory cell before a write operation is performed, in order to avoid repeated write operations on the non-volatile memory cell and cause large energy consumption, it is necessary to compare the output QM (i.e., the data to be written) of the latch circuit module with QN. If QM and QN are the same, the data currently stored in the non-volatile memory cell module is the same as the data to be written QM, and no write operation is required, so no valid write logic control signal WE is generated. If the two are different, the write logic control signal WE is activated, and the write current generation circuit will perform a write operation on the non-volatile memory cell. The write logic control signal WE is generated by the write logic control circuit. The comparison process is as follows: When the CLK clock signal is high, the QN signal will be latched by the latch composed of IN4, IN5 and TG1. Then, the QN signal and the QM signal are used as inputs of the XOR gate to perform an XOR operation and compare whether they are the same. The result obtained from the comparison, along with the CLK clock signal, is input to the first NAND gate NAND1 to obtain the write control signal WE. WE is then passed through the sixth inverter IN6 to obtain its inverted signal WEB.

[0072] (2) After receiving the WEB signal, the write current generation circuit will generate four write current signals. The write current signal generation process is as follows: QM and WEB are input together to the second NAND gate NAND2 to obtain the write current signal V1, which then passes through the inverter IN7 to obtain the write current signal V4. QMB and WEB are input together to the third NAND gate NAND3 to obtain the write current signal V2, which then passes through the inverter IN8 to obtain the write current signal V3.

[0073] (3) If the data to be written, QM, is data '1', the four write current signals V1, V2, V3, and V4 are low, high, low, and high, respectively. The writing process of the non-volatile memory cell is as follows: the current flows from PMOS transistor P2 to the H terminal of the non-volatile memory cell, then flows out from the M terminal, and flows to GND through NMOS transistor N1. At the same time, the WE write logic control signal is low, PMOS transistors P3 and P4 are turned on, and a power supply voltage is applied to the A and B terminals of the non-volatile memory cell module (i.e., the T1 ports of MTJ1 and MTJ2) to ensure the correct writing of MTJ. When the write operation is completed, MTJ1 and MTJ2 are written to the low-resistance state and the high-resistance state, respectively, that is, the data of the non-volatile memory cell is written as data '1'. If the data to be written, QM, is data '0', the four write current signals V1, V2, V3, and V4 are high, low, high, and low, respectively. The write process for the non-volatile memory cell module is as follows: Current flows from PMOS transistor P1 to the M terminal of the non-volatile memory cell module, then flows out from the H terminal, through NMOS transistor N2, and to GND. Simultaneously, the WE write logic control signal is low, PMOS transistors P3 and P4 are turned on, and a power supply voltage is applied to the A and B terminals of the non-volatile memory cell module (i.e., the T1 ports of MTJ1 and MTJ2) to ensure correct writing to MTJ. When the write operation is complete, MTJ1 and MTJ2 are written to high-impedance and low-impedance states respectively, meaning the data in the non-volatile memory cell module is now written as data '0'.

[0074] Figure 9 The diagram shows the operating waveforms of the non-volatile D flip-flop circuit of this invention. This non-volatile D flip-flop circuit is level-triggered. When the clock signal input terminal CLK is low, the non-volatile D flip-flop circuit maintains the state of the previous high-level clock signal, independent of the input terminal D. When the clock signal input terminal CLK is high, the non-volatile D flip-flop circuit flips, and its flip state is determined by the signal at the input terminal D of the non-volatile D flip-flop circuit; at this time, Q = D.

[0075] Based on the above description, the non-volatile D flip-flop circuit provided by the present invention has the following advantages compared with the prior art:

[0076] 1. Because the non-volatile D flip-flop circuit of this invention operates in a mode where a high level in each clock cycle backs up and saves the sampled data, this invention achieves real-time data backup functionality.

[0077] 2. Because a self-enabled write circuit module is used, the write logic control circuit included in the self-enabled write circuit module judges the data to be written against the data stored in the non-volatile memory cell module, comparing whether a write operation is needed on the non-volatile memory cell module. When the two data are the same, the self-enabled write circuit module will not perform a write operation. Therefore, repeated writing to the non-volatile memory cell module is avoided, and this invention has the advantage of low power consumption.

[0078] 3. The non-volatile D flip-flop circuit of the present invention has only one operating mode, thus the present invention has the characteristic of simple control timing.

[0079] 4. Since the non-volatile memory cell module used in this invention is composed of a magnetic tunnel structure with voltage-controlled spin-orbit moment effect, the magnetic tunnel junction is characterized by small drive current and low write power consumption. Therefore, the non-volatile D flip-flop circuit of this invention has low power consumption.

[0080] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0081] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A non-volatile D flip-flop circuit, characterized in that, include: Input signal terminal, clock signal terminal, latch circuit module, self-enable write circuit module, non-volatile memory cell module, read circuit module, multiplexer module, and output signal terminal; The first input terminal of the latch circuit module is connected to the input signal terminal; the second input terminal of the latch circuit module is connected to the clock signal terminal; the first output terminal of the latch circuit module is connected to the first input terminal of the multiplexer module; the second output terminal of the latch circuit module is connected to the second input terminal of the self-enable write circuit module; the first input terminal of the self-enable write circuit module is connected to the clock signal terminal; the output terminal of the self-enable write circuit module is connected to the first input terminal of the non-volatile memory cell module; the input terminal of the read circuit module is connected to the clock signal terminal; the first output terminal of the read circuit module is connected to the second input terminal of the non-volatile memory cell module; the second output terminal of the read circuit module is connected to the second input terminal of the multiplexer module; the third output terminal of the read circuit module is connected to the third input terminal of the self-enable write circuit module; the third input terminal of the multiplexer module is connected to the clock signal terminal; and the output terminal of the multiplexer module is connected to the output signal terminal.

2. The non-volatile D flip-flop circuit according to claim 1, characterized in that, The latching circuit module includes: a first inverter, a second inverter, and a third inverter; The input terminal of the first inverter is connected to the input signal terminal; the output terminal of the first inverter is connected to the input terminal of the second inverter; the output terminal of the second inverter is connected to the input terminal of the third inverter and the first input terminal of the multiplexer module; the output terminal of the third inverter is connected to the connection path between the output terminal of the first inverter and the input terminal of the second inverter to output the inverted signal of the second inverter output signal; the inverted signal is input to the self-enabled write circuit module. The first inverter and the third inverter are controlled by the clock signal input at the clock signal terminal.

3. The non-volatile D flip-flop circuit according to claim 2, characterized in that, Both the first inverter and the third inverter include: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The source of the first PMOS transistor is connected to the power supply voltage; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the source of the first NMOS transistor; the drain of the first NMOS transistor is connected to the source of the second NMOS transistor; the drain of the second NMOS transistor is grounded; the gate of the first PMOS transistor is connected to the gate of the second NMOS transistor, and both the gates of the first PMOS transistor and the second NMOS transistor are connected to the input signal terminal; wherein, in the first inverter, the gate of the second PMOS transistor is connected to the clock signal, and the gate of the first NMOS transistor is connected to the inverted signal of the clock signal; in the third inverter, the gate of the second PMOS transistor is connected to the inverted signal of the clock signal, and the gate of the first NMOS transistor is connected to the clock signal.

4. The non-volatile D flip-flop circuit according to claim 2, characterized in that, The non-volatile memory cell module includes: a first magnetic tunnel junction, a second magnetic tunnel junction, a third NMOS transistor, a fourth NMOS transistor, an A terminal, a B terminal, an H terminal, and an M terminal; One end of the antiferromagnetic layer of the first magnetic tunnel junction is connected to the M terminal; the other end of the antiferromagnetic layer of the first magnetic tunnel junction is connected to the source of the third NMOS transistor; the drain of the third NMOS transistor is connected to the H terminal; the drain of the fourth NMOS transistor is connected to the M terminal; the source of the fourth NMOS transistor is connected to the other end of the antiferromagnetic layer of the second magnetic tunnel junction; one end of the antiferromagnetic layer of the second magnetic tunnel junction is connected to the H terminal; the upper end of the first magnetic tunnel junction is connected to the A terminal, and the upper end of the second magnetic tunnel junction is connected to the B terminal.

5. The non-volatile D flip-flop circuit according to claim 4, characterized in that, The self-enabled write circuit module includes: a write logic control circuit and a write current generation circuit; The first input terminal of the write logic control circuit and the first input terminal of the write current generation circuit are both connected to the second output terminal of the latch circuit module; the second input terminal of the write logic control circuit is connected to the third output terminal of the read circuit module; the third input terminal of the write logic control circuit is connected to the clock signal terminal; the output terminal of the write logic control circuit is connected to the second input terminal of the write current generation circuit; the output terminal of the write current generation circuit is the output terminal of the self-enabled write circuit module.

6. The non-volatile D flip-flop circuit according to claim 5, characterized in that, The write logic control circuit includes: a fourth inverter, a fifth inverter, a first transmission gate, an XOR gate, a first NAND gate, and a sixth inverter; The input terminal of the fourth inverter is connected to the third output terminal of the read circuit module; the output terminal of the fourth inverter is connected to the input terminal of the fifth inverter; the output terminal of the fifth inverter is connected to the input terminal of the first transmission gate; the output terminal of the first transmission gate is connected to the input terminal of the fourth inverter; the low-level signal control terminal of the first transmission gate is connected to the inverse signal terminal of the clock signal; the high-level signal control terminal of the first transmission gate is connected to the clock signal terminal; the first input terminal of the XOR gate is connected to the output terminal of the fifth inverter; the second input terminal of the XOR gate is connected to the output terminal of the second inverter; the output terminal of the XOR gate is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is connected to the clock signal terminal, and the output terminal of the first NAND gate outputs a write logic control signal; the output terminal of the first NAND gate is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter outputs the inverse signal of the write logic control signal.

7. The non-volatile D flip-flop circuit according to claim 6, characterized in that, The write current generation circuit includes: a second NAND gate, a seventh inverter, a third NAND gate, an eighth inverter, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The first input terminal of the second NAND gate is connected to the output terminal of the second inverter, and the second input terminal of the second NAND gate is connected to the output terminal of the sixth inverter. That is, the two input signals of the second NAND gate are the inverted signals of the second inverter output signal and the write logic control signal, respectively. The second inverter output signal is the output signal of the latch circuit module. The output terminal of the second NAND gate is connected to the input terminal of the seventh inverter. The first input terminal of the third NAND gate is connected to the connection path between the output terminal of the first inverter and the input terminal of the second inverter. The second input terminal of the third NAND gate is connected to the output terminal of the sixth inverter. The two input signals are the inverted signals of the first inverter output signal and the write logic control signal, respectively. The first inverter output signal is the inverted signal of the latch circuit module output signal. The output terminal of the third NAND gate is connected to the input terminal of the eighth inverter. The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fifth NMOS transistor is grounded. The gate of the third PMOS transistor is connected to the... The output of the third NMOS transistor is connected; the gate of the fifth NMOS transistor is connected to the output of the seventh inverter; the drain of the third PMOS transistor is connected to the M terminal of the non-volatile memory cell module; the source of the fourth PMOS transistor is connected to the power supply voltage; the drain of the fourth PMOS transistor is connected to the drain of the sixth NMOS transistor; the source of the sixth NMOS transistor is grounded; the gate of the fourth PMOS transistor is connected to the output of the second NMOS transistor; the gate of the sixth NMOS transistor is connected to the output of the eighth inverter; the drain of the fourth PMOS transistor is connected to the H terminal of the non-volatile memory cell module; the source of the fifth PMOS transistor is connected to the power supply voltage; the drain of the fifth PMOS transistor is connected to the A terminal of the non-volatile memory cell module; the gate of the fifth PMOS transistor is connected to the output of the first NMOS gate; the source of the sixth PMOS transistor is connected to the power supply voltage; the drain of the sixth PMOS transistor is connected to the B terminal of the non-volatile memory cell module; the gate of the sixth PMOS transistor is connected to the output of the first NMOS gate.

8. The non-volatile D flip-flop circuit according to claim 7, characterized in that, The read circuit module includes: a second transmission gate, a seventh NMOS transistor, a third transmission gate, an eighth NMOS transistor, and a first buffer; The input terminal of the second transmission gate is connected to the power supply voltage; the output terminal of the second transmission gate is connected to the M terminal of the non-volatile memory cell; the low-level signal control terminal of the second transmission gate is connected to the clock signal terminal; the high-level signal control terminal of the second transmission gate is connected to the inverted signal terminal of the clock signal; the drain of the seventh NMOS transistor is connected to the A terminal of the non-volatile memory cell module; the source of the seventh NMOS transistor is connected to the H terminal of the non-volatile memory cell module; the gate of the seventh NMOS transistor is connected to the inverted signal terminal of the clock signal; the eighth NMOS... The drain of the S transistor is connected to the B terminal of the non-volatile memory cell module; the source of the eighth NMOS transistor is grounded; the gate of the eighth NMOS transistor is connected to the inverse signal terminal of the clock signal; the input terminal of the third transmission gate is connected to the H terminal of the non-volatile memory cell module; the low-level signal control terminal of the third transmission gate is connected to the clock signal terminal; the high-level signal control terminal of the third transmission gate is connected to the inverse signal terminal of the clock signal; the input of the first buffer is connected to the output terminal of the third transmission gate; the output terminal of the first buffer serves as the output terminal of the read circuit module.

9. The non-volatile D flip-flop circuit according to claim 8, characterized in that, The multiplexer module includes: a fourth transmission gate and a fifth transmission gate; The input terminal of the fourth transmission gate is connected to the first output terminal of the latch circuit module; the input terminal of the fifth transmission gate is connected to the output terminal of the first buffer; the output terminal of the fourth transmission gate is connected to the output terminal of the fifth transmission gate; the low-level control signal terminal of the fourth transmission gate is connected to the opposite signal terminal of the clock signal, and the high-level control signal terminal of the fourth transmission gate is connected to the clock signal terminal; the low-level control signal terminal of the fifth transmission gate is connected to the clock signal terminal, and the high-level control signal terminal of the fifth transmission gate is connected to the opposite signal terminal of the clock signal.

10. The non-volatile D flip-flop circuit according to claim 9, characterized in that, The multiplexer module is a 2-to-1 multiplexer.

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