Chip packaging structure and preparation method

Abstract

A packaging structure and a preparation method thereof, the packaging structure comprising: a first heat dissipation structure, a first electrode, a second electrode, a third electrode, a fourth electrode and a connection structure, wherein: the first heat dissipation structure is arranged on the back of a chip; the first electrode, its upper surface is coupled to the first lead-out terminal of the chip, and its lower surface is coupled to the upper surface of the third electrode; the second electrode, its upper surface is coupled to the second lead-out terminal of the chip, and its lower surface is coupled to the upper surface of the fourth electrode; the lower surfaces of the third electrode and the fourth electrode are both connected to a PCB board; the connection structure connects the first heat dissipation structure and the first electrode, and has no contact with the chip. The above scheme can improve the heat dissipation performance of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip packaging structure and a preparation method thereof. Background Art

[0002] With the rise of third-generation compound semiconductor materials, high-frequency and high-power applications have increasingly higher requirements for heat dissipation and anti-interference of chips. At the same time, the characteristics of compound semiconductor power device chips in the gallium nitride (GaN) system make their main active layers concentrated on the upper surface of the device. Horizontal structure devices and high-frequency applications have brought new challenges to packaging and also provided opportunities for new packaging forms. Summary of the invention

[0003] The embodiment of the present invention solves the technical problem that the heat dissipation effect of the chip is poor.

[0004] To solve the above technical problems, an embodiment of the present invention provides a chip packaging structure, including: a first heat dissipation structure, a first electrode, a second electrode, a third electrode, and a fourth electrode, wherein: the first heat dissipation structure is arranged on the back side of the chip; the first electrode, whose upper surface is coupled to the first lead-out terminal of the chip, and whose lower surface is coupled to the upper surface of the third electrode; the second electrode, whose upper surface is coupled to the second lead-out terminal of the chip, and whose lower surface is coupled to the upper surface of the fourth electrode; the lower surfaces of the third electrode and the fourth electrode are both connected to a PCB board.

[0005] Optionally, the connection structure connects the first heat dissipation structure and the first electrode, and has no contact with the chip.

[0006] Optionally, the first heat dissipation structure has a first end extending out of the back side of the chip, and a second end arranged on the back side of the chip; the first end of the first heat dissipation structure is an end connected to the connecting structure, and the second end of the first heat dissipation structure is the other end of the first heat dissipation structure in the horizontal direction.

[0007] Optionally, the second end of the first heat dissipation structure extends out of the back side of the chip.

[0008] Optionally, the first end of the first electrode is located within the range of the chip, and the second end of the first electrode extends outside the range of the chip; the first end of the second electrode is located within the range of the chip, and the second end of the second electrode extends outside the range of the chip.

[0009] Optionally, the second end of the third electrode extends beyond the range of the first electrode, and the first end of the third electrode is located within the range of the first electrode; the second end of the fourth electrode extends beyond the range of the second electrode, and the first end of the fourth electrode is located within the range of the second electrode.

[0010] Optionally, a distance between the first end of the third electrode and the first end of the fourth electrode is greater than a distance between the first end of the first electrode and the first end of the second electrode.

[0011] Optionally, the chip packaging structure further includes: a second heat dissipation structure; the lower surface of the second heat dissipation structure contacts the upper surface of the first heat dissipation structure, and the upper surface of the second heat dissipation structure extends to expose the surface of the chip packaging structure.

[0012] Optionally, the connection structure includes any one of the following: a solder ball, a copper column.

[0013] An embodiment of the present invention provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure provided by any of the above embodiments, including: providing a heat dissipation structure; the heat dissipation structure includes a first heat dissipation structure; placing a chip and a connection structure, and performing molding; placing the first heat dissipation structure on the back of the chip, and the filling height of the molding material is flush with the lower surface of the first lead-out terminal and the second lead-out terminal of the chip; respectively setting a first electrode, a second electrode, a third electrode and a fourth electrode; and filling other empty spaces.

[0014] An embodiment of the present invention provides another method for preparing a chip packaging structure, which is used to prepare the chip packaging structure provided by any of the above embodiments, including: providing a substrate and performing molding, the substrate including a first electrode, a second electrode, a third electrode and a fourth electrode; placing a chip and a connecting structure; the front side of the chip faces the substrate; the filling height of the molding material is flush with the upper surfaces of the first electrode and the second electrode; setting a heat dissipation structure; the heat dissipation structure includes a first heat dissipation structure; and filling other empty spaces.

[0015] An embodiment of the present invention provides another method for preparing a chip packaging structure, which is used to prepare the chip packaging structure provided by any of the above embodiments, including: providing a substrate, the substrate including a first electrode, a second electrode, a third electrode and a fourth electrode; placing a chip; the front side of the chip faces the substrate; setting a heat dissipation structure; the heat dissipation structure includes a first heat dissipation structure; and filling other empty spaces.

[0016] The technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] A first heat dissipation structure is arranged on the back side of the chip, and a first electrode, a second electrode, a third electrode and a fourth electrode are arranged on the front side of the chip. The first electrode, the second electrode, the third electrode and the fourth electrode can all play a role in heat dissipation, so that heat dissipation channels can be formed on the front and back sides of the chip, thereby improving the heat dissipation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a cross-sectional view of a chip packaging structure in an embodiment of the present invention;

[0019] Figure 2 is a flow chart of a method for preparing a chip packaging structure in an embodiment of the present invention;

[0020] Figure 3 is a schematic diagram of a heat dissipation structure in an embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of a chip structure in an embodiment of the present invention;

[0022] Figure 5 Yes Figure 4 A schematic diagram of a chip structure after the chip structure in FIG. 1 is molded;

[0023] Figure 6 is a schematic diagram of the chip structure after completing step S203;

[0024] Figure 7 is a flow chart of another method for preparing a chip packaging structure in an embodiment of the present invention;

[0025] Figure 8 is a schematic structural diagram of a substrate in an embodiment of the present invention;

[0026] Fig. 9 It is a schematic diagram of the structure after the chip is arranged on the substrate;

[0027] Fig.10 This is a schematic diagram of the structure after filling with epoxy resin;

[0028] Fig.11 It is a schematic diagram of the structure after the heat dissipation structure is set;

[0029] Fig.12 is a flow chart of a method for preparing another chip packaging structure in an embodiment of the present invention;

[0030] Fig.13 is a schematic structural diagram of a substrate in an embodiment of the present invention;

[0031] Fig.14 This is a schematic diagram of the structure after the chip is placed;

[0032] Fig.15 It is a schematic diagram of the structure after the heat dissipation structure is set;

[0033] Fig.16 It is a cross-sectional view of another chip packaging structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In an embodiment of the present invention, a first heat dissipation structure is arranged on the back side of the chip, and a first electrode, a second electrode, a third electrode and a fourth electrode are arranged on the front side of the chip. The first electrode, the second electrode, the third electrode and the fourth electrode can all play a role in heat dissipation, so that heat dissipation channels can be formed on both the front and back sides of the chip, thereby improving the heat dissipation efficiency.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Reference Figure 1 , an embodiment of the present invention provides a cross-sectional view of a chip packaging structure, and the chip packaging structure is described in detail below.

[0037] In a specific implementation, a first heat dissipation structure 205 may be disposed on the back of the chip 100 . The first heat dissipation structure 205 adheres to the back of the chip 100 and is in full contact with the back of the chip 100 to dissipate the heat generated by the back of the chip 100 .

[0038] The upper surface of the first electrode 201 may be coupled to the first lead terminal 103 of the chip 100, and the lower surface of the first electrode 201 may be coupled to the upper surface of the third electrode 203. In the embodiment of the present invention, unless otherwise specified, "coupling" between two components indicates that there is direct contact between the two components.

[0039] An upper surface of the second electrode 202 may be coupled to the second lead-out terminal 104 of the chip 100 , and a lower surface of the second electrode 202 may be coupled to an upper surface of the fourth electrode 204 .

[0040] In the embodiment of the present invention, the first lead-out terminal 103 of the chip 100 and the second lead-out terminal 104 of the chip 100 protrude from the front side 101 of the chip 100. The first lead-out terminal 103 and the second lead-out terminal 104 of the chip 100 may be interfaces for supplying power to the chip 100 and communicating with the chip 100, such as pins of the chip 100 or external interfaces of the chip 100.

[0041] The lower surface of the third electrode 203 may be directly connected to the PCB board, and the lower surface of the fourth electrode 204 may also be directly connected to the PCB board.

[0042] In a specific implementation, the chip packaging structure may further include a connection structure 301. The connection structure 301 may connect the first heat dissipation structure 205 and the first electrode 201, and there is no contact between the connection structure 301 and the chip 100.

[0043] In the embodiment of the present invention, one surface of the connection structure 301 may be coupled to the lower surface of the first heat dissipation structure 205 , and the other surface of the connection structure 301 may be coupled to the upper surface of the first electrode 201 .

[0044] In a specific implementation, the first heat dissipation structure 205 is coupled to a portion of the back side of the chip 100. The first end of the first heat dissipation structure 205 extends out of the back side of the chip 100, and the lower surface of the first end of the first heat dissipation structure 205 is connected to the connection structure 301; the second end of the first heat dissipation structure 205 is the other end opposite to the first end in the horizontal direction, and the second end of the first heat dissipation structure 205 is coupled to the back side of the chip 100.

[0045] In the embodiment of the present invention, Figure 1 As shown, in the horizontal direction, the first end of the first heat dissipation structure 205 is the left end of the first heat dissipation structure 205, and the left end of the first heat dissipation structure 205 extends beyond the range of the chip 100; the second end of the first heat dissipation structure 205 is the right end of the first heat dissipation structure 205, and the right end of the first heat dissipation structure 205 is coupled to the back side of the chip 100.

[0046] In the embodiment of the present invention, the material of the first heat dissipation structure 205 may be copper.

[0047] In a specific implementation, the first end of the first electrode 201 may be located within the chip 100, and the second end of the first electrode 201 extends out of the chip 100. The first end of the second electrode 202 may be located within the chip 100, and the second end of the second electrode 202 extends out of the chip 100.

[0048] In the embodiment of the present invention, the first end of the first electrode 201 is located within the range of the chip 100, which means that the projection of the chip 100 on the PCB board covers the projection of the first end of the first electrode 201 on the PCB board. The second end of the first electrode 201 extends out of the range of the chip 100, which means that the projection of the chip 100 on the PCB board does not cover the projection of the second end of the first electrode 201 on the PCB board.

[0049] Correspondingly, the first end of the second electrode 202 is located within the range of the chip 100, which means that the projection of the chip 100 on the PCB board covers the projection of the first end of the second electrode 202 on the PCB board. The second end of the second electrode 202 extends out of the range of the chip 100, which means that the projection of the chip 100 on the PCB board does not cover the projection of the second end of the second electrode 202 on the PCB board.

[0050] Reference Figure 1 The second end of the first electrode 201 is coupled to the connection structure 301 , there is a gap between the first end of the first electrode 201 and the first end of the second electrode 202 , and the second end of the second electrode 202 extends out of the coverage of the chip 100 .

[0051] In a specific implementation, the first end of the third electrode 203 is located within the range of the first electrode 201, and the second end of the third electrode 203 extends beyond the range of the first electrode 201. The first end of the fourth electrode 204 is located within the range of the second electrode 202, and the second end of the fourth electrode 204 extends beyond the range of the second electrode 202.

[0052] In the embodiment of the present invention, the first end of the third electrode 203 is located within the range of the third electrode 203, which means that the projection of the first electrode 201 on the PCB board covers the projection of the first end of the third electrode 203 on the PCB board. The second end of the third electrode 203 extends outside the range of the first electrode 201, which means that the projection of the first electrode 201 on the PCB board does not cover the projection of the second end of the third electrode 203 on the PCB board.

[0053] Correspondingly, the first end of the fourth electrode 204 is located within the range of the second electrode 202, which means that the projection of the second electrode 202 on the PCB board covers the projection of the first end of the fourth electrode 204 on the PCB board. The second end of the fourth electrode 204 extends beyond the range of the second electrode 202, which means that the projection of the second electrode 202 on the PCB board does not cover the projection of the second end of the fourth electrode 204 on the PCB board.

[0054] In a specific implementation, the distance between the first end of the first electrode 201 and the first end of the second electrode 202 is smaller than the distance between the first end of the third electrode and the first end of the fourth electrode 204. By setting as above, a larger creepage distance can be ensured.

[0055] In the embodiment of the present invention, the first electrode 201 and the second electrode 202 can be large-area copper structures as gate source / drain electrodes, respectively, which can achieve the function of electrodes and also play a role in heat dissipation. The third electrode 203 and the fourth electrode 204 can also adopt large-area copper structures to further improve the heat dissipation performance.

[0056] In a specific implementation, the chip packaging structure may further include a second heat dissipation structure 207. The second heat dissipation structure 207 is disposed on the upper surface of the first heat dissipation structure 205, that is, the lower surface of the second heat dissipation structure 207 is in contact with the upper surface of the first heat dissipation structure 205, and the upper surface of the second heat dissipation structure 207 extends to expose the surface of the chip packaging structure.

[0057] In the embodiment of the present invention, the upper surface of the second heat dissipation structure 207 may be connected to an external heat sink.

[0058] By providing the second heat dissipation structure 207 , the heat dissipation area can be further expanded.

[0059] In a specific implementation, the second end of the first heat dissipation structure 205 may also extend beyond the range of the chip 100. Figure 1 The extension section 206 is shown. By providing the extension section 206 of the first heat dissipation structure 205, the heat dissipation area can be further expanded.

[0060] In an embodiment of the present invention, the connecting structure may be a solder ball, a copper column, or other devices that can connect the lower surface of the first heat dissipation structure with the upper surface of the third electrode and have both conductive and thermal conductive functions, which will not be elaborated in the embodiment of the present invention.

[0061] In the embodiment of the present invention, the connection structure can be used as a substrate ground connection. The first heat dissipation structure can be used as a substrate electrode, thereby avoiding electrical interference caused by floating.

[0062] The following is a description of the method for preparing the chip heat dissipation structure provided in the above embodiment of the present invention.

[0063] Reference Figure 2 , a method for preparing a chip packaging structure in an embodiment of the present invention is given, which is used to prepare the chip packaging structure provided in the above embodiment. The following is a detailed description through specific steps.

[0064] Step S201, providing a heat dissipation structure.

[0065] In a specific implementation, the heat dissipation structure may be prefabricated. In an embodiment of the present invention, the heat dissipation structure may include a first heat dissipation structure 205 .

[0066] In the embodiment of the present invention, when prefabricating the heat dissipation structure, it is also possible to determine whether to prefabricate the second heat dissipation structure 207 and whether to extend the first heat dissipation structure 205 to obtain the extended section 206 according to specific application scenarios and application requirements.

[0067] Reference Figure 3 , a schematic diagram of a heat dissipation structure in an embodiment of the present invention is given. Figure 3In the embodiment, the heat dissipation structure provided includes a first heat dissipation structure 205 and a second heat dissipation structure 207 , and the first heat dissipation structure 205 includes an extension section 206 .

[0068] In specific applications, a die last method can be used to prepare a heat dissipation structure.

[0069] Step S202, placing the chip and performing molding.

[0070] In a specific implementation, the back side of the chip 100 is arranged toward the first heat dissipation structure 205 .

[0071] In a specific implementation, the connection structure 301 may be placed or generated before the molding.

[0072] If the connection structure 301 is a copper pillar, the copper pillar may be formed by a deposition method. If the connection structure 301 is a solder ball, the solder ball may be placed by a ball placement method.

[0073] It should be noted that, in the embodiment of the present invention, the connection structure 301 may be generated or placed when the heat dissipation structure is provided, or may be generated or placed after the chip 100 is placed.

[0074] After the chip 100 is placed and the connection structure 301 is placed or generated, the obtained structure can be molded, and the filling height of the molding material is flush with the lower surface of the first lead-out terminal 103 and the second lead-out terminal 104 of the chip 100 .

[0075] In the embodiment of the present invention, the molding material may be epoxy resin 401 .

[0076] Reference Figure 4 , a schematic diagram of the structure of a chip 100 in an embodiment of the present invention is given. Figure 4 In the process, the connection structure 301 and the chip 100 are placed.

[0077] right Figure 4 The structure in the mold is molded to obtain Figure 5 , Figure 5 Yes Figure 4 Schematic diagram of the chip structure after the chip structure in FIG. 1 is molded. Figure 5 In the embodiment, the remaining space except for the placed components is filled with epoxy resin 401.

[0078] Step S203 , respectively setting a first electrode, a second electrode, a third electrode and a fourth electrode.

[0079] In a specific implementation, the first electrode 201, the second electrode 202, the third electrode 203 and the fourth electrode 204 can be grown separately. After completing step S203, the obtained chip structure is as follows: Figure 6shown.

[0080] Step S204, filling other empty spaces.

[0081] In the embodiment of the present invention, Figure 6 On the basis of, epoxy resin 402 is used to fill other empty spaces to obtain Figure 1 The chip packaging structure shown.

[0082] Reference Figure 7 , a flow chart of another chip packaging structure preparation method in an embodiment of the present invention is given. The following is a detailed description through specific steps.

[0083] Step S701, providing a substrate and performing molding.

[0084] In the specific implementation, refer to Figure 8 , a schematic diagram of the structure of a substrate in an embodiment of the present invention is given, the substrate may include a first electrode 201, a second electrode 202, a third electrode 203 and a fourth electrode 204, and the space between the first electrode 201, the second electrode 202, the third electrode 203 and the fourth electrode 204 is filled with epoxy resin 402. The height of the epoxy resin 402 is flush with the upper surface of the first electrode 201 and the second electrode 202.

[0085] A connection structure 301 is provided on the substrate.

[0086] Step S702, placing the chip.

[0087] In a specific implementation, after obtaining a substrate, a chip 100 may be arranged on the substrate. The obtained chip structure is as follows: Fig. 9 A schematic diagram of the structure after a chip is provided on the substrate is given.

[0088] It should be noted that, in the embodiment of the present invention, the connection structure 301 may be generated or placed when the substrate is provided, or may be generated or placed after the chip 100 is placed, or may be generated or placed at the same time as the chip 100 is placed.

[0089] After the chip 100 is placed, the remaining space can be filled with epoxy resin 401, and the resulting chip 100 structure is as follows: Fig.10 shown.

[0090] Step S703, setting a heat dissipation structure.

[0091] exist Fig.10 Based on the obtained chip 100 structure, a heat dissipation structure is set to obtain Fig.11 The chip 100 structure is shown.

[0092] In the embodiment of the present invention, the heat dissipation structure may include a first heat dissipation structure 205 and a second heat dissipation structure 207 , and the first heat dissipation structure 205 includes an extension section 206 .

[0093] Step S704, filling other empty spaces.

[0094] exist Fig.11 Based on the obtained chip 100 structure, epoxy resin 401 is used to fill other empty spaces to obtain Figure 1 The chip packaging structure shown.

[0095] Reference Fig.12 , a flow chart of another chip packaging structure preparation method in an embodiment of the present invention is given. The following is a detailed description through specific steps.

[0096] Step S121, providing a substrate.

[0097] In a specific implementation, the substrate may include a first electrode 201, a second electrode 202, a third electrode 203, and a fourth electrode 204, and the spaces between the first electrode 201, the second electrode 202, the third electrode 203, and the fourth electrode 204 are filled with epoxy resin 402. The height of the epoxy resin 402 is flush with the upper surfaces of the first electrode 201 and the second electrode 202. Fig.13 , a schematic structural diagram of a substrate in an embodiment of the present invention is given.

[0098] Step S122, placing the chip.

[0099] Place the chip 100 on the substrate to obtain Fig.14 The chip 100 structure is shown.

[0100] Step S123, setting a heat dissipation structure.

[0101] In the embodiment of the present invention, the heat dissipation structure may include a first heat dissipation structure 205 and a second heat dissipation structure 207 , and the first heat dissipation structure 205 includes an extension section 206 .

[0102] What is different from the above embodiment is that Fig.15 The first heat dissipation structure 205 provided in the embodiment also has the function of the connection structure 301 and is connected to the first electrode 201 .

[0103] Step S124, filling other empty spaces.

[0104] Adopt epoxy resin 401 Fig.15 The remaining spaces of the chip 100 structure shown in FIG. Fig.16 The chip packaging structure shown.

[0105] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0106] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A chip packaging structure, characterized in that: include: A first heat dissipation structure, a first electrode, a second electrode, a third electrode, a fourth electrode and a connection structure, wherein: The first heat dissipation structure is arranged on the back side of the chip; The first electrode has an upper surface coupled to the first lead-out terminal of the chip, and a lower surface coupled to the upper surface of the third electrode; The second electrode has an upper surface coupled to the second lead-out terminal of the chip, and a lower surface coupled to the upper surface of the fourth electrode; The lower surfaces of the third electrode and the fourth electrode are both connected to the PCB board; The connecting structure connects the first heat dissipation structure and the first electrode and has no contact with the chip.

2. The chip packaging structure according to claim 1, characterized in that: The first heat dissipation structure has a first end extending out of the back side of the chip, and a second end arranged on the back side of the chip; the first end of the first heat dissipation structure is an end connected to the connecting structure, and the second end of the first heat dissipation structure is the other end of the first heat dissipation structure in the horizontal direction.

3. The chip packaging structure according to claim 2, characterized in that: The second end of the first heat dissipation structure extends out of the back side of the chip.

4. The chip packaging structure according to claim 1, characterized in that: The first end of the first electrode is located within the chip, and the second end of the first electrode extends out of the chip; the first end of the second electrode is located within the chip, and the second end of the second electrode extends out of the chip.

5. The chip packaging structure according to claim 4, characterized in that: The second end of the third electrode extends beyond the range of the first electrode, and the first end of the third electrode is located within the range of the first electrode; the second end of the fourth electrode extends beyond the range of the second electrode, and the first end of the fourth electrode is located within the range of the second electrode.

6. The chip packaging structure according to claim 5, characterized in that: A distance between a first end of the third electrode and a first end of the fourth electrode is greater than a distance between a first end of the first electrode and a first end of the second electrode.

7. The chip packaging structure according to claim 1, characterized in that: Also includes: A second heat dissipation structure; the lower surface of the second heat dissipation structure contacts the upper surface of the first heat dissipation structure, and the upper surface of the second heat dissipation structure extends to expose the surface of the chip packaging structure.

8. The chip packaging structure according to claim 1, characterized in that: The connection structure includes any one of the following: a solder ball, a copper column.

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