Manufacturing Method of Split-Gate Flash Memory

Abstract

The present invention provides a method for manufacturing a split-gate flash memory. After forming the floating-gate tip, by performing an oxidation treatment on the floating-gate layer, the floating-gate tip can be made smooth, reducing electron leakage in the floating gate, lowering the leakage current, helping to improve the data retention ability, and thus improving the erasure performance of the memory. Further, by performing an oxidation treatment on the floating-gate layer, the height of the floating-gate tip can be reduced, and the smoothness of the surface of the floating-gate layer can be improved, reducing the capacitance between the floating-gate layer and the word line, so that the capacitance coupling ratio is also correspondingly reduced, and further improving the programming performance of the memory.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a manufacturing method of a split-gate flash memory. Background Art

[0002] Flash memory, abbreviated as flash, is divided into two types: stack gate devices and split gate devices. Among them, in split gate devices, a word line serving as an erase gate is formed on one side of the floating gate, and the word line serves as a control gate. In terms of erase performance, split gate devices effectively avoid the over-erase effect of stack gate devices, and the circuit design is relatively simple. Therefore, it is widely used in various electronic products such as smart cards, SIM cards, microcontrollers, mobile phones, etc. In split-gate flash memories, the height and sharpness of the tip of the floating gate affect the voltage coupled during programming and erasing of the floating gate, thereby affecting the performance of the flash during programming and erasing. Moreover, the sharpness of the tip of the floating gate has a strong correlation with the erase performance of the flash. Therefore, in the manufacturing method of split-gate flash memories, it is necessary to optimize the formation process of the tip of the floating gate to improve the erase and programming performance of the memory. Summary of the Invention

[0003] The purpose of the present invention is to provide a manufacturing method of a split-gate flash memory to improve the erase performance and programming performance of the memory.

[0004] To achieve the above purpose, the present invention provides a manufacturing method of a split-gate flash memory, including:

[0005] Providing a semiconductor substrate;

[0006] Successively forming a floating gate layer and a word line on the semiconductor substrate, and the word line penetrates the floating gate layer;

[0007] Etching the floating gate layer to form a floating gate tip, and the floating gate tip is formed at the top corner of the floating gate layer away from the word line;

[0008] Performing an oxidation treatment on the floating gate layer to smooth the floating gate tip.

[0009] Optionally, in the manufacturing method of the split-gate flash memory, the forming method of the floating gate layer includes:

[0010] Successively forming a floating gate material layer and a hard mask layer on the semiconductor substrate, and the hard mask layer has a first opening exposing a part of the floating gate material layer;

[0011] Etching the exposed part of the floating gate material layer with the hard mask layer as a mask to make the top surface of the floating gate material layer arc-shaped;

[0012] Form a sidewall layer that covers the sidewalls of the first opening; and,

[0013] Using the sidewall layer and the hard mask layer as masks, etch the exposed floating gate material layer to form the floating gate layer.

[0014] Optionally, in the method for manufacturing the split-gate flash memory, the method for forming the floating gate tip includes:

[0015] Remove the hard mask layer to expose the floating gate layer;

[0016] Using the sidewall layer as a mask, etch the floating gate layer and retain the floating gate layer below the sidewall layer to form the floating gate tip.

[0017] Optionally, in the method for manufacturing the split-gate flash memory, the material of the sidewall layer is silicon oxide and / or silicon oxynitride.

[0018] Optionally, in the method for manufacturing the split-gate flash memory, the floating gate layer has a second opening communicating with the first opening.

[0019] Optionally, in the method for manufacturing the split-gate flash memory, after forming the floating gate layer and before forming the word line, it further includes: forming a tunneling oxide layer that covers the sidewalls and the bottom wall of the second opening and extends to cover the sidewall layer, and the tunneling oxide layer has a third opening.

[0020] Optionally, in the method for manufacturing the split-gate flash memory, the word line fills the third opening, and the top surface of the word line is flush with the top surface of the sidewall layer, or the top surface of the word line is lower than the top surface of the sidewall layer.

[0021] Optionally, in the method for manufacturing the split-gate flash memory, the oxidation treatment includes a thermal oxidation process and / or an in-situ steam generation process.

[0022] Optionally, in the method for manufacturing the split-gate flash memory, the process gas for the thermal oxidation process includes oxygen, and the process temperature is 500°C to 1200°C; the gas for the in-situ steam generation process includes hydrogen and oxygen, and the process temperature is 800°C to 1100°C, and the gas for the in-situ steam generation process includes hydrogen and oxygen.

[0023] Optionally, in the method for manufacturing the split-gate flash memory, a floating gate oxide layer is further formed between the floating gate layer and the semiconductor substrate.

[0024] In the manufacturing method of the split-gate flash memory provided by the present invention, after forming the floating gate tip, by oxidizing the floating gate layer, the floating gate tip can be made smooth, reducing electron leakage in the floating gate, reducing leakage current, helping to improve data retention ability, and thus improving the erasure performance of the memory. Further, by oxidizing the floating gate layer, the height of the floating gate tip can be reduced, and the smoothness of the surface of the floating gate layer can be improved, reducing the capacitance between the floating gate layer and the word line, and thus reducing the capacitance coupling ratio, and further improving the programming performance of the memory. Description of the Drawings

[0025] Figure 1 is a schematic flow chart of the manufacturing method of the split-gate flash memory according to an embodiment of the present invention;

[0026] Figures 2 to 10 is a schematic cross-sectional view of the structure formed in the manufacturing method of the split-gate flash memory according to an embodiment of the present invention;

[0027] Among them, the reference numerals are described as follows:

[0028] 100 - semiconductor substrate; 110 - floating gate oxide layer; 120 - floating gate material layer; 120a - floating gate layer; 121 - floating gate tip; 130 - hard mask layer; 130a - first opening; 130b - second opening; 140 - sidewall layer; 150 - tunneling oxide layer; 160 - third opening; 170 - word line. Detailed Embodiment

[0029] The following further describes in detail the manufacturing method of the split-gate flash memory proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0030] Figure 1 is a schematic flow chart of the manufacturing method of the split-gate flash memory provided by an embodiment of the present invention.

[0031] As Figure 1 described, the manufacturing method of the split-gate flash memory of this embodiment includes:

[0032] Step S1: Provide a semiconductor substrate;

[0033] Step S2: Sequentially form a floating gate layer and a word line on the semiconductor substrate, and the word line penetrates the floating gate layer;

[0034] Step S3: Etch the floating gate layer to form a floating gate tip, and the floating gate tip is formed at the vertex of the floating gate layer away from the word line;

[0035] Step S4: Perform an oxidation process on the floating gate layer to make the tip of the floating gate smooth.

[0036] Figures 2 to 10 Schematic cross-sectional view of the structure formed in the manufacturing method of the split-gate flash memory according to the embodiment of the present invention. The following combines Figures 2 to 10 To further describe in detail the manufacturing method of the split-gate flash memory provided in this embodiment.

[0037] Refer to Figure 2 , perform step S1 to provide a semiconductor substrate 100. The material of the semiconductor substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, etc., or it can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or it can also be other materials, such as gallium arsenide and other group III-V compounds. In this embodiment, the semiconductor substrate 100 is a silicon substrate.

[0038] A floating gate oxide layer 110 can be formed on the surface of the semiconductor substrate 100. The floating gate oxide layer 110 can isolate the subsequently formed floating gate layer from the semiconductor substrate 100. The method of forming the floating gate oxide layer 110 can adopt the conventional thermal furnace tube process or rapid thermal oxidation process in the prior art. In this embodiment, the material of the floating gate oxide layer 110 can be silicon oxide or nitrogen-doped silicon oxide. The thickness can be, for example, 50 Å to 100 Å.

[0039] Continue to refer to Figure 2 shown, and in combination with Figures 3 to 8 shown, perform step S2 to sequentially form a floating gate layer 120a and a word line 170 on the semiconductor substrate 100, and the word line 170 penetrates through the floating gate layer 120a. Specifically, the method of forming the floating gate layer 120a includes: First, continue to refer to Figure 2 , sequentially form a floating gate material layer 120 and a hard mask layer 130 on the semiconductor substrate 100, and a first opening 130a exposing a part of the floating gate material layer 120 is formed in the hard mask layer 130. The material of the floating gate material layer 120 can be polysilicon, and ions can be doped in the floating gate material layer 120, and it can be formed by the conventional deposition process in the art. The thickness of the floating gate material layer 120 can be, for example, 300 Å to 800 Å. The material of the hard mask layer 130 can be a nitride layer, which can be used as a protective layer for subsequent etching processes. The thickness of the hard mask layer 130 can be, for example, 100 Å to 600 Å.

[0040] It should be noted here that the materials of each layer, the thickness of each layer, and the formation method of each layer mentioned above and below are only an example of the embodiments of the present invention. Different materials, different thicknesses, and different formation methods can be adopted in different situations, and these should not constitute a limitation to the present invention.

[0041] As Figure 4 shown, after forming the floating gate material layer 120 and the hard mask layer 130, a part of the thickness of the floating gate material layer 120 exposed is etched using the hard mask layer 130 as a mask, so that the top surface of the exposed floating gate material layer 120 is arc-shaped (or concave). In this embodiment, an isotropic etching process is used to etch the floating gate material layer 120, and the gas used in the isotropic etching process includes hydrogen. After etching, the top surface of the floating gate material layer 120 is arc-shaped, that is, the top surface of the floating gate material layer 120 gradually rises from the middle to the edge, thus preparing for the subsequent formation of the floating gate tip of the floating gate layer, and further making the angle of the subsequently formed floating gate tip an acute angle.

[0042] Next, as Figure 5 shown, a sidewall layer 140 is formed, and the sidewall layer 140 covers the sidewalls of the first opening 130a. The sidewall layer 140 can be used as a blocking layer to etch the floating gate layer 120a material layer to form the floating gate layer 120a. Specifically, the material of the sidewall layer 140 can be silicon oxide and / or silicon oxynitride.

[0043] Next, as Figure 6 shown, using the sidewall layer 140 and the hard mask layer 130 as masks, the exposed floating gate material layer 120 is etched to form the floating gate layer 120a, and the floating gate layer 120a has a second opening 130b. Among them, an anisotropic dry etching process can be used to etch the floating gate material layer 120 to form the floating gate layer 120a.

[0044] As Figure 7 shown, after forming the floating gate layer 120a, a tunneling oxide layer 150 is formed. The tunneling oxide layer 150 covers the sidewalls and the bottom wall of the second opening 130b and extends to cover the sidewall layer 140. The tunneling oxide layer 150 is used to isolate the subsequently formed word line 170 and the floating gate layer 120a. The material of the tunneling oxide layer 150 can be silicon oxide, and it can be formed by a thermal furnace tube process or a rapid thermal oxidation process. In addition, the tunneling oxide layer 150 has a third opening 160, and the third opening 160 can define the position of the word line 170.

[0045] Next, as Figure 8As shown, a word line 170 is formed, and the word line 170 fills the third opening 160. Among them, the top surface of the word line 170 can be flush with the top surface of the hard mask layer 130. In other embodiments, the top surface of the word line 170 can be lower than the top surface of the hard mask layer 130.

[0046] Specifically, a relatively thick word line material layer (not shown) can be first formed in the third opening 160 and on the hard mask. The material of the word line material layer can be polysilicon, and the word line material layer can be formed by chemical vapor deposition process. Then, the word line material layer is planarized, for example, by chemical mechanical polishing (CMP) process, to form the word line 170.

[0047] As Figures 9 to 10 shown, step S3 is performed to etch the floating gate layer 120a to form a floating gate tip 121, and the floating gate tip 121 is formed at the top corner of the floating gate layer 120a away from the word line 170. Specifically, the method for forming the floating gate tip 121 includes: First, as Figure 9 shown, the hard mask layer 130 is removed to expose the floating gate layer 120a (exposing the floating gate layer 120a not covered by the sidewall layer 140). The remaining hard mask layer 130 can be removed by dry or wet etching process. The etching gas for dry etching can be selected from one or more of HBr, Cl 2 、SF 6 、O 2 、N 2 、NF 3 、Ar, He and CF 4 in, and phosphoric acid solution can be selected for wet etching to improve the hard mask etching selectivity. Then, the floating gate layer 120a is etched by dry etching process, and the floating gate layer 120a under the sidewall layer 140 is retained to form a floating gate tip 121 at the top corner of the floating gate layer 120a. In addition, when etching the floating gate layer 120a, the floating gate oxide layer 110 under the floating gate layer 120a can also be etched to expose the semiconductor substrate 100.

[0048] Among them, a part of the top surface and the side surface away from the word line 170 of the floating gate layer 120a form the floating gate tip 121. Since the top surface of the floating gate layer 120a is arc-shaped, it can ensure the height and acute angle shape of the floating gate tip 121 at the top corner of the etched floating gate layer 120a, so that the angle of the floating gate tip 121 is an acute angle, thereby meeting the requirements of the erase and programming functions. When the memory is erased, the floating gate tip 121 reduces the channel voltage of the tunneling effect through the tip discharge principle, enabling electrons to be pulled away from the floating gate layer 120a and flow into the word line 170, thus realizing the erase operation. Since the top surface of the floating gate layer 120a is arc-shaped, the angle of the floating gate tip 121 is an acute angle, thereby reducing the electron leakage in the floating gate, reducing the leakage current, helping to improve the data retention ability, and thus improving the erase performance of the memory.

[0049] Next, step S4 is executed to oxidize the floating gate layer 120a to smooth the floating gate tip 121. Here, the smoothing means that the floating gate tip after oxidation treatment is smoother than the floating gate tip before oxidation treatment, thereby reducing the leakage current. In other embodiments, before oxidizing the floating gate layer 120a, the sidewall layer 140 can be thinned by a dry etching process to completely expose the floating gate tip 121, which is beneficial for the floating gate tip to be quickly oxidized during the oxidation treatment.

[0050] The oxidation treatment includes a rapid thermal oxidation (RTO) process and / or an in-situ steam generation (ISSG) process. Among them, the rapid thermal oxidation process uses an oxidation furnace or a rapid thermal annealing chamber to thermally oxidize the floating gate layer 120a when the process gas is oxygen and the process temperature is 500°C to 1200°C. The process temperature can be, for example, 600°C, 700°C, 800°C, or 950°C. During the thermal oxidation process, oxygen atoms invade from the surface of the floating gate layer 120a and chemically react with the polysilicon in the floating gate layer 120a, so that a part of the thickness of the floating gate layer 120a is oxidized. After the floating gate layer 120a is oxidized, its surface becomes smoother, improving the smoothness of the surface of the floating gate layer 120a, reducing the capacitance between the floating gate layer 120a and the word line 170, and thus reducing the capacitance coupling rate, and further improving the programming performance of the memory. Further, after the oxygen atoms in the oxidation process chemically react with the polysilicon in the floating gate layer 120a, a thin oxide layer will be formed on the surface of the floating gate layer 120a. At the same time, the thickness of the tunneling oxide layer 150 can also be increased. In this way, the electron leakage in the floating gate layer 120a can be blocked, and the leakage current can be reduced.

[0051] In-situ steam generation process (ISSG) is to introduce hydrogen and oxygen into a rapid thermal annealing chamber, in-situ synthesize water vapor on the surface of the floating gate layer 120a, and react with the polysilicon in the floating gate layer 120a to oxidize a part of the thickness of the floating gate layer 120a. Among them, the gases of the in-situ steam generation process include hydrogen and oxygen, and the process temperature is 800°C to 1100°C. After the oxidation treatment, the floating gate tip 121 is smoothed, reducing electron leakage in the floating gate, reducing leakage current, helping to improve data retention ability, and thus improving the erasure performance of the memory.

[0052] In this embodiment, the oxidation treatment time is 5s to 10s, for example, it can be 5s, 6s or 10s. If the oxidation treatment time is too long, the floating gate layer 120a will be oxidized to a greater extent, and even the floating gate layer 120a will be completely oxidized, thus affecting the performance of the memory.

[0053] In summary, in the manufacturing method of the split-gate flash memory provided by the present invention, after forming the floating gate tip, by oxidizing the floating gate layer, the floating gate tip can be smoothed, reducing electron leakage in the floating gate, reducing leakage current, helping to improve data retention ability, and thus improving the erasure performance of the memory. Further, by oxidizing the floating gate layer, the height of the floating gate tip can be reduced, and the smoothness of the surface of the floating gate layer can be improved, reducing the capacitance between the floating gate layer and the word line, and thus reducing the capacitance coupling rate, and further improving the programming performance of the memory.

[0054] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the protection scope of the claims.

Claims

1. A manufacturing method of a split-gate flash memory, characterized in that, comprising: providing a semiconductor substrate; successively forming a floating gate material layer and a hard mask layer on the semiconductor substrate, wherein the hard mask layer has a first opening exposing a part of the floating gate material layer; etching the exposed part of the floating gate material layer with the hard mask layer as a mask to make the top surface of the floating gate material layer arc-shaped; forming a sidewall layer covering the sidewalls of the first opening etching the exposed floating gate material layer with the sidewall layer and the hard mask layer as masks to form the floating gate layer; forming word lines on the semiconductor substrate, the word lines penetrating the floating gate layer; etching the floating gate layer to form floating gate tips, the floating gate tips being formed at the top corners of the floating gate layer away from the word lines; thinning the sidewall layer to completely expose the floating gate tips; performing an oxidation treatment on the floating gate layer to make the floating gate tips smoother, wherein the floating gate tips after the oxidation treatment are smoother than those before the oxidation treatment.

2. The manufacturing method of the split-gate flash memory according to claim 1, characterized in that, the method for forming the floating gate tips includes: removing the hard mask layer to expose the floating gate layer; etching the floating gate layer with the sidewall layer as a mask to form the floating gate tips.

3. The manufacturing method of the split-gate flash memory according to claim 1, characterized in that, the material of the sidewall layer is silicon oxide and / or silicon oxynitride.

4. The manufacturing method of the split-gate flash memory according to claim 1, characterized in that, the floating gate layer has a second opening communicating with the first opening.

5. The manufacturing method of the split-gate flash memory according to claim 4, characterized in that, after forming the floating gate layer and before forming the word lines, further comprising: forming a tunneling oxide layer covering the sidewalls and the bottom wall of the second opening and extending to cover the sidewall layer, and the tunneling oxide layer has a third opening.

6. The manufacturing method of the split-gate flash memory according to claim 5, characterized in that, the word lines fill the third opening, and the top surface of the word lines is flush with the top surface of the sidewall layer, or the top surface of the word lines is lower than the top surface of the sidewall layer.

7. The manufacturing method of the split-gate flash memory according to claim 1, characterized in that, the oxidation treatment includes a thermal oxidation process and / or an in-situ steam generation process.

8. The manufacturing method of the split-gate flash memory according to claim 7, characterized in that, the process gas of the thermal oxidation process includes oxygen, and the process temperature is 500°C to 1200°C; the gas of the in-situ steam generation process includes hydrogen and oxygen, and the process temperature is 800°C to 1100°C.

9. The manufacturing method of the split-gate flash memory according to claim 1, characterized in that, a floating gate oxide layer is further formed between the floating gate layer and the semiconductor substrate.

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