Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. A semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of stacked insulating layers alternately stacked, a trench structure penetrating the stacked structure, a tunnel insulating layer surrounding the trench structure, a cell storage pattern surrounding the tunnel insulating layer, and a dummy storage pattern surrounding the tunnel insulating layer, the dummy storage pattern being spaced apart from the cell storage pattern. The conductive pattern includes a selected conductive pattern in contact with the tunnel insulating layer.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods of manufacturing semiconductor devices, and more specifically, to a three-dimensional semiconductor device and a method of manufacturing a three-dimensional semiconductor device. Background Technology

[0002] Semiconductor devices include memory cells capable of storing data. Three-dimensional semiconductor devices include memory cells arranged in three dimensions, thereby reducing the area occupied by the memory cells per unit area of ​​the substrate.

[0003] To improve the integration density of three-dimensional semiconductor devices, the number of memory cell stacks can be increased. However, the operational reliability of three-dimensional semiconductor devices can deteriorate as the number of memory cell stacks increases. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device may be provided, the semiconductor device comprising: a stacked structure including a plurality of conductive patterns and a plurality of stacked insulating layers alternately stacked; a channel structure penetrating the stacked structure; a tunnel insulating layer surrounding the channel structure; a cell memory pattern surrounding the tunnel insulating layer; and a dummy memory pattern surrounding the tunnel insulating layer, the dummy memory pattern being spaced apart from the cell memory pattern, wherein the conductive patterns include selective conductive patterns in contact with the tunnel insulating layer.

[0005] According to another aspect of this disclosure, a semiconductor device may be provided, comprising: a stacked structure including a plurality of stacked insulating layers and a plurality of conductive patterns alternately stacked; a plurality of unit plugs penetrating the stacked structure; and an isolation structure between the plurality of unit plugs, wherein the conductive patterns include selective conductive patterns in contact with the isolation structure, wherein a recess is defined when a sidewall of the isolation structure is recessed, and wherein the selective conductive pattern includes an insertion portion inserted into the recess.

[0006] According to another aspect of this disclosure, a semiconductor device may be provided, comprising: a stacked structure including a plurality of stacked insulating layers and a plurality of conductive patterns alternately stacked; a cell plug penetrating the stacked structure; and an insulating structure covering the stacked structure and the cell plug, wherein the cell plug includes a protrusion extending to the outside of the stacked structure, wherein the insulating structure includes a first portion covering the protrusion and a second portion covering the top surface of the stacked structure, and wherein the width of the first portion is greatest at a first height between a central portion of the first portion and the uppermost portion of the first portion.

[0007] According to another aspect of this disclosure, a method for manufacturing a semiconductor device may be provided, the method comprising the steps of: forming a stacked structure including overlapping cell sacrificial layers, selective sacrificial layers and stacked insulating layers; forming a first opening exposing the selective sacrificial layers; removing the selective sacrificial layers through the first opening; forming a first portion of a filling sacrificial layer in a blank space formed by removing the selective sacrificial layers; forming a second opening exposing the first portion of the filling sacrificial layer and the cell sacrificial layers; and removing the first portion of the filling sacrificial layer and the cell sacrificial layers.

[0008] According to another aspect of this disclosure, a method for manufacturing a semiconductor device may be provided, the method comprising the steps of: forming a stacked structure including overlapping cell sacrificial layers, selective sacrificial layers, and stacked insulating layers; forming a plurality of cell plugs penetrating the stacked structure, the cell plugs protruding to the outside of the stacked structure; forming an insulating structure including a plurality of first portions covering the cell plugs and a second portion covering a top surface of the stacked structure; forming a mask layer including a first opening exposing cavities between the plurality of first portions; and etching the stacked structure through the first opening and the cavities. Attached Figure Description

[0009] Examples of embodiments will now be described below with reference to the accompanying drawings; however, they may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey to those skilled in the art the scope of the examples of embodiments.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Similar reference numerals always indicate similar elements.

[0011] Figure 1A This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 1B yes Figure 1A An enlarged view of region A shown.

[0013] Figure 1C yes Figure 1A An enlarged view of region B shown.

[0014] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10, Figure 11A , Figure 12A , Figure 13 and Figure 14 It is shown Figures 1A to 1C A cross-sectional view of the manufacturing method of the semiconductor device shown.

[0015] Figure 11B yes Figure 11A An enlarged view of region C shown.

[0016] Figure 12B yes Figure 12A An enlarged view of region D shown.

[0017] Figure 15 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0018] Figure 16 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0019] The specific structural or functional descriptions disclosed herein are merely illustrative in order to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0020] The embodiments provide a semiconductor device and a method for manufacturing a semiconductor device that can improve operational reliability.

[0021] Figure 1A This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B yes Figure 1A An enlarged view of region A shown. Figure 1C yes Figure 1A An enlarged view of region B shown.

[0022] Reference Figure 1A The semiconductor device may include a stacked structure STA. In an embodiment, the stacked structure STA may be disposed on a source structure (not shown). The source structure may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. In an example, the first direction D1 and the second direction D2 may be orthogonal to each other. The source structure may serve as a source line of the semiconductor device. The source structure may include a conductive material. In an example, the source structure may include polysilicon.

[0023] In one embodiment, the source structure may be disposed on a substrate that physically supports the source structure. The substrate may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. In an example, the substrate may be a semiconductor substrate.

[0024] In one embodiment, a peripheral circuit structure (not shown) including transistors and lines may be disposed between the source structure and the substrate.

[0025] The stacked structure STA may include conductive patterns CP and stacked insulating layers IL alternately stacked on a third direction D3. The third direction D3 may intersect with the first direction D1 and the second direction D2. In the example, the third direction D3 may be orthogonal to the first direction D1 and the second direction D2.

[0026] The stacked insulating layer IL may include an insulating material. Each conductive pattern CP may include a conductive layer. In an example, the conductive layer may include at least one of a doped silicon layer, a metal silicide layer, tungsten, nickel, and cobalt. In an embodiment, each conductive pattern CP may also include a barrier layer covering the surface of the conductive layer. The barrier layer may be formed between the conductive layer and the stacked insulating layer IL. In an example, the barrier layer may include titanium, titanium nitride, tantalum, or tantalum nitride.

[0027] The conductive pattern CP may include a selection conductive pattern SCP used as a selection line and a unit conductive pattern CCP used as a word line. The conductive pattern CP located on the upper part of the stacked structure STA can be defined as a conductive pattern SCP, and the conductive pattern CP located below the selection conductive pattern SCP can be defined as a unit conductive pattern CCP.

[0028] Cell plugs (PLs) with a through-layer structure can be provided. Each cell plug (PL) may include a channel structure (CS) and a memory layer (ML).

[0029] The channel structure CS can penetrate the stacked structure STA. The channel structure can penetrate the stacked insulating layer IL and conductive pattern CP of the stacked structure STA. The channel structure CS can extend in the third direction D3.

[0030] Each channel structure CS may include a fill layer FI and a channel layer CL surrounding the fill layer FI. The fill layer FI and the channel layer CL may extend in the third direction D3. The channel layer CL may cover the top surface of the fill layer FI. The upper portion of the channel structure CS may protrude over the stacked structure STA. The upper portion of the channel layer CL may protrude over the stacked structure STA. The fill layer FI may include an insulating material. In an example, the fill layer may include an oxide. The channel layer CL may include a semiconductor material. In an example, the channel layer CL may include polysilicon. The channel layer CL may be electrically connected to the source structure.

[0031] The memory layer ML may surround the channel structure CS. The memory layer ML may penetrate the stacked structure STA. The memory layer ML may penetrate the stacked insulating layer IL and conductive pattern CP of the stacked structure STA. The memory layer ML may extend in the third direction D3. The upper part of the memory layer ML may protrude above the stacked structure STA. The memory layer ML may include a tunnel insulating layer TL surrounding the channel layer CL, a cell memory pattern CDP and a dummy memory pattern DDP surrounding the tunnel insulating layer TL, a cell blocking pattern CBP surrounding the cell memory pattern CDP, and dummy blocking patterns DBP surrounding the dummy memory pattern DDP.

[0032] Cell storage pattern CDP and dummy storage pattern DDP can be spaced apart from each other on third-party D3.

[0033] The tunnel insulating layer TL may include a charge-tunable material. In an example, the tunnel insulating layer TL may include an oxide. In an embodiment, the cell storage pattern CDP and the dummy storage pattern DDP may include materials capable of trapping charge. In an embodiment, the cell storage pattern CDP and the dummy storage pattern DDP may include nitrides. In another embodiment, depending on the data storage method, the cell storage pattern CDP and the dummy storage pattern DDP may include various materials. In an example, the cell storage pattern CDP and the dummy storage pattern DDP may include silicon, phase change materials, or nanodots. The cell blocking pattern CBP and the dummy blocking pattern DBP may include materials capable of blocking the movement of charge. In an embodiment, the cell blocking pattern CBP and the dummy blocking pattern DBP may include oxides.

[0034] An isolation structure DS may be disposed within a stacked structure STA. An isolation structure DS may be disposed between cell plugs PL. An isolation structure DS may be disposed in the upper part of the stacked structure STA. An isolation structure DS may extend in a second direction D2 and a third direction D3. An isolation structure DS may isolate selected conductive patterns SCP from each other in a first direction D1. An isolation structure DS may isolate stacked insulating layers IL disposed in the upper part of the stacked structure STA from each other in the first direction D1. An isolation structure DS may include an insulating material. In an example, an isolation structure DS may include an oxide. An isolation structure DS may be in contact with a selected conductive pattern SCP. An isolation structure DS may be spaced apart from a cell conductive pattern CCP.

[0035] An insulating structure IS can be provided to cover the laminated structure STA and the unit plug PL. The insulating structure IS may include an insulating material. In an example, the insulating structure IS may include an oxide or amorphous carbon layer.

[0036] The insulating structure IS may include a first part IS1 and a second part IS2. The first part IS1 of the insulating structure IS may be a portion covering the unit plug PL. The second part IS2 of the insulating structure IS may be a portion covering the top surface of the laminated structure STA.

[0037] The second part IS2 of the insulating structure IS can connect the first parts IS1 of the insulating structure IS to each other. The second part IS2 of the insulating structure IS can cover the top surface of the uppermost layer IL of the laminated structure STA.

[0038] A first cavity CA1 may be defined by the sidewalls of the first portion IS1 of the insulating structure IS and the top surface of the second portion IS2 of the insulating structure IS. The first cavity CA1 may be the space between the first portions IS1 of the insulating structure IS.

[0039] A first insulating layer 110 may be provided to cover the insulating structure IS and the isolation structure DS. The first insulating layer 110 may fill the first cavity CA1. The first insulating layer 110 may cover the top surface of the isolation structure DS. The first insulating layer 110 may include an insulating material. In an example, the first insulating layer 110 may include an oxide. The first insulating layer 110 may be formed continuously with the isolation structure DS without any boundary. The first insulating layer 110 may be integrally formed with the isolation structure DS.

[0040] A slit structure SLS can be provided, which penetrates the first insulating layer 110, the insulating structure IS, and the laminated structure STA. The slit structure SLS can extend in the second direction D2 and the third direction D3. The laminated insulating layer IL, the selected conductive pattern SCP, and the unit conductive pattern CCP can be isolated from each other through the slit structure SLS in the first direction D1.

[0041] In one embodiment, the slit structure SLS may include spacers SP and source contacts SC. The spacers SP may be disposed on both sides of the source contacts SC. The spacers SP and the source contacts SC may extend in a second direction D2 and a third direction D3. The spacers SP may be spaced apart from each other in a first direction D1, with the source contacts SC interposed between them. The source contacts SC may be electrically isolated from the conductive pattern CP by the spacers SP. The source contacts SC may be electrically connected to a source structure. In another embodiment, the slit structure SLS may include an insulator instead of the source contacts SC.

[0042] The spacer SP may include an insulating material. In an example, the spacer SP may include an oxide. The source contact SC may include a conductive material. In an example, the source contact SC may include at least one of polysilicon and tungsten.

[0043] Bit line contacts (not shown) may be provided, which penetrate the first portion IS1 of the insulating structure IS and connect to the channel layer CL. The bit line contacts may extend in the third direction D3. The bit line contacts may include a conductive material. In an example, the bit line contacts may include copper, aluminum, or tungsten. The channel layer CL may be electrically connected to the bit line via the bit line contacts.

[0044] Reference Figure 1B The selected conductive pattern SCP may include a first selected conductive pattern SCP1, a second selected conductive pattern SCP2 disposed at a height lower than the height of the first selected conductive pattern SCP1, and a third selected conductive pattern SCP3 disposed at a height lower than the height of the second selected conductive pattern SCP2. The second selected conductive pattern SCP2 may be disposed between the first selected conductive pattern SCP1 and the third selected conductive pattern SCP3. The unit conductive pattern CCP may be disposed at a height lower than all of the first to third selected conductive patterns SCP1, SCP2, and SCP3.

[0045] A dummy storage pattern DDP may include a first dummy storage pattern DDP1, a second dummy storage pattern DDP2 disposed at a height lower than the height of the first dummy storage pattern DDP1, and a third dummy storage pattern DDP3 disposed at a height lower than the height of the second dummy storage pattern DDP2. The second dummy storage pattern DDP2 may be disposed between the first dummy storage pattern DDP1 and the third dummy storage pattern DDP3. A cell storage pattern CDP may be disposed at a height lower than all of the first to third dummy storage patterns DDP1, DDP2, and DDP3.

[0046] The dummy blocking pattern DBP may include a first dummy blocking pattern DBP1, a second dummy blocking pattern DBP2 disposed at a height lower than the height of the first dummy blocking pattern DBP1, and a third dummy blocking pattern DBP3 disposed at a height lower than the height of the second dummy blocking pattern DBP2. The second dummy blocking pattern DBP2 may be disposed between the first dummy blocking pattern DBP1 and the third dummy blocking pattern DBP3. The unit blocking pattern CBP may be disposed at a height lower than all of the first to third blocking patterns DBP1, DBP2, and DBP3.

[0047] The first selective conductive pattern SCP1 can be disposed between the first dummy storage pattern DDP1 and the second dummy storage pattern DDP2. The second selective conductive pattern SCP2 can be disposed between the second dummy storage pattern DDP2 and the third dummy storage pattern DDP3. The third selective conductive pattern SCP3 can be disposed between the third dummy storage pattern DDP3 and the cell storage pattern CDP.

[0048] The first selective conductive pattern SCP1 can be disposed between the first dummy blocking pattern DBP and the second dummy blocking pattern DBP2. The second selective conductive pattern SCP2 can be disposed between the second dummy blocking pattern DBP2 and the third dummy blocking pattern DBP3. The third selective conductive pattern SCP3 can be disposed between the third dummy blocking pattern DBP3 and the unit blocking pattern CBP.

[0049] Each of the first through third selected conductive patterns SCP1, SCP2, and SCP3 may include an insertion portion IN. The insertion portions IN of the first through third selected conductive patterns SCP1, SCP2, and SCP3 may overlap with the cell storage pattern CDP and the first through third dummy storage patterns DDP1, DDP2, and DDP3. The insertion portions IN of the first through third selected conductive patterns SCP1, SCP2, and SCP3 may overlap with the cell blocking pattern CBP and the first through third dummy blocking patterns DBP1, DBP2, and DBP3.

[0050] The insertion portion IN of the first selective conductive pattern SCP1 can be inserted between the first dummy storage pattern DDP1 and the second dummy storage pattern DDP2, and between the first dummy blocking pattern DBP1 and the second dummy blocking pattern DBP2. The insertion portion IN of the second selective conductive pattern SCP2 can be inserted between the second dummy storage pattern DDP2 and the third dummy storage pattern DDP3, and between the second dummy blocking pattern DBP2 and the third dummy blocking pattern DBP3. The insertion portion IN of the third selective conductive pattern SCP3 can be inserted between the third dummy storage pattern DDP3 and the cell storage pattern CDP, and between the third dummy blocking pattern DBP3 and the cell blocking pattern CBP.

[0051] The insertion portion IN of the first selective conductive pattern SCP1 can contact the first exposed sidewall TL_S1 of the tunnel insulating layer TL exposed between the first dummy storage pattern DDP1 and the second dummy storage pattern DDP2. The insertion portion IN of the second selective conductive pattern SCP2 can contact the second exposed sidewall TL_S2 of the tunnel insulating layer TL exposed between the second dummy storage pattern DDP2 and the third dummy storage pattern DDP3. The insertion portion IN of the third selective conductive pattern SCP3 can contact the third exposed sidewall TL_S3 of the tunnel insulating layer TL exposed between the third dummy storage pattern DDP3 and the unit storage pattern CDP. The unit conductive pattern CCP can be spaced apart from the tunnel insulating layer TL.

[0052] The insertion portion IN of the first selective conductive pattern SCP1 can contact the bottom surface DDP1_B of the first dummy storage pattern DDP1, the bottom surface DBP_B of the first dummy blocking pattern DBP1, the top surface DDP2_T of the second dummy storage pattern DDP2, and the top surface DBP2_T of the second dummy blocking pattern DBP2. The insertion portion IN of the second selective conductive pattern SCP2 can contact the bottom surface of the second dummy storage pattern DDP2, the bottom surface of the second dummy blocking pattern DBP2, the top surface of the third dummy storage pattern DDP3, and the top surface of the third dummy blocking pattern DBP3. The insertion portion IN of the third selective conductive pattern SCP3 can contact the bottom surface of the third dummy storage pattern DDP3, the bottom surface of the third dummy blocking pattern DBP3, the top surface of the cell storage pattern CDP, and the top surface of the cell blocking pattern CBP.

[0053] The isolation structure DS isolates the first selective conductive pattern SCP1, which is positioned at the same height in the first direction D1, from each other. The isolation structure DS also isolates the second selective conductive pattern SCP2, which is positioned at the same height in the first direction D1, from each other. The isolation structure DS further isolates the third selective conductive pattern SCP3, which is positioned at the same height in the first direction D1, from each other. The lowermost part of the isolation structure DS, DS_B, can be positioned between the unit conductive pattern CCP and the third selective conductive pattern SCP3.

[0054] A recessed RS may be defined by an isolation structure DS. The recessed RS is formed when the sidewall DS_S of the isolation structure DS is depressed. Therefore, the recessed RS is then defined by the sidewall DS_S of the isolation structure DS, thereby causing the isolation structure DS to depression. Each of the first to third selective conductive patterns SCP1, SCP2, and SCP3 may include an insertion portion SE inserted into the recessed RS. The top surface SE_T and bottom surface SE_B of the insertion portion SE of each of the first to third selective conductive patterns SCP1, SCP2, and SCP3 may contact the isolation structure DS. The insertion portion SE of the first to third selective conductive patterns SCP1, SCP2, and SCP3 may overlap with the isolation structure DS.

[0055] Reference Figure 1C The portion of the unit plug PL that protrudes beyond the stacked structure STA can be defined as the protruding portion PT. The first part IS1 of the insulating structure IS can cover the protruding portion PT of the unit plug PL. The first part IS1 of the insulating structure IS can cover the top surface PT_T and sidewall PT_S of the protruding portion PT of the unit plug PL.

[0056] The first part IS1 of the insulating structure IS may overlap with the unit plug PL. The height of the uppermost part IS1_UM of the first part IS1 of the insulating structure IS may be higher than the height of the top surface PT_T of the protruding part PT. The width of the first part IS1 of the insulating structure IS in the first direction D1 may be defined as a first width W1. The first width W1 may become maximum at a first height LV1. The first height LV1 may be a height between the height of the uppermost part IS1_UM of the first part IS1 of the insulating structure IS and the height of the central part of the first part IS1 of the insulating structure IS. The height of the central part of the first part IS1 of the insulating structure IS may be defined as a second height LV2. The distance between the second height LV2 and the height of the uppermost part IS1_UM of the first part IS1 of the insulating structure IS may be equal to the distance between the second height LV2 and the height of the top surface STA_T of the stacked structure STA. The second height LV2 may be higher than the height of the top surface PT_T of the protruding part PT.

[0057] The first width W1 may decrease as it approaches the top surface STA_T of the laminated structure STA from the first height LV1. The first width W1 may decrease as it approaches the uppermost part IS_UM of the first part IS1 of the insulating structure IS from the first height LV1.

[0058] The second part IS2 of the insulating structure IS may cover the top surface STA_T of the laminated structure STA. The height of the top surface IS2_T of the second part IS2 of the insulating structure IS may be lower than the height of the top surface PT_T of the protruding part PT.

[0059] The width of the first cavity CA1 defined between the first portions IS1 of the insulating structure IS in the first direction D1 can decrease as it approaches the top surface IS2_T of the second portion IS2 of the insulating structure IS from the first height LV1.

[0060] In the semiconductor device according to the embodiments of the present disclosure, since the first to third selective conductive patterns SCP1, SCP2 and SCP3 are in contact with the tunnel insulating layer TL, only the tunnel insulating layer TL is disposed between the first to third selective conductive patterns SCP1, SCP2 and SCP3 and the channel layer CL, so that the cutoff characteristics of the selective transistor can be improved.

[0061] In the semiconductor device according to embodiments of the present disclosure, no storage pattern is disposed between the first to third selective conductive patterns SCP1, SCP2, and SCP3 and the tunnel insulating layer TL. Therefore, the programming operation of the storage pattern connected to the first to third selective conductive patterns SCP1, SCP2, and SCP3 can be omitted in the testing process of the semiconductor device, thereby simplifying the testing process of the semiconductor device.

[0062] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 12A , Figure 13 and Figure 14 It is shown Figures 1A to 1C A cross-sectional view of the manufacturing method of the semiconductor device shown. Figure 11B yes Figure 11A An enlarged view of region C shown. Figure 12B yes Figure 12A An enlarged view of region D shown.

[0063] For ease of description, refer to Figures 1A to 1C Components that are described the same are referred to by similar labels, and duplicate descriptions will be omitted.

[0064] The manufacturing method described below is only one aspect. Figures 1A to 1C One embodiment of the method for manufacturing the semiconductor device shown. Figures 1A to 1C The manufacturing method of the semiconductor device shown may not be limited to that described below.

[0065] Reference Figure 2 A stacked structure STA can be formed. In an embodiment, the stacked structure STA can be formed on a source structure (not shown). The stacked structure STA may include a stacked insulating layer IL, a unit sacrificial layer CFL, and a selective sacrificial layer SFL. The stacked insulating layer IL and the unit sacrificial layer CFL may be stacked alternately in the third direction D3. The stacked insulating layer IL, the unit sacrificial layer CFL, and the selective sacrificial layer SFL may overlap each other. The selective sacrificial layer SFL may be disposed at a height higher than the height of the unit sacrificial layer CFL.

[0066] The stacked insulating layer IL may include an insulating material. In an example, the stacked insulating layer IL may include an oxide. The unit sacrificial layer CFL may include a material different from that of the stacked insulating layer IL. In an example, the unit sacrificial layer CFL may include a nitride. The selected sacrificial layer SFL may include a material that has etch selectivity relative to the stacked insulating layer IL and the unit sacrificial layer CFL. In an example, the selected sacrificial layer SFL may include polysilicon.

[0067] A first mask layer MA1 may be formed on the stacked structure STA. In the example, the first mask layer MA1 may include a nitride. The thickness of the first mask layer MA1 may be greater than the thickness of the uppermost stacked insulating layer IL of the stacked structure STA.

[0068] Reference Figure 3 A first aperture HO1 can be formed that penetrates the first mask layer MA1 and the stacked structure STA. Forming the first aperture HO1 may include: forming a photoresist layer (not shown) including a first opening on the first mask layer MA1; and using the photoresist layer as an etching barrier to etch the first mask layer MA1 and the stacked structure STA. The first aperture HO1 can penetrate the stacked insulating layer IL, the unit sacrificial layer CF, and the selected sacrificial layer SFL. After forming the first aperture HO1, the remaining photoresist layer can be removed.

[0069] Reference Figure 4 A preliminary barrier layer pBKL, a preliminary storage layer pDL, a preliminary tunnel insulation layer pTL, a preliminary channel layer pCL, and a fill layer FI can be formed sequentially. The preliminary barrier layer pBKL can cover the sidewall of the first hole HO1 and the top surface of the first mask layer MA1. The preliminary storage layer pDL can cover the preliminary barrier layer pBKL. The preliminary tunnel insulation layer pTL can cover the preliminary storage layer pDL. The preliminary channel layer pCL can cover the preliminary tunnel insulation layer pTL. The fill layer FI can be formed in the preliminary channel layer pCL.

[0070] The initial barrier layer pBKL may include a material capable of blocking the movement of charge. In one embodiment, the initial storage layer pDL may include a material capable of trapping charge. The initial tunneling insulation layer pTL may include a material through which charge can tunnel.

[0071] Forming the filler layer FI may include: forming a filler material layer covering the initial channel layer pCL; and removing the top portion of the filler material layer. The height of the top surface of the filler layer FI may be lower than the height of the top surface of the laminated structure STA.

[0072] Reference Figure 5 A barrier layer pBKL, a storage layer pDL, a tunnel insulation layer pTL, and a channel layer CL can be formed. Forming the barrier layer pKL, storage layer pDL, tunnel insulation layer pTL, and channel layer CL may include: forming a capping channel layer covering the initial channel layer pCL and the filler layer FI; and removing the upper portion of the initial barrier layer pBKL, the upper portion of the initial storage layer pDL, the upper portion of the initial tunnel insulation layer pTL, the upper portion of the initial channel layer pCL, and the upper portion of the capping channel layer. The upper portion of the removed initial barrier layer pBKL can be defined as the barrier layer BKL. The partially removed initial storage layer pDL can be defined as the storage layer DL. The upper portion of the removed initial tunnel insulation layer pTL can be defined as the tunnel insulation layer TL. The upper portion of the removed initial channel layer pCL and the upper portion of the removed capping channel layer can be defined as the channel layer CL. A storage layer ML can be defined, which includes the barrier layer BKL, the storage layer DL, and the tunnel insulation layer TL.

[0073] In the example, the upper portions of the initial barrier layer pBKL, the initial storage layer pDL, the initial tunnel insulation layer pTL, the initial channel layer pCL, and the capping channel layer can be removed by chemical mechanical polishing (CMP). The upper portion of the first mask layer MA1 can be removed together with the upper portions of the initial barrier layer pBKL, the initial storage layer pDL, the initial tunnel insulation layer pTL, the initial channel layer pCL, and the capping channel layer.

[0074] Reference Figure 6 The first mask layer MA1 can be removed. In this example, the first mask layer MA1 can be removed using a wet etching process. When the first mask layer MA1 is removed, the top surface of the stacked structure STA is exposed. When the first mask layer MA1 is removed, the top surface of the channel layer CL, the top surface of the tunnel insulating layer TL, the top surface of the storage layer DL, the top surface of the barrier layer BKL, and a portion of the outer wall of the barrier layer BKL are exposed.

[0075] An insulating structure IS can be formed, covering the top surface of the laminated structure STA, the top surface of the channel layer CL, the top surface of the tunnel insulation layer TL, the top surface of the storage layer DL, the top surface of the barrier layer BKL, and a portion of the outer wall of the barrier layer BKL. A first portion IS1 of the insulating structure IS can cover the top surface of the channel layer CL, the top surface of the tunnel insulation layer TL, the top surface of the storage layer DL, the top surface of the barrier layer BKL, and a portion of the outer wall of the barrier layer BKL. A second portion IS2 of the insulating structure IS can connect the first portions IS1 of the insulating structure IS to each other. The second portion IS2 of the insulating structure IS can cover the top surface of the laminated structure STA.

[0076] An insulating structure IS can be formed by depositing a first deposition material. The first deposition material may have a relatively poor step coverage. Due to the relatively poor step coverage of the first deposition material, the first portion IS1 of the insulating structure IS can be formed to be thicker than the second portion IS2 of the insulating structure IS. Due to the relatively poor step coverage of the first deposition material, the width of the first portion IS1 of the insulating structure IS can be formed to be non-constant. The width of the first portion IS1 of the insulating structure IS in the first direction D1 may be maximized at the central portion and the uppermost portion of the first portion IS1 of the insulating structure IS.

[0077] A first cavity CA1 may be defined by the sidewalls of the first portion IS1 of the insulating structure IS and the top surface of the second portion IS2 of the insulating structure IS. The first cavity CA1 may be the space between the first portions IS1 of the insulating structure IS.

[0078] Reference Figure 7A second mask layer MA2 may be formed on the insulating structure IS. The second mask layer MA2 may include a second opening OP2. The second opening OP2 may extend in a second direction D2. Forming the second mask layer MA2 may include: forming a second mask layer MA2 covering the insulating structure IS; and forming the second opening OP2 by removing a portion of the second mask layer MA2. In an example, the second mask layer MA2 may be a photoresist layer.

[0079] Some first cavities CA1 can be exposed through the second opening OP2 of the second mask layer MA2. Multiple first cavities CA1 can be exposed through the second opening OP2. Multiple first cavities CA1 can be connected to the second opening OP2. A portion of the first part IS1 of the insulating structure IS can be exposed through the second opening OP2 of the second mask layer MA2. The portion of the first part IS1 of the insulating structure IS exposed through the second opening OP2 of the second mask layer MA2 can be defined as the first exposed portion EP1. A portion of the second part IS2 of the insulating structure IS can be exposed through the second opening OP2 of the second mask layer MA2. The portion of the second part IS2 of the insulating structure IS exposed through the second opening OP2 of the second mask layer MA2 can be defined as the second exposed portion EP2.

[0080] Reference Figure 8 The insulating structure IS and the stacked structure STA can be etched by using a second mask layer MA2 as an etching barrier. The second exposed portion EP2 and the first cavity CA1, exposed through the second opening OP2 of the second mask layer MA2, can be etched, and the exposed stacked structure can be etched when the second exposed portion EP2 is etched. In the process of etching the second exposed portion EP2 and the stacked structure STA, the first exposed portion EP1 can be used as an etching barrier.

[0081] When the insulating structure IS is etched, the first exposed portion EP1 of the first part IS1 of the insulating structure IS can be removed, and the second exposed portion EP2 of the second part IS2 of the insulating structure IS can be removed. A third opening OP3 can be defined by the sidewalls of the etched first part IS1 of the insulating structure IS. The space between the sidewalls of the etched first part IS1 of the insulating structure IS can be defined as the third opening OP3. The third opening OP3 can extend in the second direction D2.

[0082] An etchable multilayer structure STA comprises a multilayer insulating layer IL and a selective sacrificial layer SFL. When the multilayer insulating layer IL and the selective sacrificial layer SFL of the multilayer structure STA are etched, a fourth opening OP4 is defined. The fourth opening OP4 is defined by the sidewalls of the etched multilayer insulating layer IL and the etched selective sacrificial layer SFL. The space between the etched multilayer insulating layer IL and the etched selective sacrificial layer SFL can be defined as the fourth opening OP4. The fourth opening OP4 can extend in the second direction D2.

[0083] Based on the structure of the first portion IS1 of the insulating structure IS, the first exposed portion EP1 of the first portion IS1 of the insulating structure IS can be used as an etching barrier in the process of forming the fourth opening OP4. Therefore, even when the second opening OP2 of the second mask layer MA2 is relatively large, the fourth opening OP4 can be formed to be relatively narrow.

[0084] The fourth opening OP4 can be located below the third opening OP3. The bottom part of the fourth opening OP4 can be located within the laminated insulating layer IL. The second to fourth openings OP2, OP3 and OP4 can overlap each other.

[0085] The Selective Sacrifice Layer (SFL) may include a first Selective Sacrifice Layer (SFL1) located at the highest altitude, a second Selective Sacrifice Layer (SFL2) located at the lowest altitude, and a third Selective Sacrifice Layer (SFL3) located between the first Selective Sacrifice Layer (SFL1) and the second Selective Sacrifice Layer (SFL2).

[0086] When the fourth opening OP4 is formed, a first-selection sacrificial layer SFL1 can be isolated into two first-selection sacrificial layers SFL1, a second-selection sacrificial layer SFL2 can be isolated into two second-selection sacrificial layers SFL2, and a third-selection sacrificial layer SFL3 can be isolated into two third-selection sacrificial layers SFL3.

[0087] Reference Figure 9 The second mask layer MA2 can then be removed. Subsequently, an isolation structure DS and a first insulating layer 110 can be formed. The isolation structure DS can fill the fourth opening OP4. The first insulating layer 110 can fill the third opening OP3 and cover the insulating structure IS.

[0088] The isolation structure DS and the first insulating layer 110 can be formed simultaneously. The isolation structure DS and the first insulating layer 110 can be formed by depositing a second deposition material via a single process. In this example, the second deposition material can be an oxide. The isolation structure DS and the first insulating layer 110 can be formed continuously without any boundaries.

[0089] Reference Figure 10 A third mask layer MA3 may be formed on the first insulating layer 110. The third mask layer MA3 may include a fifth opening OP5. The fifth opening OP5 may extend in the second direction D2. Forming the third mask layer MA3 may include: forming a third mask layer MA3 covering the first insulating layer 110; and forming the fifth opening OP5 by removing a portion of the third mask layer MA3. In an example, the third mask layer MA3 may be a photoresist layer.

[0090] The first insulating layer 110, the insulating structure IS, and the stacked structure STA can be etched using a third mask layer MA3 as an etching barrier. When the first insulating layer 110, the insulating structure IS, and the stacked structure STA are etched, a sixth opening OP6 can be formed. The sixth opening OP6 can extend in the second direction D2 and the third direction D3. The fifth opening OP5 and the sixth opening OP6 can overlap each other.

[0091] In this implementation, through the sixth opening OP6, one first selected sacrificial layer SFL1 can be isolated into two first selected sacrificial layers SFL1, and one third selected sacrificial layer SFL3 can be isolated into two third selected sacrificial layers SFL3. The second selected sacrificial layer SFL2 may not be isolated by the sixth opening OP6.

[0092] The selective sacrificial layer SFL can be exposed through the sixth opening OP6. In an embodiment, the sidewalls of the first selective sacrificial layer SFL1, isolated by the sixth opening OP6, are exposed; the sidewalls of the third selective sacrificial layer SFL3, isolated by the sixth opening OP6, are exposed; and the top surface of the second selective sacrificial layer SFL2 is exposed.

[0093] Reference Figure 11A and Figure 11B The third mask layer MA3 can be removed. The selective sacrificial layer SFL exposed through the sixth opening OP6 can be removed. The selective sacrificial layer SFL can be selectively removed by using a first etch material capable of selectively etching the selective sacrificial layer SFL. In the example, the first etch material can be a material capable of selectively etching polysilicon. When the selective sacrificial layer SFL is removed, the sidewalls of the barrier layer BKL can be exposed. When the selective sacrificial layer SFL is removed, the sidewalls of the isolation structure DS can be exposed.

[0094] The exposed sidewalls of the barrier layer BKL can be etched. The sidewalls of the barrier layer BKL can be etched using a second etch material capable of selectively etching the barrier layer BKL. In this example, the second etch material can be a material capable of selectively etching oxides. When the barrier layer BKL is etched, the barrier layer BKL can be isolated into a cell barrier pattern CBP and first to third dummy barrier patterns DBP1, DBP2, and DBP3. When the barrier layer BKL is etched, the sidewalls of the storage layer DL can be exposed.

[0095] While the sidewalls of the barrier layer BKL are being etched, the sidewalls of the isolation structure DS can also be etched. The sidewalls of the isolation structure DS can be etched using a second etching material. As the isolation structure DS is etched, a recess RS can be defined within the isolation structure DS.

[0096] After the barrier layer BKL is etched, the exposed sidewalls of the storage layer DL can be etched. The sidewalls of the storage layer DL can be etched using a third etch material capable of selectively etching the storage layer DL. In this example, the third etch material can be a material capable of selectively etching nitrides. When the storage layer DL is etched, it can be isolated into a cell storage pattern CDP and first to third dummy storage patterns DDP1, DDP2, and DDP3. When the storage layer DL is etched, the sidewalls of the tunnel insulation layer TL can be exposed.

[0097] The blank space formed by etching the sacrificial layer SFL, the barrier layer BKL, and the storage layer DL can be defined as the second cavity CA2. The second cavity CA2 can be connected to the sixth opening OP6. The second cavity CA2 can be connected to the recess RS.

[0098] Reference Figure 12A and Figure 12B A filling sacrificial layer FFL can be formed in the recess RS, the second cavity CA2, and the sixth opening OP6. The filling sacrificial layer FFL can fill the recess RS, the second cavity CA2, and the sixth opening OP6. The filling sacrificial layer FFL can cover the first insulating layer 110. The filling sacrificial layer FFL can include the same material as the unit sacrificial layer CFL. In an example, the filling sacrificial layer FFL can include a nitride.

[0099] The sacrificial filler leaflet (FFL) may include a first portion FFL1, a second portion FFL2, and a third portion FFL3. The first portion FFL1 fills the second cavity CA2. The first portion FFL1 also fills the recess RS. The second portion FFL2 fills the sixth opening OP6. The third portion FFL3 covers the first insulating layer 110. The first portion FFL1 is connected to the second portion FFL2, and the second portion FFL2 is connected to the third portion FFL3.

[0100] The first portion of the sacrificial filler layer FFL, disposed between the cell storage pattern CDP and the third dummy storage pattern DDP3, can contact the top surface of the cell storage pattern CDP, the top surface of the cell blocking pattern CBP, the bottom surface of the third dummy storage pattern DDP3, and the bottom surface of the third dummy blocking pattern DBP3. The first portion of the sacrificial filler layer FFL, disposed between the third dummy storage pattern DDP3 and the second dummy storage pattern DDP2, can contact the top surface of the third dummy storage pattern DDP3, the top surface of the third dummy blocking pattern DBP3, the bottom surface of the second dummy storage pattern DDP2, and the bottom surface of the second dummy blocking pattern DBP2. The first portion of the sacrificial filler layer FFL, disposed between the second dummy storage pattern DDP2 and the first dummy storage pattern DDP1, can contact the top surface of the second dummy storage pattern DDP2, the top surface of the second dummy blocking pattern DBP2, the bottom surface of the first dummy storage pattern DDP1, and the bottom surface of the first dummy blocking pattern DBP1. A portion of the first part of the sacrificial layer FFL1 can be inserted into the recessed RS.

[0101] Reference Figure 13 A fourth mask layer MA4 may be formed on the filler sacrificial layer FFL. The fourth mask layer MA4 may be formed on a third portion FFL3 of the filler sacrificial layer FFL. The fourth mask layer MA4 may include a seventh opening OP7. Forming the fourth mask layer MA4 may include: forming a fourth mask layer MA4 covering the filler sacrificial layer FFL; and forming the seventh opening OP7 by removing a portion of the fourth mask layer MA4. In the example, the fourth mask layer MA4 may be a photoresist layer.

[0102] The seventh opening OP7 may overlap with the sixth opening OP6. The seventh opening OP7 may overlap with the second portion FFL2 of the sacrificial layer FFL. The seventh opening OP7 may extend in the second direction D2.

[0103] The filler sacrificial layer FFL and the stacked structure STA can be etched using a fourth mask layer MA4 as an etch barrier. The space formed when the filler sacrificial layer FFL and the stacked structure STA are etched can be defined as the eighth opening OP8.

[0104] When the filler sacrificial layer FFL is etched, the second portion FFL2 of the filler sacrificial layer FFL can be removed. When the second portion FFL2 of the filler sacrificial layer FFL is removed, the first portion FFL1 and the third portion FFL3 of the filler sacrificial layer FFL can be isolated from each other. When the second portion FFL2 of the filler sacrificial layer FFL is removed, the laminated insulating layer IL and the first portion FFL1 of the filler sacrificial layer FFL can be exposed through the eighth opening OP8. The eighth opening OP8 can be defined by the sidewalls of the exposed laminated insulating layer IL and the exposed first portion FFL1 of the filler sacrificial layer FFL.

[0105] An etchable stacked insulating layer IL and a unit sacrificial layer CFL are provided. An eighth opening OP8 is defined by the sidewalls of the etched stacked insulating layer IL and the etched unit sacrificial layer CFL. The etched stacked insulating layer IL and the etched unit sacrificial layer CFL are exposed through the eighth opening OP8. When the eighth opening OP8 is formed, one unit sacrificial layer CFL can be isolated into multiple unit sacrificial layer CFLs.

[0106] The eighth opening OP8 may extend in the second direction D2 and the third direction D3. The eighth opening OP8 may overlap with the seventh opening OP7. The eighth opening OP8 may penetrate the stacked structure STA.

[0107] Reference Figure 14 The fourth mask layer MA4 can be removed. The first portion FFL1 and the third portion FFL3 of the fill sacrificial layer FFL, as well as the unit sacrificial layer CFL, can be removed. The first portion FFL1 and the third portion FFL3 of the fill sacrificial layer FFL, as well as the unit sacrificial layer CFL, can be selectively etched using a fourth etch material capable of selectively etching the first portion FFL1 and the third portion FFL3 of the fill sacrificial layer FFL, as well as the unit sacrificial layer CFL. In this example, the fourth etch material selectively etches the nitride.

[0108] When the first portion FFL1 of the filler sacrificial layer FFL is removed, the sidewall of the tunnel insulation layer TL can be exposed.

[0109] Selective conductive pattern SCPs can be formed in the empty spaces left by the removal of the first portion of the sacrificial layer FFL1. Unitary conductive pattern CCPs can be formed in the empty spaces left by the removal of the unitary sacrificial layer CFL. Selective conductive pattern SCPs can contact the exposed sidewalls of the tunnel insulation layer TL.

[0110] Subsequently, a slit structure SLS can be formed in the eighth opening OP8 (see...). Figure 1A It can also form bit line contacts connected to the channel layer CL.

[0111] In the semiconductor device manufacturing method according to an embodiment of the present disclosure, the channel structure CS and the memory layer ML are formed to protrude above the stacked structure STA, thereby the insulating structure IS can be formed to include a first portion IS1 and a second portion IS2. According to the structure of the first portion IS1 of the insulating structure IS, the first portion IS1 serves as an etching barrier, thereby allowing the stacked structure STA to be self-aligned for etching. Therefore, even when the second opening OP2 of the second mask layer MA2 is relatively large, the fourth opening OP4 can be formed to be relatively narrow. Because the fourth opening OP4 is formed to be relatively narrow, damage to the memory layer ML and the channel structure CS can be prevented during the process of forming the isolation structure DS. Furthermore, because the fourth opening OP4 is formed to be relatively narrow, sufficient space can be ensured between the isolation structure DS and the memory layer ML to form the selective conductive pattern SCP. Additionally, because the fourth opening OP4 is formed to be relatively narrow, the isolation structure DS can be formed without forming any dummy channel structure or any dummy memory layer.

[0112] Figure 15 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0113] Reference Figure 15 The memory system 1100 according to an embodiment of the present disclosure includes a memory device 1120 and a memory controller 1110.

[0114] The memory device 1120 may include the semiconductor device described above. The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0115] The storage controller 1110 is configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory of the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The ECC circuit 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. Additionally, the storage controller 1110 may also include ROM for storing code data, etc., used for interfacing with the host.

[0116] The memory system 1100 configured as described above can be a memory card or a solid-state drive (SSD), wherein the memory device 1120 is combined with the controller 1110. For example, when the memory system 1100 is an SSD, the storage controller 1110 can communicate with an external source (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronic Devices (IDE) protocol.

[0117] Figure 16 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0118] Reference Figure 16 The computing system 1200 according to embodiments of the present disclosure may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210, which are electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor, mobile DRAM, etc.

[0119] Memory system 1210 is available and referenced Figure 15 The similar memory devices 1212 and memory controllers 1211 described are configured to be used.

[0120] In the semiconductor device according to this disclosure, a selective conductive pattern is made in contact with a tunnel insulating layer to improve the cutoff characteristics of the selective transistor.

[0121] In semiconductor device manufacturing methods, the memory layer and channel structure can be prevented from being damaged during the process of forming the isolation structure by using an insulating structure to etch the stacked structure.

[0122] Examples of embodiments of the present disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for illustrative purposes only. Therefore, the present disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of the present disclosure in addition to the embodiments disclosed herein.

[0123] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the meaning commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms having a dictionary definition shall be understood to have a meaning consistent with the context of the relevant art. Unless clearly defined in this application, terms shall not be interpreted in an ideal or overly formal manner.

[0124] Cross-references to related applications

[0125] This application claims priority to Korean Patent Application No. 10-2020-0093249, filed on July 27, 2020, with the Korean Intellectual Property Office, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A stacked structure comprising alternating layers of conductive patterns and multiple layers of insulating layers; A channel structure that penetrates the stacked structure; A tunnel insulation layer surrounding the trench structure; A cell storage pattern surrounds the tunnel insulation layer; as well as A dummy storage pattern surrounds the tunnel insulation layer and is spaced apart from the cell storage pattern. The conductive pattern includes a selective conductive pattern that serves as a selection line and contacts the tunnel insulation layer. The tunnel insulation layer is disposed between the selected conductive pattern and the trench structure.

2. The semiconductor device according to claim 1, wherein The selected conductive pattern is disposed between the cell storage pattern and the dummy storage pattern.

3. The semiconductor device according to claim 1, wherein A portion of the selected conductive pattern overlaps with the cell storage pattern and the dummy storage pattern.

4. The semiconductor device according to claim 1, wherein The selected conductive pattern is in contact with the top surface of the cell storage pattern.

5. The semiconductor device according to claim 1, wherein The selected conductive pattern comes into contact with the dummy storage pattern.

6. The semiconductor device of claim 1, further comprising a cell blocking pattern surrounding the cell storage pattern and a dummy blocking pattern surrounding the dummy storage pattern. in, The selected conductive pattern is disposed between the unit blocking pattern and the dummy blocking pattern.

7. The semiconductor device according to claim 6, wherein, A portion of the selected conductive pattern overlaps with the unit blocking pattern and the dummy blocking pattern.

8. The semiconductor device according to claim 1, wherein, The conductive pattern includes unit conductive patterns spaced apart from the tunnel insulation layer.

9. The semiconductor device of claim 8, further comprising a cell blocking pattern surrounding the cell storage pattern and a dummy blocking pattern surrounding the dummy storage pattern. in, The selected conductive pattern is disposed between the unit blocking pattern and the dummy blocking pattern, and The unit conductive pattern surrounds the unit blocking pattern.

10. A method for manufacturing a semiconductor device, the method comprising the following steps: This forms a laminated structure comprising overlapping unit sacrificial layers, selective sacrificial layers, and laminated insulating layers; Forming holes that penetrate the stacked structure; A barrier layer, a storage layer, a tunnel insulation layer, and a trench structure are formed within the hole; Forming a first opening that exposes the selected sacrificial layer; The selected sacrifice layer is removed through the first opening; A first portion of a filler sacrificial layer is formed in the blank space created by removing the selected sacrificial layer, the first portion of the filler sacrificial layer penetrating the barrier layer and the storage layer and contacting the sidewall of the tunnel insulation layer; A second opening is formed, which exposes the first portion of the filling sacrificial layer and the unit sacrificial layer; as well as Remove the first portion of the filling sacrificial layer and the unit sacrificial layer.

11. The method of claim 10, further comprising the step of: The second portion of the filling sacrificial layer is formed by filling the first opening.

12. The method according to claim 11, wherein, The step of forming the second opening includes the following steps: removing the second portion of the filling sacrificial layer.

13. The method of claim 10, further comprising the step of: Conductive patterns are formed in the first portion of the filling sacrificial layer and in the blank spaces where the unit sacrificial layer is removed.

14. The method of claim 10, further comprising the step of: An isolation structure is formed to isolate the selected sacrificial layer.

Images