A display panel and display device

Abstract

A display panel and a display device, wherein the display panel comprises a display area and a non-display area surrounding the display area, the display area comprises a first display area and a second display area located at least one side of the first display area, the second display area comprises a first region and a second region arranged at intervals, the first region and the second region are arranged along a first direction, and the first display area is located between the first region and the second region; the display panel comprises a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate; the circuit structure layer comprises a plurality of driving circuits and a plurality of data signal lines extending along a second direction, and the light-emitting structure layer comprises a plurality of light-emitting elements; the data signal lines are configured to provide data signals to the driving circuits, the driving circuits are configured to drive the light-emitting elements to emit light, the first direction and the second direction intersect, the light-emitting elements are located in the first display area and the second display area, and the driving circuits are located in the first region and the second region.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Currently, the concept of full-screen phones has received widespread attention in the mobile phone market and represents the future direction of mobile phone development. In these full-screen phones, the camera can be hidden so that the front viewable area is almost entirely screen, thus providing users with a superior display experience. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display panel, comprising: a display area and a non-display area surrounding the display area, the display area comprising: a first display area and a second display area located on at least one side of the first display area; the second display area comprising: a first region and a second region spaced apart, the first display area being located between the first region and the second region;

[0006] The display panel includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending along a second direction; the light-emitting structure layer includes: a plurality of light-emitting elements; the data signal lines are configured to provide data signals to the driving circuits, the driving circuits are configured to drive the light-emitting elements to emit light, and the first direction and the second direction intersect;

[0007] The light-emitting element is located in the first display area and the second display area, and the driving circuit is located in the first area and the second area.

[0008] In some possible implementations, the length of the first display area along the second direction is less than or equal to the length of the second display area along the second direction.

[0009] In some possible implementations, the length of the driving circuit along the first direction is less than the length of the light-emitting element connected to the driving circuit along the first direction.

[0010] In some possible implementations, the driving circuit includes: a first driving circuit and a second driving circuit;

[0011] The first driving circuit is connected to the first light-emitting element, and the second driving circuit is connected to the second light-emitting element. The first light-emitting element is located in the second display area, and the second light-emitting element is located in the first display area.

[0012] In some possible implementations, the driving circuit includes: a first transistor to a seventh transistor; the light-emitting element includes: an anode, an organic light-emitting layer, and a cathode; the second terminal of the sixth transistor of the driving circuit is connected to the anode of the light-emitting element;

[0013] The orthographic projection of the second electrode of the sixth transistor of the driving circuit onto the substrate does not overlap with the orthographic projection of the anode of the light-emitting element connected to the driving circuit onto the substrate.

[0014] In some possible implementations, the circuit structure layer further includes: a plurality of first transition sections, the first transition sections being located between the second electrode of the sixth transistor of the first driving circuit and the anode of the first light-emitting element;

[0015] The first driving circuit is connected to the first light-emitting element through the first adapter. The orthographic projection of the first adapter on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the first driving circuit connected to the first adapter on the substrate, and at least partially overlaps with the orthographic projection of the anode of the first light-emitting element connected to the first connection on the substrate.

[0016] The materials used to manufacture the first adapter include: metal.

[0017] In some possible implementations, the circuit structure layer further includes: a plurality of second transition sections, the second transition sections being located between the second electrode of the sixth transistor of the second driving circuit and the anode of the second light-emitting element;

[0018] The second driving circuit is connected to the second light-emitting element through the second adapter. The orthographic projection of the second adapter on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the second driving circuit connected to the second adapter on the substrate, and at least partially overlaps with the orthographic projection of the anode of the second light-emitting element connected to the second connection on the substrate.

[0019] The materials used to manufacture the second adapter include: transparent conductive materials.

[0020] In some possible implementations, the second adapter is located on the same layer as the first adapter, or on a different layer.

[0021] In some possible implementations, when the length of the first display area along the second direction is less than the length of the second display area along the second direction, the second display area further includes: a third region, the third region being located between the first region and the second region, and the third region surrounding the first display area;

[0022] The first region and the second region are symmetrically arranged along the centerline of the third region.

[0023] In some possible implementations, the circuit structure layer further includes: N columns of first dummy driving circuits;

[0024] The N columns of the first dummy driving circuits are located in the third region, where N is a positive integer greater than or equal to M, and M is the number of columns of light-emitting elements in the first display area;

[0025] The length of the first dummy driving circuit along the first direction is greater than or equal to the length of the driving circuit along the first direction.

[0026] In some possible implementations, the first region and the third region are symmetrically arranged along the midline of the second region.

[0027] In some possible implementations, the first region includes: S first sub-regions arranged sequentially along a first direction;

[0028] The interval between adjacent first sub-regions is set.

[0029] In some possible implementations, the circuit structure layer further includes at least one column of second dummy driving circuits located between adjacent first sub-regions.

[0030] In some possible implementations, the second region includes: T second sub-regions arranged sequentially along the first direction;

[0031] The interval between adjacent second sub-regions is set.

[0032] In some possible implementations, the circuit structure layer further includes at least one column of third dummy driving circuits located between adjacent second sub-regions.

[0033] In some possible implementations, S = T.

[0034] In some possible implementations, the data signal line is located in both the first region and the second region;

[0035] The drive circuits located in the same column are connected to the same data signal line.

[0036] In some possible implementations, the circuit structure layer further includes: a plurality of first power lines extending along a second direction; the first power lines are located in the first region and the second region;

[0037] When all the drive circuits in the same column are first drive circuits, the first drive circuits in the same column are connected to the same first power line. When the drive circuits in the same column include a first drive circuit and a second drive circuit, the first drive circuits located on both sides of the second drive circuit are connected to different first power lines.

[0038] In some possible implementations, the circuit structure layer further includes: a plurality of second power lines; the second power lines are located on the side of the first power lines away from the substrate;

[0039] The second drive circuits located in the same column are connected to the same second power supply line;

[0040] The voltage value of the signal on the second power line is greater than the voltage value of the signal on the first power line.

[0041] In some possible implementations, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the second power line is located in both the first and second areas and extends along the second direction.

[0042] In some possible implementations, when the length of the first display area along the second direction is less than the length of the second display area along the second direction, each second power line includes: a first power segment, a second power segment, a third power segment, a fourth power segment, and a fifth power segment connected in sequence; the first power segment, the third power segment, and the fifth power segment extend along the second direction, and the second power segment and the fourth power segment extend along the first direction;

[0043] For each second power line, the first power segment and the fifth power segment are located in the third region;

[0044] For the second power line connected to the second drive circuit located in the first region, the second power segment and the fourth power segment are located in the first region and the third region, and the third power segment is located in the first region;

[0045] For the second power line connected to the second drive circuit located in the second region, the second power segment and the fourth power segment are located in the second region and the third region, and the third power segment is located in the second region.

[0046] In some possible implementations, the display panel further includes: a first power connection line and a second power connection line located in the non-display area; the first power connection line and the second power connection line are arranged on the same layer, and are arranged on the same layer as the second power line;

[0047] When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first power connection line is connected to both ends of at least one second power line located in the first area, and the second power connection line is connected to both ends of at least one second power line located in the second area.

[0048] When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the first power connection line is respectively connected to the first power segment and the fifth power segment of a second power line that is connected to the second driving circuit located in the first region; the second power connection line is respectively connected to the first power segment and the fifth power segment of a second power line that is connected to the second driving circuit located in the second region.

[0049] In some possible implementations, the display area includes: a first side and a second side that are arranged opposite to each other, and a third side and a fourth side that are arranged opposite to each other;

[0050] The first power connection cable includes: a first connection segment, a second connection segment, a third connection segment, a fourth connection segment, and a fifth connection segment connected in sequence; the first connection segment and the second connection segment are located on a first side of the display area, the third connection segment is located on a third side of the display area, and the fourth connection segment and the fifth connection segment are located on a second side of the display area; the first connection segment, the third connection segment, and the fifth connection segment extend along a second direction, and the second connection segment and the fourth connection segment extend along a first direction;

[0051] When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first connecting segment is connected to one end of at least one second power line located in the first region, and the fifth connecting part is connected to the other end of at least one second power line located in the first region.

[0052] When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the first connecting segment is connected to at least one first power segment of a second power line connected to a second driving circuit located in the first region, and the fifth connecting segment is connected to at least one fifth power segment of a second power line connected to a second driving circuit located in the first region.

[0053] In some possible implementations, the second power connection cable includes: a sixth connection segment, a seventh connection segment, an eighth connection segment, a ninth connection segment, and a tenth connection segment connected in sequence; the sixth connection segment and the seventh connection segment are located on a first side of the display area, the eighth connection segment is located on a fourth side of the display area, and the ninth connection segment and the tenth connection segment are located on a second side of the display area; the sixth connection segment, the eighth connection segment, and the tenth connection segment extend along a second direction, and the seventh connection segment and the ninth connection segment extend along a first direction;

[0054] When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting segment is connected to one end of at least one second power line located in the second region, and the tenth connecting part is connected to the other end of at least one second power line located in the second region.

[0055] When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the sixth connecting segment is connected to at least one first power segment of a second power line connected to a second driving circuit located in the second region, and the tenth connecting segment is connected to at least one fifth power segment of a second power line connected to a second driving circuit located in the second region.

[0056] In some possible implementations, the circuit structure layer includes: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer;

[0057] The first power line is located in the first conductive layer and / or the second conductive layer; the second power line and the first adapter are located in the third conductive layer; the second adapter is located in the fourth conductive layer;

[0058] The first conductive layer, the second conductive layer, and the third conductive layer are metallic conductive layers, and the fourth conductive layer is a transparent conductive layer.

[0059] In some possible implementations, the circuit structure layer includes: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer;

[0060] The first power line is located in the first conductive layer and / or the second conductive layer; the second power line, the first adapter, and the second adapter are located in the third conductive layer;

[0061] The first conductive layer and the second conductive layer are metallic conductive layers.

[0062] In some possible implementations, the first display area is a transparent display area;

[0063] The resolution of the first display area is the same as the resolution of the second display area, or the resolution of the first display area is different from the resolution of the second display area.

[0064] Secondly, this disclosure also provides a display device, including the aforementioned display panel.

[0065] In some possible implementations, a photosensor is also included, wherein the photosensor is located within a first display area of ​​the display panel.

[0066] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0067] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0068] Figure 1A A schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0069] Figure 1B This is another structural schematic diagram of the display panel provided in an embodiment of the present disclosure;

[0070] Figure 2A for Figure 1A A cross-sectional view of the provided display panel;

[0071] Figure 2B for Figure 1B A cross-sectional view of the provided display panel;

[0072] Figure 3 A schematic diagram of the arrangement of light-emitting elements in a display panel provided for an exemplary embodiment;

[0073] Figure 4 A schematic diagram of the arrangement of light-emitting elements in a display panel provided for another exemplary embodiment;

[0074] Figure 5 This is a schematic diagram of the equivalent circuit of a driving circuit.

[0075] Figure 6 This is a timing diagram of a driving circuit.

[0076] Figure 7 A size comparison diagram of a driving circuit and a reference driving circuit in a display panel, provided for an exemplary embodiment;

[0077] Figure 8A A schematic diagram of the structure of a display panel provided in an exemplary embodiment;

[0078] Figure 8B A schematic diagram of the structure of a display panel provided for another exemplary embodiment;

[0079] Figure 9 A cross-sectional view of a display panel provided for an exemplary embodiment;

[0080] Figure 10 A schematic diagram showing the arrangement of the first transition portions in each first sub-region, provided as an exemplary embodiment;

[0081] Figure 11 yes Figure 10 A magnified view of region R;

[0082] Figure 12A A schematic diagram of the structure of a display panel provided as yet another exemplary embodiment;

[0083] Figure 12B A schematic diagram of the structure of a display panel is provided for yet another exemplary embodiment;

[0084] Figure 13 A schematic diagram of the structure of a second power line provided for an exemplary embodiment;

[0085] Figure 14 A schematic diagram of the structure of a first power connection line provided for an exemplary embodiment;

[0086] Figure 15 A schematic diagram of the structure of a second power connection line provided for an exemplary embodiment. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0088] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0089] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0090] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0091] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0092] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0093] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0094] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0095] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0096] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0097] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0098] A display panel includes a transparent display area, but data signal lines need to be routed around the transparent display area, which increases the difficulty of routing the data signal lines.

[0099] Figure 1A This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure. Figure 1B This is another schematic diagram of the structure of the display panel provided in an embodiment of the present disclosure. Figure 2A for Figure 1A The provided cross-sectional view of the display panel. Figure 2B for Figure 1B A cross-sectional view of the provided display panel. As shown in Figures 1 and 2, the display panel provided in this embodiment may include: a display area AA and a non-display area (not shown) surrounding the display area. The display area AA includes: a first display area A1 and a second display area A2 located on at least one side of the first display area A1; the second display area A2 includes: a first region R1 and a second region R2 spaced apart, the first region R1 and the second region R2 arranged along a first direction D1, and the first display area A1 located between the first region R1 and the second region R2.

[0100] In one exemplary embodiment, the display panel may include a substrate 10 and a circuit structure layer 20 and a light-emitting structure layer 30 sequentially stacked on the substrate. The circuit structure layer may include multiple driving circuits PA and multiple data signal lines D extending along a second direction D2. The light-emitting structure layer may include multiple light-emitting elements. The data signal lines D are configured to provide data signals to the driving circuits PA, and the driving circuits PA are configured to drive the light-emitting elements to emit light. The first direction D1 and the second direction D2 intersect.

[0101] The light-emitting element is located in the first display area A1 and the second display area A2, and the driving circuit PA is located in the first area R1 and the second area R2.

[0102] In one exemplary embodiment, the substrate 10 may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and metal foil. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0103] In one exemplary embodiment, the display panel may further include: a timing controller, a data driving circuit, a scan driving circuit, and a light-emitting driving circuit located in the non-display area. The display panel may also include multiple scan signal lines and multiple light-emitting signal lines located in the display area.

[0104] In one exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driving circuit to the data driving circuit, provide clock signals, scan start signals, etc. of specifications suitable for the scan driving circuit to the scan driving circuit, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driving circuit to the light-emitting driving circuit.

[0105] In one exemplary embodiment, the data driving circuit may use grayscale values ​​and control signals received from a timing controller to generate a data voltage to be provided to the data signal line D. For example, the data driving circuit may use a clock signal to sample the grayscale values ​​and apply the data voltage corresponding to the grayscale values ​​to the data signal line on a pixel-by-pixel basis.

[0106] In one exemplary embodiment, the scan driver circuit can generate scan signals to be provided to the scan signal lines by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan driver circuit can sequentially provide scan signals with on-level pulses to the scan signal lines. The scan driver circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal.

[0107] In one exemplary embodiment, the light-emitting driving circuit can generate a transmit signal to be provided to the light-emitting signal line by receiving a clock signal, a transmit stop signal, etc., from a timing controller. The light-emitting driving circuit can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines. For example, the light-emitting driving circuit can be configured as a shift register and can generate the light-emitting signal by sequentially transmitting the transmit stop signal in the form of cutoff level pulses to the next stage circuit under the control of a clock signal. Each sub-pixel can be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light-emitting signal line.

[0108] In one exemplary embodiment, the intersection of the first direction and the second direction means that the angle between the first direction and the second direction is approximately 70 to 90 degrees. The first direction and the second direction may lie in the same plane. For example, the first direction may be a direction parallel to the extension direction of the scan signal line; the second direction may be a direction parallel to the extension direction of the data signal line. Figure 1 illustrates an example where the angle between the first direction and the second direction is 90 degrees.

[0109] In one exemplary embodiment, the shape of the light-emitting element can be any one or more of the following: triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons, without limitation herein.

[0110] In one exemplary embodiment, Figure 3 This is a schematic diagram of the arrangement of light-emitting elements in a display panel provided for an exemplary embodiment. Figure 4 A schematic diagram showing the arrangement of light-emitting elements in a display panel, provided for another exemplary embodiment. (See diagram below.) Figure 3 and Figure 4As shown, the light-emitting element can be any one of a red (R) light-emitting element, a green (G) light-emitting element, a blue (B) light-emitting element, or a white light-emitting element, and this disclosure does not limit this. When the display panel includes a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element, the three light-emitting elements can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement. When the display panel includes a red (R) light-emitting element, a green (G) light-emitting element, a blue (B) light-emitting element, and a white light-emitting element, the four light-emitting elements can be arranged horizontally side by side, vertically side by side, or in an array, and this disclosure does not limit this. Figure 3 This explanation uses the example of three light-emitting elements arranged horizontally side by side. Figure 4 This explanation uses an array of four light-emitting elements as an example.

[0111] In one exemplary embodiment, the area of ​​each driving circuit can be the same, ensuring that the load of each driving circuit is the same, which can largely avoid the risk of abnormal display.

[0112] In some exemplary embodiments, the display area includes an arc-shaped display boundary. Exemplarily, the boundary of the display area may be a rounded rectangle, and this disclosure does not limit it in any way.

[0113] In one exemplary embodiment, the first display area may be a light-transmitting display area. The light-transmitting display area can both display and transmit light.

[0114] In one exemplary embodiment, the shape of the first display area in a plane parallel to the display panel can be any one or more of the following: rectangle, polygon, circle, and ellipse. Figure 1 illustrates this using a rectangle as an example.

[0115] In one exemplary embodiment, the area of ​​the first display area may be greater than the area of ​​the second display area, or the area of ​​the first display area may be equal to the area of ​​the second display area, or the area of ​​the first display area may be less than the area of ​​the second display area. FIG1 is illustrated with the example of the area of ​​the first display area being less than the area of ​​the second display area.

[0116] In one exemplary embodiment, the resolutions of the first display area and the second display area may be the same or different. Resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates that the display panel displays the image at a higher density, resulting in richer image detail.

[0117] In one exemplary embodiment, the resolution of the second display area may be greater than that of the first display area, that is, the number of light-emitting elements included in the second display area per unit area is greater than that of the first display area; or, the resolution of the second display area may be less than that of the first display area, that is, the number of light-emitting elements included in the second display area per unit area is less than that of the first display area; or, the resolution of the second display area may be equal to that of the first display area, that is, the number of light-emitting elements included in the second display area per unit area is equal to that of the first display area.

[0118] In one exemplary embodiment, the boundary of the display area AA may include at least one arc segment. For example, as shown in FIG1, the shape of the display area AA may be a rounded rectangle, and this disclosure does not limit it in any way.

[0119] In one exemplary embodiment, the driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 This is a schematic diagram of the equivalent circuit of a driving circuit. For example... Figure 5 As shown, the driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, high-level power supply line VDD, and low-level power supply line VSS).

[0120] In one exemplary embodiment, the first end of the storage capacitor C is connected to the high-level power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0121] In one exemplary embodiment, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When a conduction level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge on the control electrode of the third transistor T3.

[0122] In one exemplary embodiment, the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a pass-through scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0123] In one exemplary embodiment, the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor. The third transistor T3 determines the amount of driving current flowing between the high-level power line VDD and the low-level power line VSS based on the potential difference between its control electrode and its first electrode.

[0124] In one exemplary embodiment, the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the driving circuit.

[0125] In one exemplary embodiment, the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the high-level power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting element to emit light by forming a drive current path between the high-level power supply line VDD and the low-level power supply line VSS.

[0126] In one exemplary embodiment, the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting element. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the anode of the light-emitting element to initialize or release the charge accumulated in the first electrode of the light-emitting element and the charge accumulated in the anode of the light-emitting element.

[0127] In one exemplary embodiment, the cathode of the light-emitting element is connected to a low-level power line VSS, where the signal of the low-level power line VSS is a low-level signal, and the signal of the high-level power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the current display row driving circuit, and the second scan signal line S2 is the scan signal line in the previous display row driving circuit. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the previous display row driving circuit are the same signal line, which can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.

[0128] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors. When a low level is applied to the gate electrode of the P-type transistor, the P-type transistor is turned on; when a high level is applied to the gate electrode of the P-type transistor, the P-type transistor is turned off. These two levels are typically used to turn the transistor on and off respectively; therefore, the higher of the two is usually referred to as the high level, and the lower one as the low level.

[0129] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. In an exemplary embodiment, LTPS and oxide thin-film transistors can be integrated onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate. This leverages the advantages of both, enabling high resolution (Pixels Per Inch, PPI), low-frequency driving, reduced power consumption, and improved display quality.

[0130] In one exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT extend along a first direction, while the low-level power supply line VSS, the high-level power supply line VDD, and the data signal line D extend along a second direction.

[0131] In one exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. The anode is connected to a driving circuit via a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode.

[0132] In one exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0133] In one exemplary embodiment, the anode may be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0134] In one exemplary embodiment, the cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the aforementioned metals.

[0135] Figure 6 This is a timing diagram of a driving circuit. The following is a demonstration of its operation. Figure 5 The operation of the example drive circuit illustrates an exemplary embodiment of this disclosure. Figure 6The driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, high-level power supply line VDD, and low-level power supply line VSS). All 7 transistors are P-type transistors.

[0136] In one exemplary embodiment, the operation of the driving circuit may include:

[0137] The first stage, called the reset stage, involves a low-level signal on the second scan signal line S2, and high-level signals on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage within it. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0138] The second stage, also known as the data writing stage or threshold compensation stage, involves a low-level signal on the first scan signal line S1, while the signals on the second scan signal line S2 and the light-emitting signal line E are high-level. The data signal line D outputs a data voltage. During this stage, the second terminal of the storage capacitor C is low, causing the third transistor T3 to conduct. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the conducting third transistor T3, the third node N3, and the conducting second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0139] The third stage, known as the light-emitting stage, involves a low-level signal on the light-emitting signal line E, while the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the high-level power supply line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0140] During the driving process of the driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0141] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0142] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0143] The display panel provided in this embodiment includes: a display area and a non-display area surrounding the display area. The display area includes: a first display area and a second display area located on at least one side of the first display area; the second display area includes: a first region and a second region spaced apart, the first region and the second region being arranged along a first direction, and the first display area being located between the first region and the second region; the display panel includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending along a second direction; the light-emitting structure layer includes: a plurality of light-emitting elements; the data signal lines are configured to provide data signals to the driving circuits, the driving circuits are configured to drive the light-emitting elements to emit light, and the first direction and the second direction intersect; the light-emitting elements are located in the first display area and the second display area, and the driving circuits are located in the first region and the second region. By placing the driving circuits in the first region and the second region, this embodiment simplifies the layout of the data signal lines, as the data signal lines do not need to avoid the first display area.

[0144] In one exemplary embodiment, the length of the first display area A1 along the second direction D2 is less than or equal to the length of the second display area A2 along the second direction D2. Figure 1A and Figure 2A This explanation is based on the example that the length of the first display area A1 along the second direction D2 is less than the length of the second display area A2 along the second direction D2. Figure 1B and Figure 2B This explanation is based on the example that the length of the first display area A1 along the second direction D2 is equal to the length of the second display area A2 along the second direction D2.

[0145] In one exemplary embodiment, the length of any driving circuit along the first direction is less than the length of the light-emitting element connected to the driving circuit along the first direction.

[0146] In one exemplary embodiment, Figure 7 This is a size comparison diagram of a driving circuit and a reference driving circuit in a display panel, provided for an exemplary embodiment. The reference driving circuit CPA refers to the driving circuit in the display panel located in all areas of the second display area. The driving circuit in the display panel provided in an exemplary embodiment is obtained by proportionally compressing the reference driving circuit CPA. This proportional compression may include: proportional compression along a first direction or proportional compression along both row and column directions. Figure 7 As shown, l3 = l1 × k, l4 = l2. Where l1 is the length of the reference driving circuit CPA along the first direction, l2 is the length of the reference driving circuit CPA along the second direction, l3 is the length of the driving circuit PA along the first direction, l4 is the length of the driving circuit PA along the second direction, k is the compression ratio, and 0 <k<1。

[0147] In one exemplary embodiment, the length of the light-emitting element along the first direction is X micrometers, and the length of the driving circuit along the first direction is Xa micrometers, wherein the value of a is determined according to the size of the first display area.

[0148] In one exemplary embodiment, Figure 8A A schematic diagram of the structure of a display panel provided in an exemplary embodiment. Figure 8B A schematic diagram of the structure of a display panel is provided for another exemplary embodiment. As shown in FIG8, the driving circuit may include: a first driving circuit PA1 and a second driving circuit PA2. The first driving circuit PA1 is connected to a first light-emitting element, and the second driving circuit PA2 is connected to a second light-emitting element. The first light-emitting element is located in the second display area, and the second light-emitting element is located in the first display area. Figure 8A This explanation is based on the example that the length of the first display area A1 along the second direction D2 is less than the length of the second display area A2 along the second direction D2. Figure 8B This explanation is based on the example that the length of the first display area A1 along the second direction D2 is equal to the length of the second display area A2 along the second direction D2.

[0149] In one exemplary embodiment, Figure 9 A cross-sectional view of a display panel provided for an exemplary embodiment. Figure 9 As shown, the orthographic projection of the second electrode 64 of the sixth transistor T6 of the driving circuit onto the substrate 10 does not overlap with the orthographic projection of the anode 31 of the light-emitting element connected to the driving circuit onto the substrate 10.

[0150] In one exemplary embodiment, the circuit structure layer 20 may further include: an active layer 61, a gate electrode 62, and a first electrode 63 of the sixth transistor T6, a first plate C1 and a second plate C2 of a storage capacitor, and a high-level power supply line VDD.

[0151] In one exemplary embodiment, the light-emitting structure layer 30 may further include: a pixel defining layer 34, an organic light-emitting layer 32, and a cathode 33.

[0152] In one exemplary embodiment, the pixel defining layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.

[0153] In one exemplary embodiment, such as Figure 9 As shown, the circuit structure layer 20 also includes a plurality of first transition sections VL1, which are located between the second electrode 61 of the sixth transistor of the first driving circuit and the anode 31 of the first light-emitting element.

[0154] In one exemplary embodiment, the first driving circuit is connected to the first light-emitting element via a first adapter portion. The orthographic projection of the first adapter portion on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the first driving circuit connected to the first adapter portion on the substrate, and the orthographic projection of the anode of the first light-emitting element connected to the first connection portion on the substrate at least partially overlaps with the orthographic projection of the anode of the first light-emitting element connected to the first connection portion on the substrate.

[0155] In one exemplary embodiment, the material used to manufacture the first adapter may include metal. Using metal as the material for the first adapter can reduce impedance and ensure uniform brightness in the second display area.

[0156] In one exemplary embodiment, the circuit structure layer may further include: a plurality of second transition portions, the second transition portions being located between the second electrode of the sixth transistor of the second driving circuit and the anode of the second light-emitting element.

[0157] In one exemplary embodiment, the second driving circuit is connected to the second light-emitting element via a second adapter portion. The orthographic projection of the second adapter portion on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the second driving circuit connected to the second adapter portion on the substrate, and at least partially overlaps with the orthographic projection of the anode of the second light-emitting element connected to the second connection portion on the substrate.

[0158] In one exemplary embodiment, the second adapter is made of a transparent conductive material. Using a transparent conductive material to manufacture the second adapter ensures the light transmittance of the second display area.

[0159] In one exemplary embodiment, the second adapter is disposed on the same layer as the first adapter, or on a different layer; this disclosure does not limit this.

[0160] In one exemplary embodiment, such as Figure 1A and Figure 2A As shown, when the length of the first display area A1 along the second direction is less than the length of the second display area A2 along the second direction, the second display area A2 may further include: a third area R3, the third area R3 is located between the first area R1 and the second area R2, and the third area R3 surrounds the first display area A1.

[0161] In one exemplary embodiment, the first region R1 and the second region R2 are symmetrically arranged along the midline of the third region R3.

[0162] In one exemplary embodiment, such as Figure 2A and Figure 8A As shown, the circuit structure layer may further include: N columns of first dummy driving circuits DPA1. These N columns of first dummy driving circuits are located in the third region R3, where N is a positive integer greater than or equal to M, and M is the number of columns of light-emitting elements in the first display area.

[0163] In one exemplary embodiment, each column of the first dummy driving circuit is not connected to any light-emitting element. This disclosure, by setting the first dummy driving circuit, can ensure the uniformity of the driving circuit's display, thereby improving the display effect of the display panel. The value of N can be determined based on the size of the first display area in the display panel, and this disclosure does not impose any limitations on it.

[0164] In one exemplary embodiment, the length of the first dummy driving circuit along the first direction is greater than or equal to the length of the driving circuit along the first direction. For example, the length of the first dummy driving circuit along the first direction is equal to the length of the driving circuit along the first direction. Having the length of the first dummy driving circuit equal to the length of the driving circuit along the first direction simplifies the manufacturing process of the display panel and saves on manufacturing costs.

[0165] In one exemplary embodiment, such as Figure 8A and Figure 8B As shown, the first region includes S first sub-regions R1_1 to R1_S arranged sequentially along the first direction, wherein adjacent first sub-regions are spaced apart, and S is a positive integer greater than or equal to 2. Figure 8 illustrates this with S=3 as an example.

[0166] In one exemplary embodiment, each first sub-region may include the same number of columns of driving circuits.

[0167] In one exemplary embodiment, Figure 10 A schematic diagram of the arrangement of the first transition portions in each first sub-region provided as an exemplary embodiment. Figure 11 yes Figure 10 An enlarged view of region R is shown in Figure 8. Figure 10 and Figure 11 As shown, the circuit structure layer may further include: at least one column of second dummy drive circuits DPA2 located between adjacent first sub-regions.

[0168] In one exemplary embodiment, each column of second dummy driving circuits is not connected to any light-emitting element. This disclosure, by setting second dummy driving circuits between adjacent first sub-regions, can better maintain the uniformity of the offset between the driving circuits and the light-emitting elements connected to them, ensuring the uniformity of the display panel and improving the display effect. Each first sub-region and its adjacent second dummy driving circuit can form a loop unit. All first transition sections in each loop unit have the same size and arrangement, which not only simplifies the manufacturing process of the display panel but also facilitates the implementation of the first transition sections, avoiding excessively long first transition sections.

[0169] In one exemplary embodiment, such as Figure 8A and Figure 8B As shown, the second region R2 includes T second sub-regions R2_1 to R2_T arranged sequentially along the first direction, wherein adjacent second sub-regions are spaced apart, and T is a positive integer greater than or equal to 2. Figure 8 illustrates this with T=3 as an example.

[0170] In some possible implementations, the circuit structure layer also includes at least one column of third dummy driver circuits DPA3 located between adjacent second sub-regions.

[0171] In one exemplary embodiment, each column of third dummy driving circuits is not connected to any light-emitting element. This disclosure, by setting third dummy driving circuits between adjacent first sub-regions, can better maintain the uniformity of the offset between the driving circuits and the light-emitting elements connected to them, thus ensuring the uniformity of the display panel and improving the display effect. (Refer to...) Figure 10 and Figure 11 Each second sub-region and the adjacent third dummy driving circuit can be used as a loop unit. All the first transition parts in each loop unit have the same size and arrangement. This not only simplifies the manufacturing process of the display panel, but also facilitates the realization of the first transition part and avoids the first transition part being too long.

[0172] In one exemplary embodiment, S = T.

[0173] In one exemplary embodiment, as shown in FIG1, the data signal line D can be located in a first region R1 and a second region R2. Drive circuits located in the same column are connected to the same data signal line.

[0174] In one exemplary embodiment, Figure 12A A schematic diagram of the structure of a display panel is provided as yet another exemplary embodiment. Figure 12B A schematic diagram of the structure of a display panel provided for yet another exemplary embodiment. (See diagram below.) Figure 12A and Figure 12B As shown, the circuit structure layer also includes: multiple first power lines VDD1 extending along the second direction; the first power lines VDD1 are located in the first region R1 and the second region R2. Figure 12A and Figure 12B This explanation is based on the example of S=2 and T=2. Figure 12A This explanation is based on the example where the length of the first display area along the second direction is less than the length of the second display area along the second direction. Figure 12B This explanation is based on the example where the length of the first display area along the second direction is equal to the length of the second display area along the second direction.

[0175] In one exemplary embodiment, when all the driving circuits in the same column are first driving circuits, the first driving circuits in the same column are connected to the same first power line. When the driving circuits in the same column include a first driving circuit and a second driving circuit, the first driving circuits located on both sides of the second driving circuit are connected to different first power lines.

[0176] In one exemplary embodiment, the first power line is a high-level power line connected to the first driving circuit.

[0177] In one exemplary embodiment, as shown in FIG12, the circuit structure layer may further include: a plurality of second power lines VDD2; the second power lines VDD2 are located on the side of the first power line VDD1 away from the substrate 10.

[0178] In one exemplary embodiment, the second power line VDD2 is a high-level power line connected to the second drive circuit.

[0179] In one exemplary embodiment, such as Figure 12A and Figure 12B As shown, the second drive circuits located in the same column are connected to the same second power supply line.

[0180] In one exemplary embodiment, the voltage value of the signal on the second power line VDD2 is greater than the voltage value of the signal on the first power line VDD1.

[0181] In one exemplary embodiment, the second driving circuit is connected to the second light-emitting element through a second adapter. The second adapter is made of a transparent conductive material. Since the transparent conductive material has a large resistance, it may cause uneven display of the first light-emitting element and the second light-emitting element. This disclosure connects the second driving circuit to the second power line, which can adjust the brightness of the light-emitting element in the first display area to compensate for the brightness of the light-emitting element in the first display area. This can achieve uniformity of display panel display and improve the display effect of display panel.

[0182] In one exemplary embodiment, such as Figure 12B As shown, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the second power line is located in the first region R1 and the second region, and extends along the second direction.

[0183] In one exemplary embodiment, Figure 13 A schematic diagram of the structure of a second power line provided for an exemplary embodiment. (See diagram below.) Figure 12A and Figure 13 As shown, when the length of the first display area along the second direction is less than the length of the second display area along the second direction, each second power line includes: a first power segment Va, a second power segment Vb, a third power segment Vc, a fourth power segment Vd, and a fifth power segment Ve connected in sequence; the first power segment Va, the third power segment Vc, and the fifth power segment Ve extend along the second direction, and the second power segment Vb and the fourth power segment Vd extend along the first direction.

[0184] In one exemplary embodiment, for each second power line, the first power segment Va and the fifth power segment Ve are located in the third region.

[0185] In one exemplary embodiment, for a second power line connected to a second drive circuit located in a first region, a second power segment Vb and a fourth power segment Vd are located in a third region and a first region, and a third power segment Vc is located in the first region.

[0186] In one exemplary embodiment, for a second power supply line connected to a second drive circuit located in a second region, a second power supply segment Vb and a fourth power supply segment Vd are located in the second region and a third region, respectively, and a third power supply segment Vc is located in the second region.

[0187] In one exemplary embodiment, Figure 14 A schematic diagram of the structure of a first power connection line provided in an exemplary embodiment. Figure 15 A schematic diagram of the structure of a second power connection line provided for an exemplary embodiment. As shown in Figures 12, 14, and 15, the display panel may further include: a first power connection line L1 and a second power connection line L2 located in the non-display area.

[0188] In one exemplary embodiment, the first power connection line L1 and the second power connection line L2 can be arranged on the same layer, and are arranged on the same layer as the second power line.

[0189] In one exemplary embodiment, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first power connection line L1 is connected to both ends of at least one second power line located in the first region, and the second power connection line L2 is connected to both ends of at least one second power line located in the second region.

[0190] In one exemplary embodiment, the first power connection line L1 may be respectively connected to a first power segment and a fifth power segment of at least one second power line connected to a second drive circuit located in the first region. The second power connection line L2 is respectively connected to the first power segment and the fifth power segment of at least one second power line connected to a second drive circuit located in the second region.

[0191] In one exemplary embodiment, the display area includes: a first side and a second side that are arranged opposite to each other, and a third side and a fourth side that are arranged opposite to each other.

[0192] In one exemplary embodiment, such as Figure 14 As shown, the first power connection line L1 includes: a first connection segment La, a second connection segment Lb, a third connection segment Lc, a fourth connection segment Ld, and a fifth connection segment Le connected in sequence.

[0193] In one exemplary embodiment, the first connecting segment La and the second connecting segment Lb are located on the first side of the display area, the third connecting segment Lc is located on the third side of the display area, and the fourth connecting segment Ld and the fifth connecting segment Le are located on the second side of the display area.

[0194] In one exemplary embodiment, the first connecting segment La, the third connecting segment Lc, and the fifth connecting segment Le extend along a second direction, and the second connecting segment Lb and the fourth connecting segment Ld extend along a first direction.

[0195] In one exemplary embodiment, such as Figure 12B As shown, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first connecting segment connects to one end of at least one second power line located in the first area, and the fifth connecting part connects to the other end of at least one second power line located in the first area.

[0196] In one exemplary embodiment, when the length of the first display area along the second direction is less than the length of the second display area along the second direction, the first connecting segment La connects to at least one first power segment of a second power line connected to a second driving circuit located in the first region, and the fifth connecting segment Le connects to at least one fifth power segment of a second power line connected to a second driving circuit located in the first region.

[0197] In one exemplary embodiment, such as Figure 15 As shown, the second power connection line includes: the sixth connection segment Lf, the seventh connection segment Lg, the eighth connection segment Lh, the ninth connection segment Li, and the tenth connection segment Lj connected in sequence.

[0198] In one exemplary embodiment, the sixth connecting segment Lf and the seventh connecting segment Lg are located on the first side of the display area, the eighth connecting segment Lh is located on the fourth side of the display area, and the ninth connecting segment Li and the tenth connecting segment Lj are located on the second side of the display area.

[0199] In one exemplary embodiment, the sixth connecting segment Lf, the eighth connecting segment Lh, and the tenth connecting segment Lj extend along a second direction, while the seventh connecting segment Lg and the ninth connecting segment Li extend along a first direction.

[0200] When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting segment connects to one end of at least one second power line located in the second area, and the tenth connecting part connects to the other end of at least one second power line located in the second area.

[0201] In one exemplary embodiment, when the length of the first display area along the second direction is less than the length of the second display area along the second direction, the sixth connection segment Lf connects to the first power segment of at least one second power line connected to the second driving circuit located in the second region, and the tenth connection segment Lj connects to the fifth power segment of at least one second power line connected to the second driving circuit located in the second region.

[0202] In one exemplary embodiment, the circuit structure layer may include: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer. A first power line is located on the first conductive layer and / or the second conductive layer; a second power line and a first transition portion are located on the third conductive layer; and a second transition portion is located on the fourth conductive layer.

[0203] In one exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer may be metal conductive layers.

[0204] In one exemplary embodiment, the fourth conductive layer may be a transparent conductive layer.

[0205] In an exemplary embodiment, when the circuit structure layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer, the circuit structure layer may further include a buffer layer, an active layer, a fourth insulating layer, a first metal layer, a fifth insulating layer, a second metal layer, and a sixth insulating layer disposed between the substrate and the first conductive layer and sequentially stacked on the substrate.

[0206] In one exemplary embodiment, the active layer may include: an active layer of multiple transistors; the first metal layer may include: gate electrodes of the multiple transistors and a first electrode of a storage capacitor; the second metal layer may include: a second electrode of the multiple transistors; and the conductive layer may further include: a first electrode and a second electrode of the multiple transistors.

[0207] In one exemplary embodiment, the circuit structure layer may further include a flat layer disposed on the side of the fourth conductive layer away from the substrate.

[0208] In one exemplary embodiment, such as Figure 9 As shown, the circuit structure layer may further include: a first conductive layer, a first insulating layer 26, a second conductive layer, a second insulating layer 27, and a third conductive layer. The first power line VDD1 is located in the first conductive layer and / or the second conductive layer; the second power line, the first adapter VL1, and the second adapter are located in the third conductive layer.

[0209] In one exemplary embodiment, the first conductive layer and the second conductive layer are metallic conductive layers.

[0210] In one exemplary embodiment, the circuit structure layer may further include: a buffer layer 22, an active layer, a third insulating layer 23, a first metal layer, a fourth insulating layer 24, a second metal layer, and a fifth insulating layer 25 disposed between the substrate and the first conductive layer and sequentially stacked on the substrate 10.

[0211] In one exemplary embodiment, the active layer may include: an active layer of multiple transistors; the first metal layer may include: the gate electrode of the multiple transistors and the first electrode C1 of the storage capacitor; the second metal layer may include: the second electrode C2 of the multiple transistors.

[0212] In one exemplary embodiment, the first conductive layer may further include: a first electrode and a second electrode of a plurality of transistors.

[0213] In one exemplary embodiment, the circuit structure layer may further include a planar layer 28 disposed on the side of the third conductive layer away from the substrate.

[0214] In one exemplary embodiment, the active layer may be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0215] In one exemplary embodiment, the first metal layer, the second metal layer, the first conductive layer, and the second conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0216] In one exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0217] In one exemplary embodiment, the planarization layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.

[0218] In one exemplary embodiment, such as Figure 9 As shown, the display panel may also include an encapsulation layer 40 and a spacer 50.

[0219] In one exemplary embodiment, the encapsulation layer 40 is disposed on the side of the light-emitting structure layer 30 away from the substrate 10, and the spacer 50 is disposed on the side of the encapsulation layer 40 away from the substrate 10.

[0220] In one exemplary embodiment, the encapsulation layer 40 may employ a stacked structure of inorganic material / organic material / inorganic material, with the organic material layer disposed between the two inorganic material layers. Exemplarily, the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting device.

[0221] This disclosure also provides a display device, including a display panel.

[0222] In one exemplary embodiment, the display device can be any product or component with display functionality, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, or a monitor. The accompanying drawings in this disclosure only illustrate the structures relevant to the embodiments of this disclosure; other structures can be referred to in general design.

[0223] The display panel is any of the display panels provided in the aforementioned embodiments, and the implementation principle and effect are similar, so they will not be described again here.

[0224] In one exemplary embodiment, the display device may further include a photosensor located within a first display area of ​​the display panel.

[0225] In one exemplary embodiment, the first display area can be rectangular, and the area of ​​the orthographic projection of the photosensitive sensor onto the substrate can be less than or equal to the area of ​​the inscribed circle of the first display area. That is, the size of the area where the photosensitive sensor is located can be less than or equal to the size of the inscribed circle of the first display area. For example, the size of the area where the photosensitive sensor is located is equal to the size of the inscribed circle of the first display area, meaning the shape of the area where the photosensitive sensor is located can be circular, and correspondingly, the area where the photosensitive sensor is located can also be referred to as a light-transmitting hole.

[0226] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0227] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, comprising: The display area and the non-display area surrounding the display area are characterized in that the display area includes: a first display area and a second display area located on at least one side of the first display area; the second display area includes: a first region and a second region spaced apart, the first region and the second region being arranged along a first direction, and the first display area being located between the first region and the second region; The display panel includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending along a second direction; the light-emitting structure layer includes: a plurality of light-emitting elements; the data signal lines are configured to provide data signals to the driving circuits, the driving circuits are configured to drive the light-emitting elements to emit light, and the first direction and the second direction intersect; The light-emitting element is located in the first display area and the second display area, and the driving circuit is located in the first area and the second area; the data signal line is located in the first area and the second area, and the area of ​​the display panel other than the first area and the second area is not provided with driving circuit and data signal line.

2. The display panel according to claim 1, characterized in that, The length of the first display area along the second direction is less than or equal to the length of the second display area along the second direction.

3. The display panel according to claim 1 or 2, characterized in that, The length of the driving circuit along the first direction is less than the length of the light-emitting element connected to the driving circuit along the first direction.

4. The display panel according to claim 3, characterized in that, The driving circuit includes: a first driving circuit and a second driving circuit; The first driving circuit is connected to the first light-emitting element, and the second driving circuit is connected to the second light-emitting element. The first light-emitting element is located in the second display area, and the second light-emitting element is located in the first display area.

5. The display panel according to claim 4, characterized in that, The driving circuit includes: a first transistor to a seventh transistor; the light-emitting element includes: an anode, an organic light-emitting layer, and a cathode; the second terminal of the sixth transistor of the driving circuit is connected to the anode of the light-emitting element; The orthographic projection of the second electrode of the sixth transistor of the driving circuit onto the substrate does not overlap with the orthographic projection of the anode of the light-emitting element connected to the driving circuit onto the substrate.

6. The display panel according to claim 5, characterized in that, The circuit structure layer further includes: a plurality of first transition sections, wherein the first transition sections are located between the second electrode of the sixth transistor of the first driving circuit and the anode of the first light-emitting element; The first driving circuit is connected to the first light-emitting element through the first adapter. The orthographic projection of the first adapter on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the first driving circuit connected to the first adapter on the substrate, and at least partially overlaps with the orthographic projection of the anode of the first light-emitting element connected to the first connection on the substrate. The materials used to manufacture the first adapter include: metal.

7. The display panel according to claim 6, characterized in that, The circuit structure layer further includes: a plurality of second transition sections, wherein the second transition sections are located between the second electrode of the sixth transistor of the second driving circuit and the anode of the second light-emitting element; The second driving circuit is connected to the second light-emitting element through the second adapter. The orthographic projection of the second adapter on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the second driving circuit connected to the second adapter on the substrate, and at least partially overlaps with the orthographic projection of the anode of the second light-emitting element connected to the second connection on the substrate. The materials used to manufacture the second adapter include: transparent conductive material.

8. The display panel according to claim 7, characterized in that, The second adapter section can be located on the same layer as the first adapter section, or on a different layer.

9. The display panel according to claim 7, characterized in that, When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the second display area further includes: a third region, the third region being located between the first region and the second region, and the third region surrounding the first display area; The first region and the second region are symmetrically arranged along the centerline of the third region.

10. The display panel according to claim 9, characterized in that, The circuit structure layer also includes: N columns of first virtual driving circuits; The N columns of the first dummy driving circuits are located in the third region, where N is a positive integer greater than or equal to M, and M is the number of columns of light-emitting elements in the first display area; The length of the first dummy driving circuit along the first direction is greater than or equal to the length of the driving circuit along the first direction.

11. The display panel according to claim 2, characterized in that, The first region includes: S first sub-regions arranged sequentially along a first direction; The interval between adjacent first sub-regions is set.

12. The display panel according to claim 11, characterized in that, The circuit structure layer further includes at least one column of second dummy driving circuits located between adjacent first sub-regions.

13. The display panel according to claim 2, characterized in that, The second region includes: T second sub-regions arranged sequentially along the first direction; The interval between adjacent second sub-regions is set.

14. The display panel according to claim 13, characterized in that, The circuit structure layer also includes at least one column of third dummy driving circuits located between adjacent second sub-regions.

15. The display panel according to claim 13, characterized in that, S=T.

16. The display panel according to claim 2, characterized in that, The drive circuits located in the same column are connected to the same data signal line.

17. The display panel according to claim 9, characterized in that, The circuit structure layer further includes: multiple first power lines extending along a second direction; the first power lines are located in the first region and the second region; When all the drive circuits in the same column are first drive circuits, the first drive circuits in the same column are connected to the same first power line. When the drive circuits in the same column include a first drive circuit and a second drive circuit, the first drive circuits located on both sides of the second drive circuit are connected to different first power lines.

18. The display panel according to claim 17, characterized in that, The circuit structure layer further includes: multiple second power lines; the second power lines are located on the side of the first power lines away from the substrate; The second drive circuits located in the same column are connected to the same second power supply line; The voltage value of the signal on the second power line is greater than the voltage value of the signal on the first power line.

19. The display panel according to claim 18, characterized in that, When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the second power line is located in the first area and the second area, and extends along the second direction.

20. The display panel according to claim 18, characterized in that, When the length of the first display area along the second direction is less than the length of the second display area along the second direction, each second power line includes: a first power segment, a second power segment, a third power segment, a fourth power segment, and a fifth power segment connected in sequence; the first power segment, the third power segment, and the fifth power segment extend along the second direction, and the second power segment and the fourth power segment extend along the first direction; For each second power line, the first power segment and the fifth power segment are located in the third region; For the second power line connected to the second drive circuit located in the first region, the second power segment and the fourth power segment are located in the first region and the third region, and the third power segment is located in the first region; For the second power line connected to the second drive circuit located in the second region, the second power segment and the fourth power segment are located in the second region and the third region, and the third power segment is located in the second region.

21. The display panel according to claim 19 or 20, characterized in that, The display panel further includes: a first power connection line and a second power connection line located in the non-display area; the first power connection line and the second power connection line are arranged on the same layer, and are arranged on the same layer as the second power line; When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first power connection line is connected to both ends of at least one second power line located in the first area, and the second power connection line is connected to both ends of at least one second power line located in the second area. When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the first power connection line is respectively connected to the first power segment and the fifth power segment of a second power line that is connected to the second driving circuit located in the first region; the second power connection line is respectively connected to the first power segment and the fifth power segment of a second power line that is connected to the second driving circuit located in the second region.

22. The display panel according to claim 21, characterized in that, The display area includes: a first side and a second side arranged opposite to each other, and a third side and a fourth side arranged opposite to each other; The first power connection cable includes: a first connection segment, a second connection segment, a third connection segment, a fourth connection segment, and a fifth connection segment connected in sequence; the first connection segment and the second connection segment are located on a first side of the display area, the third connection segment is located on a third side of the display area, and the fourth connection segment and the fifth connection segment are located on a second side of the display area; the first connection segment, the third connection segment, and the fifth connection segment extend along a second direction, and the second connection segment and the fourth connection segment extend along a first direction; When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first connecting segment is connected to one end of at least one second power line located in the first area, and the fifth connecting segment is connected to the other end of at least one second power line located in the first area. When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the first connecting segment is connected to at least one first power segment of a second power line connected to a second driving circuit located in the first region, and the fifth connecting segment is connected to at least one fifth power segment of a second power line connected to a second driving circuit located in the first region.

23. The display panel according to claim 21, characterized in that, The second power connection cable includes a sixth connection segment, a seventh connection segment, an eighth connection segment, a ninth connection segment, and a tenth connection segment connected in sequence; the sixth connection segment and the seventh connection segment are located on the first side of the display area, the eighth connection segment is located on the fourth side of the display area, and the ninth connection segment and the tenth connection segment are located on the second side of the display area; the sixth connection segment, the eighth connection segment, and the tenth connection segment extend along the second direction, and the seventh connection segment and the ninth connection segment extend along the first direction; When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting segment is connected to one end of at least one second power line located in the second region, and the tenth connecting segment is connected to the other end of at least one second power line located in the second region. When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the sixth connecting segment is connected to at least one first power segment of a second power line connected to a second driving circuit located in the second region, and the tenth connecting segment is connected to at least one fifth power segment of a second power line connected to a second driving circuit located in the second region.

24. The display panel according to claim 21, characterized in that, The circuit structure layer includes: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer; The first power line is located in the first conductive layer and / or the second conductive layer; the second power line and the first adapter are located in the third conductive layer; the second adapter is located in the fourth conductive layer; The first conductive layer, the second conductive layer, and the third conductive layer are metallic conductive layers, and the fourth conductive layer is a transparent conductive layer.

25. The display panel according to claim 21, characterized in that, The circuit structure layer includes: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer; The first power line is located in the first conductive layer and / or the second conductive layer; the second power line, the first adapter, and the second adapter are located in the third conductive layer; The first conductive layer and the second conductive layer are metallic conductive layers.

26. The display panel according to claim 1, characterized in that, The first display area is a transparent display area; The resolution of the first display area is the same as the resolution of the second display area, or the resolution of the first display area is different from the resolution of the second display area.

27. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 26.

28. The display device according to claim 27, characterized in that, Also includes: A photosensor is provided, and the photosensor is located within the first display area of ​​the display panel.

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