Scalable mps devices based on sic

Abstract

Embodiments of the present disclosure relate to scalable SiC-based MPS devices. A merged PiN Schottky MPS device includes a SiC substrate having a first conductivity; a SiC drift layer having the first conductivity on the substrate; an implanted region having a second conductivity extending at a top surface of the drift layer to form a junction barrier JB diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diodes and the Schottky diodes alternate with each other along an axis: a minimum width of the JB diodes parallel to the axis is a first value, and a maximum width of the Schottky diodes parallel to the axis is a second value less than or equal to the first value. A breakdown voltage of the MPS device is greater than or equal to 115% of a maximum operating voltage of the MPS device in a blocking state.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a silicon carbide-based scalable electronic device, an electronic device manufacturing method and an electronic apparatus comprising the electronic device. In particular, the present disclosure relates to a miniaturizable merged PiN Schottky device with reduced current leakage. BACKGROUND

[0002] As known, semiconductor materials with wide gap (for example, with an energy value of the band gap Eg greater than 1.1 eV), low on-state resistance (R ON ), high thermal conductivity, high operating frequency and high charge carrier saturation velocity are ideal for the production of electronic components such as diodes or transistors, in particular for power applications. A material with said characteristics and designed for the manufacture of electronic components is silicon carbide (SiC). In particular, with reference to the previously listed properties, silicon carbide, in its different polytypes (for example, 3C-SiC, 4H-SiC, 6H-SiC), is better than silicon.

[0003] Electronic devices arranged on a silicon carbide substrate have many advantages with respect to similar devices arranged on a silicon substrate, such as low on-state output resistance, low leakage current, high operating temperature and high operating frequency. In particular, SiC Schottky diodes exhibit higher switching performance, making SiC electronic devices particularly advantageous for high frequency applications.

[0004] Merged PiN Schottky (MPS) devices based on SiC are also known. MPS devices have at least one Schottky diode and at least one PN diode (i.e. junction and semiconductor) arranged parallel to each other.

[0005] During use in the forward state, due to the lower Schottky diode forward voltage (about 0.7 V) with respect to the PN diode forward voltage (about 2.5 V), the MPS device operates as a Schottky diode, with lower current density (low leakage in the on-state for applied voltages comprised between about 0.7 V and about 3 V) and sufficiently high current density (for example for applied voltages greater than 3 V) assuming the characteristics of the PN diode. In this way, the MPS device has the high switching speed and high efficiency typical of Schottky diodes, but is also able to operate at high voltages and high currents, such as PN diodes (for example when biased to about 7 V, reaching a current equal to about 100 A).

[0006] In order to make the MPS device work efficiently in the on-state, the known MPS device is designed so that the total junction area of the Schottky diode is greater than the total junction area of the PN diode. This criterion on the junction area is also met during the miniaturization of the MPS device, which is necessary to optimize the current concentration, the electrical performance and the integration of the electronic device.

[0007] However, since there is a technical limit to the photolithography process currently used in the manufacture of MPS devices, it is not possible to arbitrarily reduce the junction area of the PN diode. In particular, an excessive expansion of the MPS device leads to a high risk of short circuit between the ohmic contact of the Schottky diode and the PN diode, which can cause damage to the MPS device.

[0008] Therefore, in the design of the known MPS device, there is a trade-off between the miniaturization that can be achieved and the electrical performance to be obtained. SUMMARY

[0009] The present disclosure relates to providing a scalable SiC-based MPS device, a method of manufacturing an MPS device, and an electronic device including the same, such as to overcome the drawbacks of the prior art.

[0010] The present disclosure relates to an MPS device comprising: a substrate of silicon carbide having a first conductivity; a drift layer of silicon carbide having the first conductivity extending over the substrate; a first implanted region having a second conductivity opposite the first conductivity and extending in the drift layer, the first implanted region having a first dimension in a first direction; and a second implanted region having the second conductivity and extending in the drift layer, the second implanted region having a second dimension in the first direction, the second implanted region spaced apart from the first implanted region in the first direction by a third dimension, the third dimension being less than the second dimension. The MPS device comprises: a first ohmic contact in the first implanted region, the first ohmic contact having a fourth dimension in the first direction, the fourth dimension being less than the first dimension; and a second ohmic contact in the second implanted region, the second ohmic contact having a fifth dimension in the first direction, the fifth dimension being less than the second dimension. The MPS device further comprises: a first junction barrier (JB) diode at a first surface of the drift layer and the first implanted region; and a second junction barrier (JB) diode at the first surface of the drift layer and the second implanted region. A first electrical terminal is in ohmic contact with the first surface of the drift layer at the first implanted region and the second implanted region, the first electrical terminal having a fifth dimension in the first direction, the fifth dimension being greater than a sum of the first dimension, the second dimension, and the third dimension. A first Schottky diode is located at the drift layer between the first implanted region and the second implanted region, wherein the drift layer has a dopant concentration such that a breakdown voltage of the MPS device is greater than or equal to 115% of a maximum operating voltage of the MPS device in the off-state, beyond which a charge carrier multiplication phenomenon occurs.

[0011] This disclosure also relates to a device comprising: a substrate of a first conductivity type; a drift layer of the first conductivity type; a drift layer having a first surface; a first implantation region of a second conductivity type extending from the first surface into the drift layer, the first implantation region having a first size in a first direction; and a second implantation region of the second conductivity type extending from the first surface into the drift layer, the second implantation region having a second size in the first direction, the second implantation region being spaced apart from the first implantation region by a third size in the first direction, the third size being smaller than the second size and the third size being smaller than the first size.

[0012] A first terminal is located on a first surface of the drift layer, in a first injection region and a second injection region, and has a fourth dimension in a first direction, the fourth dimension being larger than the sum of the first, second, and third dimensions. A first Schottky diode is located between the first terminal and the drift layer between the first and second injection regions. A first junction barrier diode is located between the first injection region and the first terminal, and a second junction barrier diode is located between the second injection region and the first terminal. Attached Figure Description

[0013] To better understand this disclosure, preferred embodiments thereof are now described by way of non-limiting example only with reference to the accompanying drawings, wherein:

[0014] Figure 1 An MPS device according to an embodiment of the present disclosure is shown in a cross-sectional view;

[0015] Figure 2A and Figure 2B A corresponding embodiment according to the present disclosure is shown in the plan view from above. Figure 1 MPS devices;

[0016] Figure 2C The illustration schematically depicts an embodiment according to the present disclosure. Figure 1 A graph showing the correlation between the breakdown voltage of the MPS device and the dopant concentration of the drift layer of the MPS device; and

[0017] Figures 3A to 3G An embodiment according to the present disclosure is shown in a cross-sectional view. Figure 1 The corresponding manufacturing steps of MPS devices.

[0018] Elements common to the different embodiments of this disclosure described herein are indicated by the same reference numerals. Detailed Implementation

[0019] Side section view in a Cartesian (triaxial) reference system with axes X, Y, and Z. Figure 1A merged PiN Schottky (MPS) device 50 is shown, according to one aspect of the present disclosure. In particular, the MPS device 50 is shown in an XZ plane defined by axes X and Y, and is included in an electronic apparatus (not shown, such as a notebook computer, a mobile phone, a server, a TV, a car, a car charging station or a conversion system for photovoltaic panels). Figure 1

[0020] The MPS device 50 comprises: a substrate 53 of N-type SiC, having a first dopant concentration, provided with a surface 53a opposite a surface 53b, and having a thickness comprised between 50 pm and 350 pm, more particularly between 160 pm and 200 pm, for example equal to 180 pm, between the surfaces 53a and 53b; a drift layer (grown in epitaxial way) 52 of N-type SiC, having a second dopant concentration smaller than the first dopant concentration, and having a top surface 52a and a bottom surface 52b opposite each other, the drift layer 52 extending on the surface 53a of the substrate 53 (in detail, the surfaces 53a and 52b are in contact with each other) and having a thickness comprised between 5 pm and 15 pm between the surfaces 52a and 53b; an ohmic contact region or layer 56 (for example of silicid of nickel), extending on the surface 53b of the substrate 53; a cathode metallization 57 (for example of Ti / NiV / Ag or Ti / NiV / Au), extending on the ohmic contact region 56; an anode metallization 58 (for example of Ti / AlSiCu or Ni / AlSiCu), extending on the top surface 52a of the drift layer 52; a passivation layer 69, extending on the anode metallization 58 to protect the latter; at least one P-type implantation region 59' in the drift layer 52, facing the top surface 52a of the drift layer 52, and for each implantation region 59', facing a respective ohmic contact 59", so that each implantation region 59' forms with the substrate 53 a respective junction barrier (JB) element 59; an edge termination region or guard ring 60 (optional), in particular a P-type implantation region, completely surrounding the junction barrier (JB) elements 59; and an insulating layer 61 (optional), extending on the top surface 52a of the drift layer 52 to completely surround the JB elements 59, at least partially superimposed to the guard ring 60 and laterally delimiting the anode metallization 58.

[0021] One or more Schottky diodes 62 are formed at the interface between the drift layer 52 and the anode metallization 58, laterally to the implantation regions 59'. In particular, a Schottky (semiconductor-metal) junction is formed by direct electrical contact of portions of the drift layer 52 with respective portions of the anode metallization 58.

[0022] In particular, Figure 1 ​Two implantation regions 59' are shown, which form respective JB elements 59 with the substrate 53. In more detail, the JB elements 59 are P-i-N diodes formed by the implantation regions 59', the drift layer 52 and the substrate 53.

[0023] The regions of the MPS device 50 comprising the JB elements 59 and the Schottky diodes 62 (i.e. the regions contained within the guard ring 60) are the active region 54 of the MPS device 50.

[0024] Each ohmic contact 59" forms an electrical connection having a resistivity value lower than that of the implantation region 59' in which it is housed. The ohmic contacts 59" are formed according to the prior art. For example, each ohmic contact 59" is formed by one or more carbon-rich layers, including for example a layer of graphite or a multilayer of graphene. Alternatively, as shown in the example of Fig. 4, each ohmic contact 59" is formed by a layer of metal, for example titanium or tungsten. Figure 1 As shown, the ohmic contacts 59" do not extend along the Z axis beyond the top surface 52a; in other words, the ohmic contacts 59" have a respective surface 59a coplanar with the top surface 52a (i.e. aligned along the X axis) and extend within the respective implantation region 59' to a depth (along the Z axis) comprised between 1 nanometer and tens of nanometers (for example between 1 nm and 20 nm) measured from the top surface 52a. Furthermore, the ohmic contacts 59" do not come into direct physical contact with the drift layer 52 and are physically and electrically separated from the latter by the respective implantation region 59'. For example, as shown in the example of Fig. 4, each ohmic contact 59" extends in the respective implantation region 59' so as to be surrounded on the sides and below by the latter, while the respective surface 59a is in contact with the anode metallization 58. This prevents the anode metallization 58 from forming a resistance with the drift layer 52 (and not with the Schottky diodes 62) and prevents the flow of current in direct and reverse bias conditions. Figure 1 As shown, the ohmic contacts 59" do not extend along the Z axis beyond the top surface 52a; in other words, the ohmic contacts 59" have a respective surface 59a coplanar with the top surface 52a (i.e. aligned along the X axis) and extend within the respective implantation region 59' to a depth (along the Z axis) comprised between 1 nanometer and tens of nanometers (for example between 1 nm and 20 nm) measured from the top surface 52a. Furthermore, the ohmic contacts 59" do not come into direct physical contact with the drift layer 52 and are physically and electrically separated from the latter by the respective implantation region 59'. For example, as shown in the example of Fig. 4, each ohmic contact 59" extends in the respective implantation region 59' so as to be surrounded on the sides and below by the latter, while the respective surface 59a is in contact with the anode metallization 58. This prevents the anode metallization 58 from forming a resistance with the drift layer 52 (and not with the Schottky diodes 62) and prevents the flow of current in direct and reverse bias conditions.

[0025] In a plan view from above in the XY plane defined by the axes X and Y, Figure 2A an MPS device 50 according to an embodiment of the present disclosure is shown, similar to that shown in Figure 1 .

[0026] In Figure 2A , the MPS device 50 comprises a plurality of Schottky diodes 62 and JB elements 59 having a respective shape similar to a stripe in the XY plane. In particular, in the XY plane, the Schottky diodes 62 and the JB elements 59 have a respective main extension parallel to the Y axis and are alternated with each other along the X axis.

[0027] In a plan view from above in the XY plane, Figure 2B an MPS device 50 according to a further embodiment of the present disclosure is shown, similar to that shown in Figure 1 .

[0028] InFigure 2B In particular, in the XY plane, each Schottky diode 62 (i.e., each cell) has a circular shape. Alternatively, each Schottky diode 62 has a polygonal shape in the XY plane, such as a square shape or a hexagonal shape. Moreover, one or more JB elements 59 surround the Schottky diodes 62, so that the Schottky diodes 62 and the JB elements 59 alternate to each other parallel to the X axis and parallel to the Y axis.

[0029] As shown in Figures 1 to 2B , each JB element 59 has a minimum width at the respective surface 59a parallel to the X axis, and this width is equal to a first distance (or value) dl, and each Schottky diode 62 has a respective maximum width at the top surface 52a parallel to the X axis, and this respective width is equal to a second distance (or value) d2. Therefore, considering two Schottky diodes 62 close to each other (i.e., facing each other through the same JB element 59, parallel to the X axis), the minimum mutual distance of these two Schottky diodes 62 along the X axis is equal to the first distance dl; and considering two JB elements 59 close to each other (i.e., facing each other through the drift layer 52, parallel to the X axis), the maximum mutual distance of these two JB elements 59 along the X axis is equal to the second distance d2. In particular, in the XY plane, the second distance d2 coincides with the diameter of each Schottky diode 62 having said circular shape, and the first distance dl is the distance (measured parallel to the X axis or to the Y axis) between the Schottky diodes 62 close to each other in the matrix of cells (i.e., immediately next to each other in the matrix of cells parallel to the X axis or to the Y axis). Figure 2B

[0030] More in detail, each JB element 59 has a first side surface 59b and a second side surface 59c opposite to each other parallel to the X axis and adjacent to the surface 59a Figure 1 The side surfaces 59b, 59c of the same JB element 59 are at a first distance dl from each other. Two JB elements 59 close to each other have respective first side surfaces 59b (or alternatively, respective second side surfaces 59c) facing each other and at a second distance d2 from each other at the anode metallization 58.

[0031] According to the present disclosure, the first distance dl is greater than or equal to the second distance d2. For example, the first distance dl is comprised between about 2 pm and about 3 pm, and the second distance d2 is comprised between about 1.5 pm and about 1.8 pm.

[0032] Therefore, at the top surface 52a, the total extension area of the Schottky diodes 62 is less than or equal to the total extension area of the JB elements 59.​

[0033] Furthermore, said second dopant concentration of the drift layer 52 is greater than the dopant concentration commonly used in the drift layer of known MPS devices.

[0034] According to the present disclosure, the second dopant concentration is such that the breakdown voltage of the MPS device 50 is greater than or equal to 115% of the maximum working voltage of the MPS device 50 in the quiescent state (i.e. in reverse bias). In other words, the second dopant concentration is such that the breakdown voltage (i.e. the voltage applicable to the MPS device 50 in the quiescent state, beyond which the phenomenon of charge carrier multiplication occurs, with consequent sharp increase in the current of the device MPS 50 in absolute value) exceeds said maximum working voltage in the quiescent state, at most by 15% of the latter. In particular, the maximum working voltage is equal to the repetitive peak reverse voltage (V RRM ) of the MPS device 50, as such known.

[0035] In more detail, as shown in Figure 2C , the breakdown voltage is inversely proportional (in detail, in a linear manner) to the second dopant concentration. For example, when the second dopant concentration is equal to about 2.8 · e 16 at / cm 3 , the breakdown voltage is equal to about 760 V; and when the second dopant concentration is equal to about 2 · e 16 at / cm 3 , the breakdown voltage is equal to about 880 V.

[0036] According to one embodiment, when the maximum working voltage of the MPS device 50 in the quiescent state is equal to about 650 V and said thickness of the drift layer 52 is equal to about 5 pm, the second dopant concentration varies between about 2 · e 16 at / cm 3 and about 2.8 · e 16 at / cm 3 , so as to ensure that the breakdown voltage of the MPS device 50 is greater than or equal to about 750 V.

[0037] According to yet another embodiment, when the maximum working voltage of the MPS device 50 in the quiescent state is equal to about 1200 V and said thickness of the drift layer 52 is equal to about 9 pm, the second dopant concentration is less than or equal to about 1.2 · e 16 at / cm 3 (for example it varies between about 5 · e 15 at / cm 3 and about 1.2 · e 16 at / cm 3 ), so as to ensure that the breakdown voltage of the MPS device 50 is greater than or equal to about 1380 V.

[0038] The manufacturing steps of the MPS device 50 herein are described below with reference to Figures 3A to 3G .

[0039] With reference to Figure 3A , a wafer 80 of a substrate 53 comprising SiC, in particular 4H-SiC, although other polytypes such as but not limited to 2H-SiC, 3C-SiC and 6H-SiC can be used, is arranged. For example, the substrate 53 has a N-type dopant concentration comprised between 1 · 1018at / cm3and 1 · 1020at / cm3, and a thickness measured along the Z axis between the surfaces 53a and 53b comprised between 300 pm and 450 pm, in particular equal to about 360 pm. 19 at / cm 3 and 1 · 1020at / cm3, and a thickness measured along the Z axis between the surfaces 53a and 53b comprised between 300 pm and 450 pm, in particular equal to about 360 pm. 22 at / cm 3

[0040] A drift layer 52 is formed on the surface 53a of the substrate 53, for example by epitaxial growth, having a N-type dopant concentration such that the breakdown voltage of the MPS device 50 is greater than or equal to 115% of the maximum operating voltage of the MPS device 50 in the inhibited state, as previously described. The drift layer 52 is made of SiC, in particular 4H-SiC, although other SiC polytypes can be used, such as 2H, 6H, 3C or 15R.

[0041] A hard mask 71 is formed on the surface 52a of the drift layer 52, for example by depositing photoresist or TEOS or another material suitable for this purpose. The hard mask 71 has a thickness comprised between 0.5 pm and 2 pm, or in any case, a thickness that masks the implants herein described below with reference to Figure 3B . The hard mask 71 extends in a region of the wafer 80 in which, in a subsequent step, the active region 54 of the MPS device 50 will be formed. In plan view, on the XY plane, the hard mask 70 covers the region of the surface 52a of the drift layer 52 in which the Schottky diode 62 will be formed, and leaves exposed the region of the surface 52a of the drift layer 52 in which the implant region 59' will be formed.

[0042] Then, with the hard mask 71 (the implants are indicated in the figures by the arrows 70), a step of implanting a dopant substance of the second conductivity type (here P) is performed. In Figure 3A , during the step of implanting, the guard ring 60 (if any) is also formed.

[0043] In an exemplary embodiment, the implant step 70 comprises one or more implants of a P-type dopant substance, the implant energy of which is comprised between 30 keV and 400 keV, and the dose is comprised between 1 · 1012at / cm3and 1 · 1014at / cm3. 12 at / cm 2 and 1 · 1014at / cm3. 15 ​at / cm 2 Between these values, to form a dopant concentration greater than 1.10. 18 at / cm 3 The injection region 59' is thus formed. Therefore, an injection region having a depth between 0.4 μm and 1 μm as measured from surface 52a is formed.

[0044] Injection area 59' and protective ring 60 as Figure 3B As shown, the hard mask 71 is removed. Specifically, Figure 3B This shows that the first distance d1 is greater than the second distance d2. Alternatively, the first distance d1 is equal to the second distance d2.

[0045] exist Figure 3B In this process, the thermal annealing step is performed at surface 52a to activate the surface. Figure 3A The dopant material is injected during the process. For example, thermal annealing is performed at a temperature above 1500°C (e.g., between 1700°C and 1900°C).

[0046] Reference Figures 3C to 3E Then other steps are performed to form the ohmic contact 59.

[0047] Reference Figure 3C An insulating layer 61 (if present) is formed. The insulating layer 61 is at least partially superimposed on the guard ring 60 and, together with the latter, defines the active region 54 of the MPS device 50.

[0048] In addition, refer to Figure 3C A silicon oxide or TEOS deposition mask 73 is formed to cover a surface region of the drift layer 52 (and a guard ring 60, if present) that differs from the injection region 59'. In other words, the mask 73 has a through opening 73a at a portion of the injection region 59', which will become the ohmic contact 59.

[0049] Then, Figure 3D Nickel deposition is performed on mask 73 and through opening 73a ( Figure 3D The process is performed within the metal layer 74). Thus, the deposited nickel reaches and contacts the injection region 59' through the through opening 73a.

[0050] Reference Figure 3ESubsequently, a high-temperature thermal annealing (at a temperature comprised between 900°C and 1200°C, for a time interval comprised between 1 minute and 120 minutes) allows the ohmic contact 59" of the silicon nickelide to be formed at the through opening 73a between the deposited nickel and the silicon of the drift layer 52 by chemical reaction. In fact, the deposited nickel reacts where it comes into contact with the surface material of the drift layer 52, thus forming Ni2Si (i.e. the ohmic contact 59"). Subsequently, a step of removing the metal layer 74 extending above the mask 73 and the ohmic contact 59" is performed.

[0051] With reference to Figure 3F , a step of grinding the substrate 53 is performed at the surface 53b to reduce the thickness of the substrate 53. For example, at the end of the grinding step, the substrate 53 has a thickness measured along the Z axis between the surfaces 53a and 53b comprised between 100 pm and 250 pm, and in particular equal to about 180 pm. The ohmic contact layer 56 (a process similar to the one described with reference to Figures 3C to 3E , and the cathodic metallization 57 from the ohmic contact layer 56 are then formed in succession to each other.

[0052] With reference to Figure 3G , a step of removing the mask 73 is performed. Moreover, the anodic metallization 58 is formed on the ohmic contact 59" and on the areas previously covered by the mask 73. For example, Ti / AlSiCu or Ni / AlSiCu is deposited on the surface 52a of the drift layer 52 so that the anodic metallization 58 contacts the drift layer 52 and the JB element 59.

[0053] Then, a passivation layer 69 (not shown in Figure 3G ) is formed on the anodic metallization 58 and the insulating layer 61, thus obtaining the MPS device 50 shown in Figure 1 .

[0054] The advantages achieved by the present disclosure provided according to the present description are evident through the discussion of the features of the present disclosure.

[0055] In particular, since in the MPS device 50 the first distance dl is greater than or equal to the second distance d2, the MPS device 50 is less subject to the lithography limitations of known MPS devices related to the formation of the ohmic contact 59", thus it is more scalable. Therefore, the MPS device 50 allows an optimal use of the wafer area (ensuring a higher integration density), and allows reduced manufacturing costs and improved electrical performances.

[0056] Moreover, the high dopant concentration of the drift layer 52 allows a high on-state current (i.e. a high surge peak forward current IFSM parameter) and prevents a higher ratio between the JB element 59 and the Schottky diode 62 in the area from causing a reduction in the electrical performances.

[0057] In more detail, the only parameter that influences the design and calculation of the second dopant concentration is the desired breakdown voltage of the MPS device 50. Therefore, with respect to known MPS devices, the MPS device 50 has less stringent design constraints, in which the dopant concentration of the drift layer influences the breakdown voltage, and in particular the current leakage.

[0058] Due to the higher pinching efficiency operated by the JB element 59 on the Schottky diode 62, the MPS device 50 allows to reduce the current leakage. In fact, since the first distance dl is greater than or equal to the second distance d2, in use the voltage drop is mainly taken up by the JB element 59, and therefore the electric field at the surface 52a of the drift layer 52, and in particular at the Schottky diode 62, is reduced.

[0059] Finally, it is clear that modifications and / or additions of parts can be made to the contents described and illustrated herein, without thereby departing from the scope of the present disclosure, as defined in the appended claims.

[0060] The merged PiN Schottky MPS device (50) can be summarized as comprising: a substrate (53) of silicon carbide having a first conductivity; a drift layer (52) of silicon carbide having the first conductivity, extending on the substrate (53); a first implant region (59') having a second conductivity opposite to the first conductivity and extending in the drift layer (52) at a top surface (52a) of the drift layer (52) to form with the substrate (53) a first junction barrier JB diode (59); and a first electrical terminal (58) in ohmic contact with a first surface (59a) of the first implant region (59'), coplanar with the top surface (52a) of the drift layer (52), and also in direct electrical contact with the top surface (52a) of the drift layer (52) laterally to the first implant region (59') so as to form with the drift layer (52) a first Schottky diode (62), wherein the first JB diode (59) and the first Schottky diode (62) alternate with each other along a first axis (X) at the first electrical terminal (58), so that the first JB diode (59) has a minimum width parallel to the first axis (X) at the first surface (59a) of the first implant region (59') and this width has a first value (dl), and the first Schottky diode (62) has a maximum corresponding width parallel to the first axis (X) at the top surface (52a) of the drift layer (52) and this corresponding width has a second value (d2) less than or equal to the first value (dl), and wherein the drift layer (52) has its own dopant concentration such that the breakdown voltage of the MPS device is greater than or equal to 115% of the maximum operating voltage of the MPS device in the inhibited state, beyond which a phenomenon of charge carrier multiplication occurs.

[0061] The first injection region (59') can have a first lateral surface (59b) and a second lateral surface (59c) opposite each other parallel to the first axis (X) and adjacent to the first surface (59a) of the first injection region (59'), and wherein at the first electrical terminal (58) and parallel to the first axis (X), the first (59b) and second (59c) lateral surfaces are distanced from each other of a first value (dl).

[0062] The device can comprise a second injection region (59') having a second electrical conductivity and extending in the drift layer (52) at the top surface (52a) of the drift layer (52) so as to form with the substrate (53) a second JB diode (59), the second injection region (59') having a respective first surface (59a) in ohmic contact with the first electrical terminal (58) and having a respective first lateral surface (59b) and a respective second lateral surface (59c) opposite each other parallel to the first axis (X) and adjacent to the first surface (59a) of the second injection region (59'), the first Schottky diode (62) being arranged at the top surface (52a) of the drift layer (52) between the first injection region (59') and the second injection region (59') and parallel to the first axis (X) so that the respective first lateral surface (59b) or, alternatively, the respective second lateral surface (59c) face each other through the drift layer (52) and are distanced from each other parallel to the first axis (X) at the top surface (52a) of the drift layer (52) of a second value (d2).

[0063] The device can further comprise a first electrical contact region (59") extending in or on the first injection region (59') at the respective first surface (59a), the first electrical contact region (59") forming an ohmic contact and being physically and electrically separated from the drift layer (52) through the first injection region (59').

[0064] For a maximum working voltage equal to 650 V, the dopant concentration of the drift layer (52) can be less than or equal to 2.8 · e 16 at / cm 3 .

[0065] For a maximum working voltage equal to 1200 V, the dopant concentration of the drift layer (52) can be less than or equal to 1.2 · e 16 at / cm 3 .

[0066] The device can further comprise: a second electrical contact area (56) opposite the drift layer (52) at a back side (53b) of the substrate (53); a second electrical terminal (57) at the second electrical contact area (56); and a passivation layer (69) extending over the first electrical terminal (58).

[0067] The device can comprise at least one second Schottky diode (62) and at least one third implantation region (59') forming a respective third JB diode (59), wherein the Schottky diodes (62) and the JB diodes (59) are alternating to each other along a first axis (X) to form an array of diodes, or alternatively, along the first axis (X) and along a second axis (Y) orthogonal to the first axis (X) to form a matrix of diodes.

[0068] A method for manufacturing a merged PiN Schottky MPS device (50) can be summarized as comprising the steps of: arranging a substrate (53) of silicon carbide having a first conductivity; forming a drift layer (52) of silicon carbide having the first conductivity on the substrate (53); forming, in the drift layer (52) and at a top surface (52a) of the drift layer (52), a first implantation region (59') having a second conductivity opposite to the first conductivity to form a first junction barrier JB diode (59) with the substrate (53); and forming a first electrical terminal (58) in ohmic contact with a first surface (59a) of the first implantation region (59'), coplanar with the top surface (52a) of the drift layer (52) and also directly electrically contacting the top surface (52a) of the drift layer (52) laterally to the first implantation region (59') so as to form a first Schottky diode (62) with the drift layer (52), the first JB diode (59) and the first Schottky diode (62) being alternating to each other along a first axis (X) at the first electrical terminal (58) so that the first JB diode (59) has a minimum width parallel to the first axis (X) at the first surface (59a) of the first implantation region (59') and this width has a first value (dl), and the first Schottky diode (62) has a respective maximum width parallel to the first axis (X) at the top surface (52a) of the drift layer (52) and this respective width has a second value (d2) smaller than or equal to the first value (dl), and the drift layer (52) has its own dopant concentration so that a breakdown voltage of the MPS device is greater than or equal to 115% of a maximum operating voltage of the MPS device in a quiescent state, beyond which a phenomenon of charge carrier multiplication occurs.

[0069] An electronic device can be summarized as comprising a merged PiN Schottky MPS device (50).

[0070] For example, with reference to Figure 1The conductivity described can be opposite to each other as previously described. Thus, in this case, the drift layer 52 and the substrate 53 are P-type, and the implanted region 59' and, if any, the guard ring 60 are N-type.

[0071] The various embodiments described above can be combined to provide further embodiments. If the concepts of various patents, applications, and publications are employed to provide other embodiments, the various aspects of the embodiments can be modified.

[0072] In light of the above detailed description, these and other changes can be made to the embodiments. In general, the terms used in the appended claims should not be construed to limit the claims of the application to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments that can be explicitly disclosed or residual equivalents thereof. Thus, the claims are not limited to the embodiments disclosed in this disclosure.

Claims

1. A merged PiN Schottky MPS device, comprising: a substrate of silicon carbide having a first conductivity; a drift layer of silicon carbide having the first conductivity extending over the substrate; a first implanted region having a second conductivity opposite the first conductivity and extending in the drift layer, the first implanted region having a first dimension in a first direction; a second implanted region having the second conductivity and extending in the drift layer, the second implanted region having a second dimension in the first direction, the second implanted region spaced apart from the first implanted region in the first direction by a third dimension, the third dimension being less than both the first dimension and the second dimension; a first ohmic contact in the first implanted region, the first ohmic contact having a fourth dimension in the first direction, the fourth dimension being less than the first dimension; a second ohmic contact in the second implanted region, the second ohmic contact having a fifth dimension in the first direction, the fifth dimension being less than the second dimension; a first junction barrier JB diode at a first surface of the drift layer and the first implanted region; a second junction barrier JB diode at the first surface of the drift layer and the second implanted region; and a first electrical terminal ohmically contacting the first surface of the drift layer at the first implanted region and the second implanted region, the first electrical terminal having a fifth dimension in the first direction, the fifth dimension being greater than a sum of the first dimension, the second dimension, and the third dimension; a first Schottky diode at the drift layer between the first implanted region and the second implanted region, wherein the drift layer has a dopant concentration such that a breakdown voltage of the MPS device is greater than or equal to 115% of a maximum operating voltage of the MPS device in a quiescent state, beyond which a charge carrier multiplication phenomenon occurs.

2. The device of claim 1, wherein the first implanted region has first and second side surfaces opposite each other and transverse to the first surface of the first implanted region, and wherein the first and second side surfaces are spaced apart from each other by the first dimension.

3. The device of claim 2, wherein the second implanted region has a surface ohmically contacting the first electrical terminal, and first and second side surfaces opposite each other, the first Schottky diode is disposed at the first surface of the drift layer and parallel to a second direction transverse to the first direction, the first side surface of the first implanted region and the first side surface of the second implanted region facing each other through the drift layer and spaced apart from each other by the third dimension.

4. The device of claim 1, wherein the first ohmic contact is physically and electrically separated from the drift layer by the first implanted region.

7. The device of claim 1, further comprising:

5. The device of claim 1, wherein the dopant concentration of the drift layer is less than or equal to 2.8 e at / cm for the maximum operating voltage equal to 650 V. 16 at / cm 3 .

6. The device of claim 1, wherein the dopant concentration of the drift layer is less than or equal to 1.2 e at / cm for the maximum operating voltage equal to 1200 V. 16 at / cm 3 . a second electrical contact region at a backside of the substrate opposite the drift layer. ​ a second electrical terminal at the second electrical contact region; and a passivation layer extending over the first electrical terminal.

8. The device of claim 1, further comprising a diode array comprising the first junction barrier JB diode and the second junction barrier JB diode, the first Schottky diode, at least one second Schottky diode, at least one third implant region, and a third junction barrier JB diode, wherein the first junction barrier JB diode, the Schottky diode, and the second junction barrier JB diode alternate with each other along the first direction.

9. A method for manufacturing a combined PiN Schottky MPS device, comprising: forming a drift layer of silicon carbide having a first conductivity on a substrate of silicon carbide having the first conductivity; forming a first junction barrier JB diode with the substrate by forming a first implant region having a second conductivity opposite the first conductivity in the drift layer and at a first surface of the drift layer; and forming a first Schottky diode with the drift layer by forming a first electrical terminal in ohmic contact with a first surface of the first implant region, coplanar with the first surface of the drift layer, and also directly electrically contacting the first surface of the drift layer laterally to the first implant region, the first junction barrier JB diode and the first Schottky diode alternate with each other along a first axis at the first electrical terminal such that the first junction barrier JB diode has a first width at the first surface of the first implant region parallel to the first axis and the first Schottky diode has a second width at the first surface of the drift layer parallel to the first axis, the second width being less than or equal to the first width, and the drift layer has a dopant concentration such that a breakdown voltage of the MPS device is greater than or equal to 115% of a maximum operating voltage of the MPS device in a blocking state, beyond which a charge carrier multiplication phenomenon occurs.

10. The method of claim 9, further comprising: forming a second junction barrier JB diode spaced apart from the first junction barrier JB diode by the first Schottky diode.

11. A combined PiN Schottky MPS device, comprising: a substrate of a first conductivity type; a drift layer of the first conductivity type, the drift layer having a first surface; a first implant region of a second conductivity type extending from the first surface into the drift layer, the first implant region having a first dimension in a first direction; a second implant region of the second conductivity type extending from the first surface into the drift layer, the second implant region having a second dimension in the first direction, the second implant region spaced apart from the first implant region in the first direction by a third dimension, the third dimension being less than the second dimension, the third dimension being less than the first dimension; a first ohmic contact in the first implant region, the first ohmic contact having a fifth dimension in the first direction, the fifth dimension being less than the first dimension; a second ohmic contact in the second implant region, the second ohmic contact having a sixth dimension in the first direction, the sixth dimension being less than the second dimension; a first terminal on the first surface of the drift layer, the first terminal over the first implant region and the second implant region, the first terminal having a fourth dimension in the first direction, the fourth dimension being greater than a sum of the first dimension, the second dimension, and the third dimension; a first Schottky diode between the first terminal and the drift layer between the first implant region and the second implant region; a first junction barrier diode between the first implant region and the first terminal; and a second junction barrier diode between the second implant region and the first terminal.

12. The device of claim 11, further comprising a guard ring in the drift layer and surrounding the first implant region and the second implant region.

13. The device of claim 12, wherein a first end of the first terminal overlaps a portion of the guard ring adjacent to the first implant region, and a second end of the first terminal overlaps a portion of the guard ring adjacent to the second implant region.

14. The device of claim 11, further comprising a second terminal spaced apart from the drift layer by the substrate.

15. The device of claim 14, further comprising a third ohmic contact on the second terminal.

16. The device of claim 15, further comprising a first insulating layer adjacent to the first terminal and on the first surface of the drift layer.

17. The device of claim 16, further comprising a second insulating layer on the first terminal and on the first insulating layer, the second insulating layer comprising an opening exposing a surface of the first terminal aligned with the first Schottky diode. ​

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