LED vertical chip assembly and manufacturing method thereof
By depositing a transparent conductive layer and a bonding metal layer on the Micro vertical chip, and then patterning the target substrate to deposit a passivation layer and a planarization layer, the problem of ITO breakage on the sidewall of the Micro vertical chip was solved, and the chip's normal light emission and reliable electrical connection were achieved.
Patent Information
- Application Number
- CN202411139311.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2026-03-03
AI Technical Summary
When micro vertical chips are deposited with ITO after Mesa and metal etching and passivation layer opening, the lines on the sidewalls are prone to breakage, which affects the normal light emission of the chip.
After depositing a transparent conductive layer and a bonding metal layer on the epitaxial wafer, the epitaxial wafer is transferred to the target substrate for patterning, passivation layer deposition and planarization layer filling, electrode exposure by etching, and finally a second transparent conductive layer is deposited to bypass the chip gap to avoid ITO wire breakage.
This effectively solved the ITO wire breakage problem, ensuring the chip emits light normally and improving the reliability of the chip's electrical connection and signal transmission efficiency.
Smart Images
Figure CN121604569A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LED chip technology, and in particular to an LED vertical chip assembly and its manufacturing method. Background Technology
[0002] Traditional micro vertical chips deposit a passivation layer after Mesa and metal etching, and then deposit ITO after creating openings in the passivation layer to complete the common cathode connection. However, the spacing of micro vertical chips is generally less than 4µm. To ensure the effective light-emitting area of the chip, the angle after Mesa and metal etching needs to be close to 90°. However, at this angle, it is easy to cause ITO breaks at the sidewalls, affecting the normal light emission of the chip. Summary of the Invention
[0003] In view of the shortcomings of the prior art, the purpose of this application is to provide an LED vertical chip assembly and its manufacturing method, which aims to solve the problem that the ITO wires at the sidewall of the Micro vertical chip are easily broken, affecting the normal light emission of the chip.
[0004] In a first aspect, this application provides a method for manufacturing an LED vertical chip assembly, comprising:
[0005] An epitaxial wafer is provided, the epitaxial wafer comprising a substrate and a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially deposited on the substrate, wherein the surface of the second semiconductor layer is doped with a doping element;
[0006] A first transparent conductive layer is deposited on the second semiconductor layer to form an ohmic contact;
[0007] A bonding metal layer is deposited on the first transparent conductive layer by vapor deposition;
[0008] The target substrate is bonded to the bonding metal layer, and the substrate is removed to expose the first semiconductor layer;
[0009] The first electrode is deposited on the first semiconductor layer by vapor deposition;
[0010] The bonding structure on the target substrate is patterned to obtain multiple red vertical chips bonded to the target substrate;
[0011] A passivation layer is deposited on the surface and sidewalls of the red light vertical chip;
[0012] A planarization layer is filled between the passivation layers covering the red light vertical chip;
[0013] The planarization layer and the passivation layer are etched to expose the first electrode;
[0014] A second transparent conductive layer is deposited on the target substrate. The second transparent conductive layer includes a first portion and a second portion connected to the first portion. The first portion is connected to the first electrode, and the second portion is located on the target substrate.
[0015] In one possible embodiment, the method further includes:
[0016] A second electrode is deposited on the second part by vapor deposition.
[0017] In one possible embodiment, filling the planarization layer between the passivation layers covering the red vertical chip includes:
[0018] The adhesive is spin-coated between the passivation layers covering the red vertical chip to form a planarization layer.
[0019] In one possible embodiment, the spin coating of the adhesive material between the passivation layers covering the red vertical chip to form a planarization layer includes:
[0020] BCB adhesive is spin-coated between the passivation layers covering the red vertical chip to form a planarization layer.
[0021] In one possible embodiment, etching the planarization layer and the passivation layer to expose the first electrode includes:
[0022] The planarization layer and the passivation layer are dry etched using oxygen and carbon tetrafluoride at a concentration ratio of 10:1 to expose the first electrode; wherein the height of the etched planarization layer is consistent with the height of the red light vertical chip.
[0023] In one possible embodiment, etching the planarization layer and the passivation layer to expose the first electrode includes: dry etching the planarization layer and the passivation layer using oxygen and carbon tetrafluoride at a concentration ratio of 15:1 to expose the first electrode; wherein the height of the etched planarization layer is consistent with the height of the red light vertical chip.
[0024] In one possible embodiment, bonding the target substrate to the bonding metal layer includes:
[0025] Provide a target substrate;
[0026] A metal layer is deposited on the target substrate;
[0027] The metal layer is bonded to the bonding metal layer using a low-temperature bonding process, so that the target substrate is bonded to the bonding metal layer.
[0028] In one possible embodiment, the second semiconductor layer is a P-type semiconductor layer.
[0029] In one possible embodiment, the doping element includes carbon or magnesium.
[0030] Secondly, this application also provides an LED vertical chip assembly, which is prepared using the LED vertical chip assembly fabrication method as described in the first aspect.
[0031] Beneficial effects:
[0032] This application provides an LED vertical chip assembly and its fabrication method. The method involves processing an epitaxial wafer and transferring it onto a target substrate, then patterning the epitaxial wafer to obtain multiple red vertical chips. A passivation layer is deposited on the surface and sidewalls of the red vertical chips, and then the gaps between the chips are filled to obtain a planarization layer. The planarization layer and passivation layer are then etched to expose the first electrode. Finally, a second transparent conductive layer is deposited on the target substrate. Due to the design of the planarization layer, the second transparent conductive layer can bypass the ramps between the chips, thereby effectively solving the problem of ITO wire breakage. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of a method for manufacturing an LED vertical chip assembly, provided in an embodiment of this application.
[0034] Figure 2 for Figure 1 A schematic diagram of the epitaxial wafer provided in a method for fabricating an LED vertical chip assembly is shown.
[0035] Figure 3 for Figure 1 The diagram shows the structure of the first transparent conductive layer after evaporation in a method for fabricating an LED vertical chip assembly.
[0036] Figure 4 for Figure 1 A schematic diagram of the structure after vapor deposition of a bonding metal layer in a method for fabricating an LED vertical chip assembly;
[0037] Figure 5 For Figure 1 A schematic diagram of the structure after depositing a passivation layer in a method for fabricating an LED vertical chip assembly is shown.
[0038] Figure 6 for Figure 1 A schematic diagram of the substrate removal process in a method for fabricating an LED vertical chip assembly is shown.
[0039] Figure 7 for Figure 1This is a schematic diagram of the structure after the first electrode is fabricated in a method for manufacturing an LED vertical chip assembly.
[0040] Figure 8 for Figure 1 A schematic diagram of the structure after depositing a passivation layer in a method for fabricating an LED vertical chip assembly is shown.
[0041] Figure 9 for Figure 1 A schematic diagram of the structure after filling the planarization layer in a method for manufacturing an LED vertical chip assembly is shown.
[0042] Figure 10 for Figure 1 A schematic diagram of the structure after etching the planarization layer and passivation layer in a method for fabricating an LED vertical chip assembly;
[0043] Figure 11 for Figure 1 This diagram shows the structure after the second transparent conductive layer is deposited in a method for fabricating an LED vertical chip assembly.
[0044] Explanation of reference numerals in the attached figures:
[0045] 10-Substrate; 11-Red vertical chip; 20-First semiconductor layer; 21-First electrode; 30-Light emitting layer; 40-Second semiconductor layer; 50-First transparent conductive layer; 60-Bonding metal layer; 70-Target substrate; 71-Metal layer; 80-Passivation layer; 90-Planarization layer; 100-Second transparent conductive layer; 110-Second electrode. Detailed Implementation
[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0047] This invention discloses many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described herein. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, terms can be understood at least in part according to their usage in accordance with the invention. For example, the term "one or more" as used herein, depending at least in part on the invention, can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood, depending at least in part on the invention, to convey either a singular or a plural usage. Furthermore, the term "based on..." can be understood not necessarily to convey an exclusive set of factors, but rather, depending at least in part on the invention, can alternatively allow for additional factors that do not necessarily have to be explicitly described.
[0049] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this invention should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.
[0050] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used in this invention to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways, rotated 90°, or otherwise oriented, and the spatial relative descriptive terms used in this invention can be interpreted accordingly.
[0051] As used in this invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.
[0052] refer to Figure 1 This is a schematic flowchart of a method for manufacturing an LED vertical chip assembly according to an embodiment of this application. The method includes:
[0053] 101: Provide an epitaxial wafer.
[0054] For example, such as Figure 2 As shown, the epitaxial wafer includes a substrate 10 and a first semiconductor layer 20, a light-emitting layer 30 and a second semiconductor layer 40 sequentially deposited on the substrate 10. The surface of the second semiconductor layer 40 is doped with doping elements.
[0055] Optionally, the doping element includes carbon or magnesium.
[0056] In the embodiments of this application, the first semiconductor layer 20 and the second semiconductor layer 40 are doped semiconductor layers of different types.
[0057] The first semiconductor layer 20 can be an N-doped semiconductor layer or a P-doped semiconductor layer, and the second semiconductor layer 40 can be a P-doped semiconductor layer or an N-doped semiconductor layer.
[0058] In other words, if the first semiconductor layer 20 is an N-doped semiconductor layer (i.e., an N-type semiconductor layer), then the second semiconductor layer 40 can be a P-doped semiconductor layer (i.e., a P-type semiconductor layer).
[0059] The aforementioned light-emitting layer 30 can be a multiple quantum well (MQW) structure. Specifically, the quantum well or quantum layer can be InGaN, AlGaN, InN, InAlN, AlInGaN, etc., while the quantum barrier alternately stacked with the quantum well layer can be GaN, AlN, AlGaN, AlInGaN, InAlN, etc.; the multiple quantum well structure can include one, two, three, four, five, six, seven, or eight quantum wells (or at least one quantum hole); the wavelength emitted by the aforementioned light-emitting layer 30 is a wavelength in the red light band.
[0060] In the embodiments of this application, the substrate 10 can be a growth substrate or a temporary substrate. For example, the epitaxial wafer can be a red-light epitaxial wafer based on aluminum indium gallium phosphate, and the substrate is a temporary sapphire substrate and includes a P-type AlInP (or AlGaInP) layer, a light-emitting layer and an N-type AlInP (or AlGaInP) layer stacked sequentially.
[0061] 102: A first transparent conductive layer is deposited on the second semiconductor layer to form an ohmic contact.
[0062] For example, such as Figure 3 As shown, a first transparent conductive layer 50 is deposited on the surface of a second semiconductor layer 40 doped with C using a vapor deposition process, thereby forming an ohmic contact between the first transparent conductive layer 50 and the second semiconductor layer 40.
[0063] Optionally, the material of the first transparent conductive layer 50 is at least one of ITO, IGO, and IZO.
[0064] 103: A bonding metal layer is deposited on the first transparent conductive layer.
[0065] For example, such as Figure 4 As shown, a bonding metal layer 60 is then deposited on the first transparent conductive layer 50.
[0066] Optionally, the material of the bonding metal layer 60 can be a metal such as Au or Sn.
[0067] 104: Bond the target substrate to the bonding metal layer and remove the substrate to expose the first semiconductor layer.
[0068] In one implementation, step 104 includes: providing a target substrate; depositing a metal layer on the target substrate; and performing gold-to-gold bonding between the metal layer and the bonding metal layer using a low-temperature bonding process, so that the target substrate is bonded to the bonding metal layer.
[0069] Optionally, the material of the metal layer can be a metal such as Au or Sn. For example, when the material of the bonding metal layer 60 is Au, the material of the metal layer can be Au or Sn; if the material of the bonding metal layer 60 is Sn, the material of the metal layer is Au.
[0070] For example, such as Figure 5 As shown, the side of the target substrate 70 with the metal layer 71 deposited thereon is bonded to the bonding metal layer 60 by a low-temperature bonding process to transfer the epitaxial wafer onto the target substrate 70.
[0071] Optionally, the target substrate 70 is a CMOS (Complementary Metal Oxide Semiconductor) substrate.
[0072] 105: Deposit the first electrode on the first semiconductor layer.
[0073] For example, such as Figure 6 As shown, the first electrode 21 is fabricated on the first semiconductor layer 20 through photolithography, vapor deposition and annealing processes.
[0074] The first electrode 21 is one or more metals that can form an ohmic contact with the first semiconductor layer 20 to conduct current. For example, the first electrode 21 can be formed by a combination of one or more of Cr, Pt, Ti, Ni, Au, and Sn.
[0075] Alternatively, the first electrode 21 may also be formed of a transparent conductive material, such as ITO.
[0076] 106: Pattern the bonding structure on the target substrate to obtain multiple red vertical chips bonded to the target substrate.
[0077] The aforementioned patterning refers to forming a predetermined pattern shape into the layer structure through multiple photolithography and etching processes. After patterning the bonding structure, multiple independent red vertical chips 11 are formed, each separated from the others. The original functional layers between adjacent red vertical chips 11 are removed to form channels, such as... Figure 7 As shown.
[0078] 107: Deposit a passivation layer on the surface and sidewalls of the red light vertical chip.
[0079] For example, such as Figure 8 As shown, a passivation layer 80 is deposited on the surface and sidewalls of the red light vertical chip using PECVD.
[0080] Optionally, the passivation layer 80 is applied to the surface of the red light vertical chip to protect it. The passivation layer 80 can be one or more of Al2O3, AlN, SiN, SiO2, and AlON thin films.
[0081] 108: A planarization layer is filled between the passivation layers covering the red vertical chip.
[0082] In one implementation, step 108 includes: spin-coating an adhesive material between the passivation layers covering the red vertical chip to form a planarization layer.
[0083] Optionally, the step of spin-coating the adhesive between the passivation layers covering the red vertical chip to form a planarization layer includes: spin-coating BCB adhesive between the passivation layers covering the red vertical chip to form a planarization layer.
[0084] For example, such as Figure 9 As shown, BCB is filled between the passivation layers 80 of the red vertical chip using spin coating, and then cured to form a planarization layer 90.
[0085] It is understandable that this embodiment uses BCB adhesive for filling, which can improve the electrical insulation between chips and facilitate signal transmission after bonding to the target substrate, while reducing interference. For example, the spacing between AR display chips is generally less than 0.5µm, which can easily lead to chip leakage. Filling with BCB can reduce the risk of leakage between chips.
[0086] Of course, in actual use, the filler material can also be other materials, such as polyimide, silicone, polymethyl methacrylate (PMMA), etc., and no specific limitation is made here.
[0087] 109: Etch the planarization layer and the passivation layer to expose the first electrode.
[0088] In one implementation, step 109 includes: using oxygen and carbon tetrafluoride, at a concentration ratio of 10:1, to dry etch the planarization layer and the passivation layer to expose the first electrode; wherein the height of the etched planarization layer is consistent with the height of the red light vertical chip.
[0089] In another implementation, step 109 includes: using oxygen and carbon tetrafluoride, at a concentration ratio of 15:1, to dry etch the planarization layer and the passivation layer to expose the first electrode; wherein the height of the etched planarization layer is consistent with the height of the red light vertical chip.
[0090] It should be noted that the etching rate is the same when etching the planarization layer and the passivation layer.
[0091] It should be understood that exposing the first electrode means just etching away the passivation layer and planarization layer covering the first electrode, without actually etching the first electrode itself. Etching the first electrode would damage it and affect its conductivity.
[0092] For example, such as Figure 10 As shown, the passivation layer 80 and the planarization layer 90 are simultaneously etched using dry etching gas O2+CF4 (ratio 10:1 or 15:1), eventually exposing the first electrode 21.
[0093] 110: A second transparent conductive layer is deposited on the target substrate.
[0094] The second transparent conductive layer includes a first portion and a second portion connected to the first portion. The first portion is connected to the first electrode, and the second portion is located on the target substrate.
[0095] In one possible embodiment, after step 110, the method for fabricating the LED vertical chip assembly further includes: depositing a second electrode on the second portion.
[0096] The second electrode can also be referred to as the common electrode.
[0097] For example, such as Figure 11 As shown, a second transparent conductive layer 100 is deposited on the surface of the LED vertical chip and a second electrode 110 is deposited on the second portion.
[0098] Based on the same inventive concept, this embodiment also provides an LED vertical chip assembly, which is prepared using the LED vertical chip assembly manufacturing method described above.
[0099] In summary, the LED vertical chip assembly and its fabrication method provided in this application involve transferring an epitaxial wafer onto a target substrate, then patterning the epitaxial wafer to obtain multiple red vertical chips. A passivation layer is deposited on the surface and sidewalls of the red vertical chips, and the gaps between the chips are filled to obtain a planarization layer. The planarization layer and passivation layer are then etched to expose the first electrode. Finally, a second transparent conductive layer is deposited on the target substrate. Due to the design of the planarization layer, the second transparent conductive layer can bypass the ramps between the chips, thereby effectively solving the problem of ITO wire breakage.
[0100] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A method for manufacturing an LED vertical chip assembly, characterized in that, include: An epitaxial wafer is provided, the epitaxial wafer comprising a substrate and a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially deposited on the substrate, wherein the surface of the second semiconductor layer is doped with a doping element; A first transparent conductive layer is deposited on the second semiconductor layer to form an ohmic contact; A bonding metal layer is deposited on the first transparent conductive layer by vapor deposition; The target substrate is bonded to the bonding metal layer, and the substrate is removed to expose the first semiconductor layer; The first electrode is deposited on the first semiconductor layer by vapor deposition; The bonding structure on the target substrate is patterned to obtain multiple red vertical chips bonded to the target substrate; A passivation layer is deposited on the surface and sidewalls of the red light vertical chip; A planarization layer is filled between the passivation layers covering the red light vertical chip; The planarization layer and the passivation layer are etched to expose the first electrode; A second transparent conductive layer is deposited on the target substrate. The second transparent conductive layer includes a first portion and a second portion connected to the first portion. The first portion is connected to the first electrode, and the second portion is located on the target substrate.
2. The method for manufacturing an LED vertical chip assembly as described in claim 1, characterized in that, The method further includes: A second electrode is deposited on the second part by vapor deposition.
3. The method for manufacturing an LED vertical chip assembly as described in claim 1, characterized in that, The step of filling the planarization layer between the passivation layers covering the red light vertical chip includes: The adhesive is spin-coated between the passivation layers covering the red vertical chip to form a planarization layer.
4. The method for manufacturing an LED vertical chip assembly as described in claim 3, characterized in that, The method of spin-coating adhesive material between the passivation layers covering the red vertical chip to form a planarization layer includes: BCB adhesive is spin-coated between the passivation layers covering the red vertical chip to form a planarization layer.
5. The method for manufacturing an LED vertical chip assembly as described in claim 1, characterized in that, The etching of the planarization layer and the passivation layer to expose the first electrode includes: The planarization layer and the passivation layer are dry etched using oxygen and carbon tetrafluoride at a concentration ratio of 10:1 to expose the first electrode; wherein the height of the etched planarization layer is consistent with the height of the red light vertical chip.
6. The method for manufacturing an LED vertical chip assembly as described in claim 1, characterized in that, The etching of the planarization layer and the passivation layer to expose the first electrode includes: The planarization layer and the passivation layer are dry etched using oxygen and carbon tetrafluoride at a concentration ratio of 15:1 to expose the first electrode; wherein the height of the etched planarization layer is consistent with the height of the red light vertical chip.
7. The method for manufacturing an LED vertical chip assembly as described in claim 1, characterized in that, The bonding of the target substrate to the bonding metal layer includes: Provide a target substrate; A metal layer is deposited on the target substrate; The metal layer is bonded to the bonding metal layer using a low-temperature bonding process, so that the target substrate is bonded to the bonding metal layer.
8. The method for manufacturing an LED vertical chip assembly as described in claim 1, characterized in that, The second semiconductor layer is a P-type semiconductor layer.
9. The method for manufacturing an LED vertical chip assembly as described in any one of claims 1-8, characterized in that, The doping element includes carbon or magnesium.
10. An LED vertical chip assembly, characterized in that, It is prepared using the LED vertical chip assembly fabrication method as described in any one of claims 1-9.