Gallium oxide vertical device and preparation method therefor
By employing epitaxial structures and low-temperature bonding technology, the crystal quality and interface characteristics of gallium oxide pn junction diodes were addressed, enabling efficient large-scale fabrication of high-quality gallium oxide pn heterojunction diodes and improving the device's breakdown voltage and reliability.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SUZHOU INST OF NANO TECH & NANO BIONICS CHINESE ACEDEMY OF SCI
- Filing Date
- 2025-11-27
- Publication Date
- 2026-06-04
AI Technical Summary
Existing technologies struggle to produce high-quality gallium oxide pn junction diodes due to issues with p-type oxide crystal quality and material interface characteristics, which prevent the full realization of the theoretical advantages of Ga2O3. Furthermore, devices fabricated through high-temperature bonding face challenges in terms of performance and reliability.
An epitaxial structure design is adopted, including a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region, an insertion layer, and a p-type nitride epitaxial layer. A high-quality pin structure is formed by low-temperature bonding, and Al elements are diffused under high pressure using the Al2O3/AlN insertion layer to improve the bonding interface quality and carrier concentration.
High-quality gallium oxide pn heterojunction diodes have been achieved, which improves the uniformity and reliability of the device, reduces the on-resistance, increases the depletion region width, and improves the breakdown voltage performance of the device, making it suitable for large-scale fabrication.
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Figure CN2025138197_04062026_PF_FP_ABST