A V-shaped cavity narrow linewidth semiconductor laser chip and a preparation method thereof

Abstract

The application provides a V-shaped cavity narrow linewidth semiconductor laser chip and a preparation method thereof, and belongs to the technical field of semiconductor laser chip preparation. The chip comprises a chip body, wherein the chip body comprises a substrate layer, an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer and an ohmic contact layer which are sequentially grown on the substrate layer; a V-shaped ridge waveguide comprises two ridge strips arranged in a V shape, the ridge strips are vertically arranged on the chip body and are composed of an unetched ohmic contact layer and an unetched P-type confinement layer; a Bragg grating is vertically arranged on one ridge strip; the two ridge strips of the V-shaped ridge waveguide are connected at the non-light-out cavity surface and are separated at the light-out cavity surface; a high-transmittance film layer is evaporated on the light-out cavity surface; and a high-reflection film layer is evaporated on the non-light-out cavity surface. The application improves the effective cavity length through the V-shaped cavity design, and realizes narrow linewidth, high output power and high side mode suppression ratio.

Description

Technical Field

[0001] This application belongs to the field of semiconductor laser chip fabrication technology, specifically relating to a V-cavity narrow-linewidth semiconductor laser chip and its fabrication method. Background Technology

[0002] Semiconductor lasers are widely used in industrial processing, medical aesthetics, information sensing, and optical communication due to their advantages of small size, high electro-optical conversion efficiency, and wide wavelength coverage. However, because semiconductor lasers are based on an interband recombination emission mechanism, they have a high spectral density and a high wavelength drift coefficient with temperature. Therefore, in many applications, spectral locking (i.e., mode-locking) of the laser emitted from the semiconductor laser chip is required. Currently, common mode-locking schemes mainly include external cavity mode-locking and on-chip integrated grating mode-locking.

[0003] External cavity mode-locking typically employs external volume Bragg gratings (VBGs) or fiber Bragg gratings to achieve wavelength locking, but this approach leads to increased overall laser size, structural complexity, and higher cost. In contrast, on-chip integrated Bragg grating solutions (such as distributed feedback (DFB) and distributed Bragg reflection (DBR) lasers) require no external components, have a compact structure, and are more suitable for integrated applications.

[0004] DBR lasers achieve direct wavelength locking by fabricating Bragg gratings in the non-output cavity surface region of the chip, thereby compressing spectral density and reducing temperature drift. However, traditional DBR lasers have long Bragg grating regions that cannot be injected with current, resulting in large chip size, warpage, and packaging difficulties. Furthermore, conventional semiconductor lasers use naturally curved surfaces as mirrors, leaving residual reflectivity on the cavity surface, which leads to a decrease in side-mode suppression ratio and poorer mode-locking performance. While DFB lasers have gratings distributed throughout the resonant cavity and lower losses, they require secondary epitaxial processes, resulting in complex fabrication, low yield, and a tendency to introduce lattice defects, affecting reliability and lifespan at high power.

[0005] Therefore, there is an urgent need for a semiconductor laser chip structure that can achieve narrow linewidth, high side-mode suppression ratio, small size, large cavity length, and high power output capability. Summary of the Invention

[0006] In a first aspect, embodiments of this application provide a V-cavity narrow-linewidth semiconductor laser chip, including a chip body, a V-ridge waveguide, a Bragg grating, an output cavity surface, and a non-output cavity surface; The chip body includes a substrate layer, and an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer and an ohmic contact layer grown sequentially on the substrate layer; The V-shaped ridge waveguide includes two ridges arranged in a V-shape, which are vertically disposed on the chip body and consist of an unetched ohmic contact layer and an unetched P-type confinement layer. A Bragg grating is vertically mounted on a ridge. The two ridges of the V-shaped ridge waveguide are connected at the non-outlet cavity surface and separated at the outlet cavity surface. The light-emitting cavity surface is coated with a high-reflection film layer; The non-light-emitting cavity surface is coated with a high-reflectivity film.

[0007] Furthermore, the included angle between the two ridges of the V-shaped ridge waveguide is 3° to 10°.

[0008] Furthermore, the Bragg grating includes several parallel and periodically arranged etch lines, the etching depth of which reaches the P-type waveguide layer.

[0009] Furthermore, the period of the etched lines The Prague condition must be met:

[0010] in, is the grating order, and its value is a positive integer; Output wavelength for the target; The effective refractive index of the waveguide containing the etched line structure; The Bragg grating is a first-order Bragg grating, a second-order Bragg grating, or a higher-order Bragg grating; wherein... Corresponding to a first-order Bragg grating, Corresponding to a second-order Bragg grating, Corresponding to a higher-order Bragg grating.

[0011] Furthermore, the reflectivity of the high antireflection film layer on the light-emitting cavity surface is less than 0.1%, and the reflectivity of the high reflectance film layer on the non-light-emitting cavity surface is greater than 95%.

[0012] Secondly, embodiments of this application also provide a method for fabricating a V-cavity narrow-linewidth semiconductor laser chip as described in the first aspect, comprising the following steps: S1. Provide a substrate, and sequentially epitaxially grow an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer, and an ohmic contact layer on the substrate; S2. A V-shaped ridge waveguide structure is formed in the ohmic contact layer and part of the P-type confinement layer through photolithography and etching processes; S3. A Bragg grating is fabricated on one ridge of a V-shaped ridge waveguide to generate several periodically arranged etching lines, and the etching depth is controlled to the P-shaped waveguide layer. S4. A non-optical cavity surface is prepared at the junction of the two ridges of the V-shaped ridge waveguide and a high-reflection film is deposited thereon. An optical cavity surface is prepared at the junction of the two ridges of the V-shaped ridge waveguide and a high-reflection film is deposited thereon.

[0013] Furthermore, the specific steps of step S1 are as follows: S11. Provide an N-type gallium arsenide substrate and perform cleaning and surface pretreatment; S12. Using a metal-organic chemical vapor deposition process, an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer, and an ohmic contact layer are epitaxially grown sequentially on the substrate.

[0014] Furthermore, the specific steps of step S2 are as follows: S21. Spin-coat photoresist onto the surface of the ohmic contact layer and expose it using a mask with a V-shaped pattern; the included angle of the V-shaped pattern is pre-designed to be 3°~10°; S22. Develop the exposed photoresist to generate a photoresist mask with a V-shaped opening; S23. Using a photoresist mask as a barrier layer, an inductively coupled plasma dry etching process is used to sequentially etch away the ohmic contact layer and part of the P-type confinement layer in the exposed area until the preset ridge height is reached; S24. Remove the remaining photoresist mask to generate a V-shaped ridge waveguide consisting of the remaining ohmic contact layer and P-type confinement layer.

[0015] Furthermore, the specific steps of step S3 are as follows: S31. Based on the target output wavelength Effective refractive index of waveguides containing etched line structures and the selected grating order Using the Bragg condition formula Calculate the period of the etched line ; S32. Coat the formed ridge surface with photoresist, and use holographic interference exposure or electron beam direct writing process to form a ridge with a period of... The grating pattern is transferred onto the photoresist to generate a photoresist grating mask; S33. Using a photoresist grating mask as a blocking layer, an etched line is generated on the selected ridge by reactive ion etching process. The etching depth is controlled by monitoring the etching time or endpoint so that the etched line reaches the P-type waveguide layer. S34. Use a resist remover to remove the residual photoresist mask to complete the fabrication of the Bragg grating.

[0016] Furthermore, the specific steps of step S4 are as follows: S41. The non-light-emitting cavity surface and the light-emitting cavity surface are generated using a cleavage process; S42. A high-reflectivity film layer is deposited on the non-light-emitting cavity surface using a physical vapor deposition process, wherein the high-reflectivity film layer has a reflectivity greater than 95%; S43. A high antireflection film is deposited on the light-emitting cavity surface using a physical vapor deposition process, wherein the reflectivity of the high antireflection film is less than 0.1%.

[0017] As can be seen from the above technical solutions, this application has the following advantages: The V-cavity narrow-linewidth semiconductor laser chip and its fabrication method provided in this application increase the effective resonant cavity length without increasing the chip's physical size by using a V-shaped ridge waveguide structure and a single-sided integrated Bragg grating. This achieves high output power, narrow linewidth, high side-mode suppression ratio, and excellent wavelength stability. Simultaneously, it avoids the complex secondary epitaxial process required by traditional DFB / DBR lasers, simplifying the manufacturing process and improving yield and reliability. Furthermore, by depositing a high-reflection film on the output cavity surface and a high-reflection film on the non-output cavity surface, it suppresses side-mode competition caused by residual reflection from natural cleavage surfaces, improving mode-locking performance. In addition, the V-shaped structure makes it difficult for stray light of non-Bragg center wavelengths to return to the resonant cavity and participate in oscillation, enhancing wavelength selectivity and spectral purity. Attached Figure Description

[0018] To more clearly illustrate the technical solution of this application, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a side view of the V-cavity narrow linewidth semiconductor laser chip of the present invention.

[0020] Figure 2 This is a top view of the V-cavity narrow-linewidth semiconductor laser chip of the present invention.

[0021] Figure 3 This is a schematic diagram of the optical path of the V-cavity narrow linewidth semiconductor laser chip of the present invention.

[0022] Figure 4 This is a schematic flowchart of the method for fabricating a V-cavity narrow-linewidth semiconductor laser chip according to the present invention.

[0023] Figure 5 This is a schematic diagram of the epitaxial structure of the chip body obtained by the method for preparing V-cavity narrow-linewidth semiconductor laser chips according to the present invention.

[0024] Among them, 110-chip body; 101-substrate layer; 102-N-type confinement layer; 103-N-type waveguide layer; 104-quantum layer; 105-P-type waveguide layer; 106-P-type confinement layer; 107-ohmic contact layer; 201-light-emitting cavity surface; 202-non-light-emitting cavity surface; 301-V-type ridge waveguide; 401-Bracket grating. Detailed Implementation

[0025] Various embodiments of this disclosure will be described more fully in the following detailed description of V-cavity narrow-linewidth semiconductor laser chips. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0026] For example, semiconductor lasers, with their advantages of small size, high electro-optic efficiency, and wide wavelength coverage, are widely used in industries such as industry, medicine, sensing, and communication. However, their inherent wide spectral characteristics and large temperature drift coefficient limit their application in high-precision scenarios, typically requiring mode-locking techniques to achieve wavelength stabilization. Existing mode-locking schemes mainly include external cavity schemes (such as bulk Bragg gratings or fiber gratings) and on-chip integrated gratings (such as DFB / DBR structures). While external cavity schemes are effective, they are large and costly; traditional DBR structures suffer from large chip sizes and warping due to excessively long passive grating regions, and residual reflections from naturally cleaved cavity surfaces degrade the side-mode suppression ratio; while DFBs, although high-performing, rely on complex secondary epitaxial processes, resulting in low yield and poor reliability, making it difficult to meet high-power requirements. Therefore, there is an urgent need for a novel semiconductor laser chip structure that combines narrow linewidth, high side-mode suppression ratio, compact size, large effective cavity length, and high power output capability.

[0027] To address the aforementioned issues, this embodiment provides a V-cavity narrow-linewidth semiconductor laser chip. By integrating a V-shaped ridge waveguide with a single-sided Bragg grating, the effective cavity length and wavelength selectivity are significantly improved, achieving narrow linewidth, high power, high SMSR without the need for secondary epitaxy.

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Please see Figure 1 and Figure 2The diagram shown is a schematic of a V-cavity narrow linewidth semiconductor laser chip in a specific embodiment. The chip includes a chip body 110, a V-ridge waveguide 301, a Bragg grating 401, an output cavity surface 201, and a non-output cavity surface 202. The chip body 110 includes a substrate layer 101, and an N-type confinement layer 102, an N-type waveguide layer 103, a quantum layer 104, a P-type waveguide layer 105, a P-type confinement layer 106 and an ohmic contact layer 107 sequentially grown on the substrate layer 101. The V-shaped ridge waveguide 301 includes two ridges arranged in a V-shape. The ridges are vertically disposed on the chip body 110 and are composed of an unetched ohmic contact layer 107 and an unetched P-type confinement layer 106. The Bragg grating 401 is vertically mounted on a ridge. The two ridges of the V-shaped ridge waveguide 301 are connected at the non-light-emitting cavity surface 202 and separated at the light-emitting cavity surface 201. The light-emitting cavity surface 201 is coated with a high-reflection film layer; The non-light-emitting cavity surface 202 is coated with a high-reflectivity film.

[0030] This embodiment integrates a V-shaped ridge waveguide 301, a Bragg grating 401, and high and low reflection cavity surfaces, achieving small size, large effective cavity length, high side-mode suppression ratio, and narrow linewidth output.

[0031] Specifically, the included angle (i.e., the V-angle) between the two ridges of the V-shaped ridge waveguide 301 is precisely designed to be 6. This angle range (usually 3) 10 The key to achieving the technical effect of this application is that, on the one hand, the angle is small enough to allow the laser to undergo total internal reflection or high reflectivity propagation in the V-shaped cavity, effectively folding the linear cavity length. With the physical length of the chip remaining unchanged, the effective optical path length (i.e., effective cavity length) of the photon in the resonant cavity is increased by more than 2 times, which is equivalent to doubling the gain area, thus laying the foundation for increasing the output power. On the other hand, the angle makes the ridge and the output cavity surface 201 form a non-perpendicular angle, so that the stray light generated by the residual reflectivity of the cavity surface and the non-Bracket center wavelength cannot return to the waveguide core layer of another ridge along the original path. This avoids the competition between these side modes and the main mode in the gain region and significantly improves the side mode suppression ratio.

[0032] The Bragg grating 401 is fabricated on one of its ridges, consisting of a series of parallel and periodically arranged etched lines. The etched lines are formed using a dry etching process, penetrating the upper ohmic contact layer 107 and the P-type confinement layer 106, ultimately reaching the P-type waveguide layer 105. Etching the grating to the waveguide layer strongly modulates the optical field distribution and equivalent refractive index in that region, thereby providing highly selective wavelength feedback. The grating period Λ strictly adheres to the Bragg condition, depending on the target wavelength (e.g., 1550 nm), the effective refractive index of the waveguide, and the selected grating order. Design it to achieve locking onto a specific wavelength.

[0033] A high-reflectance film is deposited on the light-emitting cavity surface 201, with its reflectivity controlled at 0.1%; this minimizes cavity surface reflection loss, promotes efficient laser output, and allows light of non-selected wavelengths to escape from this surface. A high-reflectance film is deposited on the non-light-emitting cavity surface 202, with a reflectivity higher than 95%, which, together with the Bragg grating 401, forms the high-reflection end of the resonant cavity, ensuring photon density and lasing efficiency within the cavity.

[0034] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, another V-cavity narrow linewidth semiconductor laser chip is provided, which includes a chip body 110, a V-ridge waveguide 301, a Bragg grating 401, a light-emitting cavity surface 201, and a non-light-emitting cavity surface 202. The chip body 110 includes a substrate layer 101, and an N-type confinement layer 102, an N-type waveguide layer 103, a quantum layer 104, a P-type waveguide layer 105, a P-type confinement layer 106 and an ohmic contact layer 107 sequentially grown on the substrate layer 101. The V-shaped ridge waveguide 301 includes two ridges arranged in a V-shape. The ridges are vertically disposed on the chip body 110 and are composed of an unetched ohmic contact layer 107 and an unetched P-type confinement layer 106. The Bragg grating 401 is vertically mounted on a ridge. The two ridges of the V-shaped ridge waveguide 301 are connected at the non-light-emitting cavity surface 202 and separated at the light-emitting cavity surface 201. The light-emitting cavity surface 201 is coated with a high-reflection film layer; The non-light-emitting cavity surface 202 is coated with a high-reflectivity film layer. The included angle between the two ridges of the V-shaped ridge waveguide 301 is 3°~10°; The period of the etched line The Prague condition must be met:

[0035] in, is the grating order, and its value is a positive integer; Output wavelength for the target; The effective refractive index of the waveguide containing the etched line structure; The Bragg grating 401 is a first-order Bragg grating, a second-order Bragg grating, or a higher-order Bragg grating; wherein... Corresponding to a first-order Bragg grating, Corresponding to a second-order Bragg grating, Corresponding to higher-order Bragg gratings; The reflectivity of the high-reflection film layer on the light-emitting cavity surface 201 is less than 0.1%, and the reflectivity of the high-reflection film layer on the non-light-emitting cavity surface 202 is greater than 95%. The optical path of this application is as follows: Figure 3 As shown.

[0036] Combination Figure 3 The schematic diagram of the optical path shown illustrates the working principle of this chip as follows: When current is injected into the active region (i.e., quantum layer 104) through the electrodes, stimulated emission photons are generated. These photons oscillate within a composite resonant cavity comprised of a high-reflectivity film (non-emitting cavity surface 202), a V-shaped ridge waveguide 301, a Bragg grating 401, and a high-reflection antireflection film (emitting cavity surface 201). The Bragg grating 401 acts as a wavelength selector, providing strong distributed reflection only to the center wavelength λB that satisfies the Bragg condition, thus establishing stable oscillations within the cavity. Light of other wavelengths cannot obtain effective feedback from the grating because it does not meet the Bragg condition.

[0037] The V-shaped structure serves a dual filtering function: firstly, its folded path increases the effective cavity length, naturally compressing the longitudinal mode spacing, which is beneficial for single-mode operation; secondly, as mentioned above, its inclined ridges make it geometrically difficult for non-λB sidemode light reflected from the output cavity surface 201 to couple back into the waveguide of another ridge (i.e., "deflection"), thus preventing them from completing a full round-trip oscillation and effectively suppressing them. Therefore, only light with the Bragg center wavelength λB can achieve low-loss, high-gain resonance within this V-shaped composite cavity, ultimately outputting laser light with extremely narrow linewidth and extremely high sidemode suppression ratio from the output cavity surface 201.

[0038] like Figure 4 As shown, the following are embodiments of the method for fabricating a V-cavity narrow-linewidth semiconductor laser chip provided by this disclosure. This method and the method for fabricating a V-cavity narrow-linewidth semiconductor laser chip in the above embodiments belong to the same inventive concept. For details not described in detail in the embodiments of the method for fabricating a V-cavity narrow-linewidth semiconductor laser chip, please refer to the embodiments of the V-cavity narrow-linewidth semiconductor laser chip described above.

[0039] The method includes the following steps: S1. Provide a substrate, and sequentially epitaxially grow an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer, and an ohmic contact layer on the substrate; It should be noted that completing the growth of all functional layers in one go avoids introducing defects through secondary epitaxy, improves material quality and device reliability, and is especially suitable for high-power applications; S2. A V-shaped ridge waveguide structure is formed in the ohmic contact layer and part of the P-type confinement layer through photolithography and etching processes; It should be noted that this step uses photolithography and dry etching to define the V-shaped ridge, which has strong process compatibility and high precision. It can precisely control the ridge width, height and angle to ensure the symmetry and optical performance of the double-ridge waveguide. S3. A Bragg grating is fabricated on one ridge of a V-shaped ridge waveguide to generate several periodically arranged etching lines, and the etching depth is controlled to the P-shaped waveguide layer. It should be noted that in this step, the grating is directly etched onto the already formed ridge, without the need for additional alignment or regrowth; the depth reaches the P-type waveguide layer, enhancing the interaction between the grating and the guided mode and improving the wavelength locking capability; S4. A non-optical cavity surface is prepared at the junction of the two ridges of the V-shaped ridge waveguide and a high-reflection film is deposited thereon; and an optical cavity surface is prepared at the junction of the two ridges of the V-shaped ridge waveguide and a high-reflection film is deposited thereon. It should be noted that this step involves cleaving to obtain an atomically flat cavity surface, and PVD coating to achieve extreme reflectivity control, thereby realizing the control of an ideal unidirectional resonant cavity, maximizing the master mode gain and suppressing parasitic oscillations.

[0040] This embodiment uses a V-cavity structure to extend the effective resonant length, and combines a high-reflection / anti-reflection film with a deeply etched Bragg grating to effectively suppress side modes and stabilize the wavelength, achieving narrow linewidth, high output power and high side mode suppression ratio, while simplifying the process and improving yield.

[0041] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, another method for fabricating a V-cavity narrow-linewidth semiconductor laser chip is provided, which includes the following steps: S1. Provide a substrate, and sequentially epitaxially grow an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer, and an ohmic contact layer on the substrate; the specific steps of step S1 are as follows: S11. Provide an N-type gallium arsenide substrate and perform cleaning and surface pretreatment; S12. Using a metal-organic chemical vapor deposition process, an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer, and an ohmic contact layer are sequentially epitaxially grown on the substrate; such as Figure 5 As shown; S2. A V-shaped ridge waveguide structure is formed in the ohmic contact layer and part of the P-type confinement layer through photolithography and etching processes; the specific steps of step S2 are as follows: S21. Spin-coat photoresist onto the surface of the ohmic contact layer and expose it using a mask with a V-shaped pattern; the included angle of the V-shaped pattern is pre-designed to be 3°~10°; S22. Develop the exposed photoresist to generate a photoresist mask with a V-shaped opening; S23. Using a photoresist mask as a barrier layer, an inductively coupled plasma dry etching process is used to sequentially etch away the ohmic contact layer and part of the P-type confinement layer in the exposed area until the preset ridge height is reached; S24. Remove the remaining photoresist mask to generate a V-shaped ridge waveguide consisting of the remaining ohmic contact layer and P-type confinement layer; Key points of the process in step S2: using an included angle of 6 (Can be found in 3) 10 By using a V-shaped pattern mask with internal adjustment and precisely controlling process parameters (such as Cl2 / BCl3 mixed gas, RF power, and etching time) during ICP etching, a V-shaped ridge waveguide with steep sidewalls and controllable morphology can be formed. The etching stops at a preset depth in the P-type confinement layer to ensure that the ridge has sufficient carrier confinement and optical field confinement capabilities, while maintaining the integrity of the underlying P-type waveguide layer, thus preparing for subsequent grating etching. S3. Fabricate a Bragg grating on one ridge of the V-shaped ridge waveguide, generating several periodically arranged etching lines, controlling the etching depth to the P-shaped waveguide layer; the specific steps of step S3 are as follows: S31. Based on the target output wavelength Effective refractive index of waveguides containing etched line structures and the selected grating order Using the Bragg condition formula Calculate the period of the etched line ; S32. Coat the formed ridge surface with photoresist, and use holographic interference exposure or electron beam direct writing process to form a ridge with a period of... The grating pattern (i.e., the pattern of equally spaced parallel lines) is transferred onto the photoresist to generate a photoresist grating mask; S33. Using a photoresist grating mask as a blocking layer, an etched line is generated on the selected ridge by reactive ion etching process. The etching depth is controlled by monitoring the etching time or endpoint so that the etched line reaches the P-type waveguide layer. S34. Use a resist remover to remove the residual photoresist mask and complete the fabrication of the Bragg grating; Key process points and design considerations for step S3: Effective refractive index of the waveguide in step S31 The value needs to be determined through theoretical calculations (such as the equivalent refractive index method) or software simulation. It incorporates the perturbations caused by the refractive index of each layer of the chip material and the depth of the etching lines. For example, for a target wavelength of 1550nm, if a second-order Bragg grating (m=2) is used in the design, and the calculated value is... If ≈3.2, then the grating period Λ is approximately 484nm; The etching depth to the P-type waveguide layer in step S33 is the core of this application. By using reactive ion etching and a endpoint detection system (such as monitoring the spectral intensity change of a specific etched product), the etching depth can be precisely controlled to reach the surface of the P-type waveguide layer. This allows the refractive index modulation of the grating to directly act on the waveguide region with the strongest optical field intensity, greatly enhancing the coupling coefficient and wavelength selectivity of the grating, thereby achieving a better wavelength locking effect and narrower linewidth output. Compared to the grating located in the passive region in traditional DBR lasers, this application integrates the grating onto the active waveguide ridge, achieving a combination of structural compactness and functional efficiency. S4. A non-emitting cavity surface is fabricated at the junction of the two ridges of the V-shaped ridge waveguide, and a high-reflectivity film is deposited thereon; an emitting cavity surface is fabricated at the junction of the two ridges of the V-shaped ridge waveguide, and a high-antireflection film is deposited thereon. The specific steps of step S4 are as follows: S41. The non-light-emitting cavity surface and the light-emitting cavity surface are generated using a cleavage process; S42. A high-reflectivity film layer is deposited on the non-light-emitting cavity surface using a physical vapor deposition process, wherein the high-reflectivity film layer has a reflectivity greater than 95%; S43. A high-reflection coating is deposited on the light-emitting cavity surface using a physical vapor deposition process, wherein the reflectivity of the high-reflection coating is less than 0.1%; Key points of step S4: The cleavage process utilizes the crystal orientation characteristics of semiconductor materials to obtain atomically flat and perpendicular cavity surfaces, which is the foundation of low-loss optical resonators. When depositing high-reflectivity films (such as SiO2 / TiO2 multilayer dielectric films) and high-reflection films (such as single-layer Al2O3 or MgF2), the film thickness needs to be controlled in real time through an optical monitoring system to ensure that the reflectivity accurately meets the technical specifications (>95% and <0.1%). This extreme contrast in reflectivity, combined with the V-shaped cavity and Bragg grating, constructs a highly unidirectional and wavelength-selective resonator, ultimately enabling the chip to simultaneously achieve excellent comprehensive performance with small size, large effective cavity length, high output power, narrow linewidth, and high side-mode rejection ratio.

[0042] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0043] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A V-cavity narrow-linewidth semiconductor laser chip, characterized in that, This includes the chip body, V-shaped ridge waveguide, Bragg grating, light-emitting cavity surface, and non-light-emitting cavity surface; The chip body includes a substrate layer, and an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer and an ohmic contact layer grown sequentially on the substrate layer; The V-shaped ridge waveguide includes two ridges arranged in a V-shape, which are vertically disposed on the chip body and consist of an unetched ohmic contact layer and an unetched P-type confinement layer. A Bragg grating is vertically mounted on a ridge. The two ridges of the V-shaped ridge waveguide are connected at the non-outlet cavity surface and separated at the outlet cavity surface. The light-emitting cavity surface is coated with a high-reflection film layer; The non-light-emitting cavity surface is coated with a high-reflectivity film.

2. The V-cavity narrow-linewidth semiconductor laser chip according to claim 1, characterized in that, The angle between the two ridges of a V-shaped ridge waveguide is 3° to 10°.

3. The V-cavity narrow-linewidth semiconductor laser chip according to claim 1, characterized in that, The Bragg grating includes several parallel and periodically arranged etch lines, the etching depth of which reaches the P-type waveguide layer.

4. The V-cavity narrow-linewidth semiconductor laser chip according to claim 3, characterized in that, The period of the etched line The Prague condition must be met: in, is the grating order, and its value is a positive integer; Output wavelength for the target; The effective refractive index of the waveguide containing the etched line structure; The Bragg grating is a first-order Bragg grating, a second-order Bragg grating, or a higher-order Bragg grating; wherein... Corresponding to a first-order Bragg grating, Corresponding to a second-order Bragg grating, Corresponding to a higher-order Bragg grating.

5. The V-cavity narrow-linewidth semiconductor laser chip according to claim 1, characterized in that, The reflectivity of the high-reflection coating on the light-emitting cavity surface is less than 0.1%, and the reflectivity of the high-reflection coating on the non-light-emitting cavity surface is greater than 95%.

6. A method for fabricating a V-cavity narrow-linewidth semiconductor laser chip as described in any one of claims 1-5, characterized in that, Includes the following steps: S1. Provide a substrate, and sequentially epitaxially grow an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer, and an ohmic contact layer on the substrate; S2. A V-shaped ridge waveguide structure is formed in the ohmic contact layer and part of the P-type confinement layer through photolithography and etching processes; S3. A Bragg grating is fabricated on one ridge of a V-shaped ridge waveguide to generate several periodically arranged etching lines, and the etching depth is controlled to the P-shaped waveguide layer. S4. A non-optical cavity surface is prepared at the junction of the two ridges of the V-shaped ridge waveguide and a high-reflection film is deposited thereon. An optical cavity surface is prepared at the junction of the two ridges of the V-shaped ridge waveguide and a high-reflection film is deposited thereon.

7. The method according to claim 6, characterized in that, The specific steps of step S1 are as follows: S11. Provide an N-type gallium arsenide substrate and perform cleaning and surface pretreatment; S12. Using a metal-organic chemical vapor deposition process, an N-type confinement layer, an N-type waveguide layer, a quantum layer, a P-type waveguide layer, a P-type confinement layer, and an ohmic contact layer are epitaxially grown sequentially on the substrate.

8. The method according to claim 6, characterized in that, The specific steps of step S2 are as follows: S21. Spin-coat photoresist onto the surface of the ohmic contact layer and expose it using a mask with a V-shaped pattern; the included angle of the V-shaped pattern is pre-designed to be 3°~10°; S22. Develop the exposed photoresist to generate a photoresist mask with a V-shaped opening; S23. Using a photoresist mask as a barrier layer, an inductively coupled plasma dry etching process is used to sequentially etch away the ohmic contact layer and part of the P-type confinement layer in the exposed area until the preset ridge height is reached; S24. Remove the remaining photoresist mask to generate a V-shaped ridge waveguide consisting of the remaining ohmic contact layer and P-type confinement layer.

9. The method according to claim 6, characterized in that, The specific steps of step S3 are as follows: S31. Based on the target output wavelength Effective refractive index of waveguides containing etched line structures and the selected grating order Using the Bragg condition formula Calculate the period of the etched line ; S32. Coat the formed ridge surface with photoresist, and use holographic interference exposure or electron beam direct writing process to form a ridge with a period of... The grating pattern is transferred onto the photoresist to generate a photoresist grating mask; S33. Using a photoresist grating mask as a blocking layer, an etched line is generated on the selected ridge by reactive ion etching process. The etching depth is controlled by monitoring the etching time or endpoint so that the etched line reaches the P-type waveguide layer. S34. Use a resist remover to remove the residual photoresist mask to complete the fabrication of the Bragg grating.

10. The method according to claim 6, characterized in that, The specific steps of step S4 are as follows: S41. The non-light-emitting cavity surface and the light-emitting cavity surface are generated using a cleavage process; S42. A high-reflectivity film layer is deposited on the non-light-emitting cavity surface using a physical vapor deposition process, wherein the high-reflectivity film layer has a reflectivity greater than 95%; S43. A high antireflection film is deposited on the light-emitting cavity surface using a physical vapor deposition process, wherein the reflectivity of the high antireflection film is less than 0.1%.

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