Vertical JFET (Junction Field Effect Transistor) power device for enhancing gate end driving capability by ohmic contact

Abstract

The invention discloses a vertical JFET (Junction Field Effect Transistor) power device for enhancing gate end driving capability by ohmic contact and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. In order to solve the problem of poor switching performance caused by high electrical resistivity of a grid active region and serious attenuation of a driving signal in the existing vertical JFET, the invention provides a metal ohmic contact layer (such as nickel) formed on the surface of the grid active region. And the low-resistance metal layer is connected in parallel with the grid electrode P region, and an efficient current path from the grid electrode contact end to each grid junction in the chip is constructed, so that the grid electrode resistance is greatly reduced, and the grid end driving capability is enhanced. According to the manufacturing method, an ohmic contact preparation step in the prior art is utilized, introduction of non-compatible materials such as polycrystalline silicon and complex procedures is not needed, and gate source short circuit is reliably prevented through the design of selectively reserving an insulating layer above a gate region. According to the invention, the switching speed and reliability of the device are improved, and excellent process compatibility and cost advantages are maintained.

Description

Technical Field

[0001] This invention relates to a power device, and more particularly to a vertical JFET (junction field-effect transistor) power device that enhances gate-end drive capability with ohmic contacts. Background Technology

[0002] Vertical JFETs (junction field-effect transistors) are semiconductor devices commonly used in high-voltage, high-power applications. Their typical structure is as follows: [The text abruptly ends here, likely due to an incomplete sentence or missing information.] The substrate, serving as the drain active region, is formed on the N-type epitaxial layer via ion implantation. The source electrode has an active region, and grooves are etched on both sides of it, and the electrode is injected into the same process window. Impurities form the gate active region at the bottom of the trench. In this structure, when a negative voltage is applied to the gate, the negative bias voltage formed between the gate and source will cause the space charge region to expand, thereby blocking the N-type channel and realizing the turn-off function of the normally open JFET.

[0003] However, the above structure has significant drawbacks in practical applications. Because the exposed source metal region needs to span almost the entire cell to reduce on-resistance, to avoid gate-source short circuits, the exposed gate metal region can only be located at the chip edge. Therefore, the gate drive signal must propagate from the edge, sequentially passing through the gate metal layer, via, gate ohmic contact layer, and then along the gate active region (…). The gate active region extends laterally to each cell. The gate active region is typically a silicon carbide region heavily doped with acceptor impurities. The high resistivity of the gate front end, coupled with the long signal propagation path, results in a large equivalent resistance at the gate front end, which severely restricts the gate driving capability of the device. This causes distortion in the pulse width modulation (PWM) waveform during propagation, especially in the internal chip area far from the gate contact point, resulting in a power supply collapse effect. This causes the actual falling edge of the driving voltage obtained by the cells in the terminal area to slow down, which may cause the local channel to fail to turn off completely, increasing the risk of device leakage.

[0004] To address these issues, existing technologies primarily propose two solutions: one is to shorten the gate active region length by reducing the total device area, thereby lowering resistance and improving drive capability. However, this method leads to increased on-resistance and exacerbated heat generation. The other is to deposit a layer of polysilicon on the gate active region, utilizing the higher conductivity of polysilicon to reduce overall resistance. However, the polysilicon approach is incompatible with conventional JFET fabrication processes, as standard JFET flows typically do not include polysilicon deposition and etching steps. Forcibly introducing this process not only requires the purchase of dedicated photomasks, increasing fabrication costs, but also, due to the trenches and uneven morphology on the JFET surface, the deposition and etching effect of polysilicon on non-planar surfaces is difficult to guarantee, potentially necessitating additional process adjustments, further increasing manufacturing costs and process complexity.

[0005] Therefore, existing vertical JFET power devices still face many shortcomings in improving gate drive capability, such as structural constraints, poor material compatibility, and high process costs. There is an urgent need for a new technical solution that can effectively reduce gate resistance without significantly increasing process complexity and cost. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention replaces polysilicon, which is incompatible with conventional JFET fabrication processes, with nickel. Nickel is a metal, and although its price is sometimes twice that of polysilicon, its sheet resistance is lower, and it does not introduce additional process steps. Therefore, it is more suitable for reducing the gate active region resistance to enhance the gate drive capability of vertical JFETs. The technical solution is as follows: A method for manufacturing a vertical JFET power device with enhanced gate-end drive capability using ohmic contacts, characterized by comprising the following steps: S1: Provides a substrate and an epitaxial layer having a first conductivity type; S2: Global ion implantation is performed on the upper surface of the epitaxial layer to form a heavily doped source active region; S3: Under the protection of the first masking layer, trenches are etched in the epitaxial layer; S4: Using the same first masking layer as in step S3, ion implantation is performed into the bottom of the trench to form a heavily doped gate active region; S5: Globally sputter metal layers onto the surfaces of the source active region and the gate active region to form their respective ohmic contacts, and the ohmic contacts of the source and the gate are isolated from each other. S6: Globally deposit a second masking layer on the device surface where ohmic contacts are completed; S7: In the region corresponding to the area directly above the source active region, the second masking layer is selectively etched to form a source region via that exposes the source ohmic contact, while retaining the entire second masking layer covering the source metal layer directly above the gate active region and directly below it. S8: Form a source metal layer that is electrically connected to the source ohmic contact and a gate metal layer that is electrically connected to the gate ohmic contact located in the edge region of the device.

[0007] Preferably, in step S5, the globally sputtered metal layer is nickel.

[0008] Preferably, the second masking layer mentioned in step S6 is a second insulating layer deposited directly after the ohmic contact is formed in step S5, and its material is different from the insulating material of the masking layer used in steps S3 to S5.

[0009] Preferably, before step S5, the method further includes the following step: S4a: After etching trenches and implanting to form the gate active region, a first masking layer is deposited on the device surface and etched to form an initial via leading to the entire source active region and gate active region. In step S5, the globally sputtered metal layer covers the surface of the first masking layer and the bottom and sidewalls of the initial via, and forms an ohmic contact with the semiconductor active region at the bottom of the via through a self-aligned process.

[0010] Preferably, the first masking layer is a residual portion of the masking layer used in step S3 or a separately deposited masking layer.

[0011] Preferably, in step S7, when selectively etching the second masking layer to form a source region via, a gate contact hole leading to the gate ohmic contact is simultaneously etched at the device edge corresponding to the position where the gate metal layer is connected.

[0012] Preferably, in step S7, the entire second masking layer covering the source metal layer directly above the gate active region is retained. The purpose of this is to achieve electrical isolation between the subsequently formed source metal layer and the gate active region and its surface metal ohmic contact, thereby preventing gate-source short circuit.

[0013] The present invention also discloses a vertical JFET power device manufactured by the above method, characterized in that it comprises: The heavily doped gate active region located at the bottom of the trench is covered with a metal ohmic contact layer. A complete insulating layer structure covering the gate active region and its metal ohmic contact layer, which isolates the source metal layer of the device from the gate active region. The metal ohmic contact layer, extending from the gate contact point at the edge of the device to the active gate region of each internal cell, together constitutes a metal conduction path for reducing gate resistance and enhancing gate drive capability.

[0014] Preferably, the material of the metal ohmic contact layer is nickel.

[0015] The present invention also discloses a high-power circuit structure, characterized by the above-described vertical JFET power device obtained by the above method. Beneficial effects

[0016] 1. By forming a metal ohmic contact layer (such as nickel) on the surface of the active region of the gate and extending it from the edge of the device into each internal cell, a low-resistance metal conduction path is provided for the gate signal. This significantly reduces the equivalent series resistance from the gate metal contact point to the internal channel PN junction. This method directly and effectively overcomes the core defects of the prior art, such as gate drive signal attenuation and distortion caused by the high resistivity and long path of the P+ region. Its technical effect is not simply optimization, but rather, by introducing a metal layer as a high-conductivity medium, it fundamentally changes the gate current conduction mechanism, enabling the device to respond quickly and completely to high-frequency PWM signals, reducing switching delay and waveform distortion, thereby reducing switching losses and potential channel leakage risks.

[0017] 2. The manufacturing method described utilizes and integrates the existing "ohmic contact formation" step in the conventional vertical JFET fabrication process. It only requires specifying the material as a metal (such as nickel) and adjusting the corresponding pattern design, without introducing entirely new polysilicon deposition and etching modules incompatible with JFET processes. This solution creatively combines the function of "reducing gate resistance" with the process objective of "forming ohmic contacts," avoiding the significant increases in manufacturing costs and defect rates associated with using polysilicon, which necessitates the additional purchase of photomasks, complex processes, and the challenges of non-planar processes (the core drawback of polysilicon solutions in the background art). It demonstrates that without overturning the existing mature process framework, a leap in performance can be achieved through clever material substitution and process design, exhibiting extremely high industrial applicability and economic efficiency.

[0018] 3. By globally depositing and selectively etching an insulating layer after forming the metal ohmic contact layer, the insulating layer covering the gate active region is strictly guaranteed to remain intact and not be etched through. This ensures reliable electrical isolation between the subsequently formed, large-area source metal layer and the gate region. This structural design cleverly solves the contradictory problem of how to avoid fatal gate-source short circuits caused by contact between the source metal layer and the metal layer while reducing gate resistance using the metal layer. It is not a simple isolation, but rather a solution achieved through precise design and control of the existing multilayer insulating dielectric photolithography steps without adding any additional isolation structures or processes. This improves performance while strictly ensuring the device's basic functions and reliability, demonstrating a high degree of integration and ingenuity at the design level.

[0019] 4. Due to the fundamentally enhanced gate drive capability, designers can allow for larger cell areas or wider channels without excessively sacrificing switching performance. This breaks the traditional contradiction and performance trade-off between "reducing area to lower gate resistance" and "increasing area to reduce on-resistance and heat generation" in the prior art. This invention enables devices to simultaneously achieve low on-resistance and strong gate drive capability, providing new design freedom for developing power devices with higher current capacity and lower heat loss, which is beneficial for improving the efficiency and power density of the entire power system. Attached Figure Description

[0020] Figure 1 The image shows the square shape of the source active region (left) and the square shape of the gate active region (right) in the power device of the present invention. Figure 2 This is a schematic diagram of the design process of a vertical JFET (junction field-effect transistor) power device that enhances gate-end driving capability using ohmic contacts, as per the present invention. Detailed Implementation Example

[0021] The following is a complete and coherent description of each manufacturing step, integrating implementation methods, design principles, and technical effects: Step S1: Provide a substrate and an epitaxial layer having a first conductivity type. First, heavily doped N-type ( A silicon carbide monocrystalline wafer is used as the substrate, which directly serves as the drain of the device to provide a low-resistance current output path. A lightly doped N-type silicon carbide (SiC) layer is grown on top of this substrate using epitaxial growth techniques, with precise control over thickness and doping concentration. The silicon carbide epitaxial layer is crucial. This epitaxial layer bears the primary voltage during the device's off-state, and its thickness and doping distribution directly determine the device's reverse blocking voltage capability. This step forms the foundation of vertical power devices, laying the groundwork for the subsequent formation of vertical conductive channels and the ability to withstand high voltages.

[0022] Step S2: Perform global ion implantation on the upper surface of the epitaxial layer to form a heavily doped source active region. A uniform heavy doping layer is formed by implanting N-type impurities with a high dose of ions across the entire epitaxial layer surface. The region, i.e., the active region of the source, is the target area for global implantation. This global implantation aims to ensure extremely low contact resistance at the subsequent source metal contact. High doping concentration facilitates the formation of ohmic contacts at the metal-semiconductor interface, significantly reducing the series resistance at the device source end. Simultaneously, this implanted layer provides a clear surface doping reference for subsequent trench etching.

[0023] Step S3: Under the protection of the first masking layer, trenches are etched in the epitaxial layer. An insulating masking layer (such as silicon dioxide) is fabricated on the surface and patterned using photolithography to define the trench region. Subsequently, a dry etching technique is employed to vertically etch downwards through the source active region and into the trench area. An epitaxial layer is formed to a certain depth, creating a trench structure with steep sidewalls. The trench depth precisely controls the effective length of the future conductive channel, which is one of the key dimensions determining the device's threshold voltage and on-resistance. This step completes the transformation from a planar structure to a three-dimensional trench structure, creating space for constructing vertical channels and gate junctions.

[0024] Step S4: Using the same first masking layer as in step S3, ion implantation is performed into the bottom of the trench to form a heavily doped gate active region. This step embodies key innovations in process integration and cost control. Without stripping the trench etching masking layer used in step S3, it is directly used as an injection mask to inject P-type impurities into the exposed trench bottom, forming a heavily doped layer. Gate active region. Etching and implantation are performed sequentially within the same process window, achieving perfect self-alignment of the gate active region relative to the trench. This ensures precise and consistent gate PN junction positioning, greatly improving the uniformity and controllability of device parameters.

[0025] Step S5: Globally sputter metal layers onto the surfaces of the source active region and the gate active region to form their respective ohmic contacts. This step is the core innovation of this invention, directly addressing the shortcomings of existing technologies. A thin metal film, preferably nickel (Ni), is globally sputtered onto the entire surface of the cleaned device (including the inner walls and bottom of the trench), followed by annealing to fuse it with the underlying... Source region and The gate semiconductor reacts to form low-resistance ohmic contacts. Nickel has extremely low sheet resistance, which... The nickel silicide ohmic contact layer formed on the surface of the gate active region is essentially on top of the original high resistivity. A low-resistance metallic conductive path is connected in parallel across the silicon carbide region. This fundamentally and significantly reduces the equivalent resistance from the gate contact to the gate junctions at various points within the chip. This solution cleverly combines the function of "reducing gate resistance" with the step of "forming ohmic contacts" in conventional processes, completely avoiding the introduction of non-standard, expensive, and poorly compatible polysilicon deposition and etching processes. This achieves a performance breakthrough while ensuring the economic efficiency and feasibility of manufacturing.

[0026] Step S6: Globally deposit a second masking layer on the device surface where ohmic contacts have been completed. After forming the ohmic contact layer, a relatively thick insulating dielectric layer (such as silicon nitride) is conformally deposited across the entire device surface using methods such as chemical vapor deposition to serve as the interlayer dielectric. This insulating layer provides an insulating foundation for subsequent metal interconnects and also protects the sensitive ohmic contact interface below from contamination or damage. Its global coverage is a prerequisite for achieving reliable selective etching subsequently.

[0027] Step S7: Selectively etch the second masking layer to expose the source region contact, while completely preserving the masking layer above the gate region. Through photolithography and etching processes, the second masking layer deposited in step S6 is selectively removed only in areas where the source metal needs to be connected, exposing the underlying source ohmic contact layer and forming source contact holes. The key design element of this step is that the second masking layer is deliberately and completely preserved without etching in the area directly above and below the source metal layer of all gate active regions. This design forms a crucial insulating isolation structure. The principle is that the subsequent large-area source metal layer can only connect to the source through the source contact holes, while the gate region covered by the complete masking layer physically isolates the source metal layer. Thus, while successfully utilizing a low-resistivity metal layer (nickel) to enhance the internal conductivity of the gate, short circuits between the source metal and the gate region are reliably prevented, resolving the contradiction between performance improvement and electrical isolation.

[0028] Step S8: Form the source metal layer and the gate metal layer with edge connection respectively. Finally, electrode interconnects are formed through metal deposition and patterning processes. A source metal layer (such as aluminum) fills the source region contact holes and covers a large area of ​​the chip's central region, achieving low-resistance connections with all source cells. The gate metal layer, at specific locations on the chip edge, is connected to a gate ohmic contact layer (nickel) extending to those locations via specially etched contact holes. After the drive signal is injected from the edge gate metal, it can be quickly and uniformly transmitted to every gate PN junction inside the chip through the low-resistance gate ohmic contact metal network, achieving powerful and synchronous driving of all chip channels.

[0029] In summary, this embodiment first selects heavily doped N-type ( Silicon carbide single-crystal wafers are used as substrates to provide a low-resistance drain current path, and lightly doped N-type silicon carbide (SiC) crystals are grown on them. A silicon carbide epitaxial layer is used to withstand high voltage. This vertical structure is the basis for achieving high blocking voltage and low specific on-resistance in the device; if a lateral structure or uniform doping is used, it will be impossible to simultaneously meet the requirements of high voltage and low loss, resulting in a fundamental loss of device performance. Subsequently, heavy doping is formed on the entire surface of the epitaxial layer through high-dose ion implantation. The source active region is designed to ensure extremely low source contact resistance while avoiding the additional photolithography steps and alignment errors required for selective implantation. While selective implantation can save on implantation dose, it increases mask costs and introduces alignment deviation risks.

[0030] Next, dry etching is performed under the patterned masking layer (such as silicon dioxide) to form a trench structure with steep sidewalls. This step realizes the transformation from planar to three-dimensional trenches and defines the channel length; if the trench morphology is not well controlled, it will directly affect the threshold uniformity and conduction characteristics of the device. The key innovation lies in the subsequent step: using the exact same masking layer, P-type impurities are directly injected into the bottom of the trench without stripping, forming... Gate active region. This design achieves perfect self-alignment between the gate and the trench, ensuring the accuracy and consistency of the PN junction position; if traditional photolithography is used for etching and implantation separately, any tiny alignment deviation will lead to gate offset and electrical parameter dispersion, seriously affecting device yield and reliability.

[0031] A metal layer (preferably nickel) is globally sputtered across the entire device surface (including within trenches) and annealed to form low-resistance ohmic contacts on the active regions of the source and gate, respectively. This approach directly targets the gate. The fundamental problem is excessively high sheet resistance. The extremely low sheet resistance of metallic nickel makes it suitable for use in... The silicide layer formed on the silicon carbide surface constitutes a highly efficient bypass conductive channel, thereby significantly reducing the path resistance from the gate contact to the gate junctions at various internal points. This method cleverly utilizes the ohmic contact fabrication step in the existing process flow without introducing any non-standard new process modules. In contrast, the polysilicon approach in the background technology not only has a higher material resistivity but also requires the introduction of entirely new deposition and etching processes incompatible with existing JFET processes, facing significant challenges in terms of increased cost and process feasibility. Without introducing such a low-resistance path, the gate drive signal will be driven through a high-resistance path. Severe attenuation within the region leads to slow response of internal cells, a sharp increase in switching losses, and even the inability to completely turn off.

[0032] After forming the ohmic contact layer, a second masking layer made of another insulating material (such as silicon nitride) is globally deposited as an interlayer dielectric and protective layer. The subsequent key isolation design involves selectively etching contact vias only above the source active region, while deliberately preserving the entire second masking layer covering the source metal layer directly above the gate active region and below it. This design ensures that the subsequent large-area source metal layer can only connect to the source region, while being physically completely isolated from the gate region. This is crucial for achieving both "improved gate conductivity" and "preventing gate-source short circuits"; if vias were also etched above the gate region, the source metal would inevitably short-circuit directly with the gate after filling, causing device malfunction.

[0033] Finally, the source metal layer and the gate metal layer located at the edge are formed through metal deposition and patterning. The gate signal is injected from the edge contact point and is quickly conducted to every gate junction inside the chip through the low-resistivity metal (nickel) network that has been formed and distributed throughout the gate regions. This "edge-driven, low-resistivity network distributed transmission" architecture is the optimal solution under the practical layout where the source metal must occupy the central area to reduce resistance. If the gate metal is also placed in the center of the chip, it will face the problem of extremely high process complexity and parasitic parameter deterioration due to cross-isolation with the source metal. Without the aforementioned low-resistivity metal network as a foundation, driving from only one point at the edge will not be able to effectively transmit the signal to the interior, returning to the original state of insufficient driving capability.

[0034] In summary, the innovation of this manufacturing method lies in a series of interconnected and inseparable technical choices: the self-aligned trench and gate integration process ensures precision advantages from the outset; using a metal ohmic contact layer as an embedded low-resistance gate path fundamentally solves the driving bottleneck and is fully compatible with existing production lines; the selectively retained insulating layer structure enhances performance while strengthening the reliability barrier. These steps work synergistically to systematically overcome the gate driving challenge of vertical JFETs. The absence or substitution of any single link will lead to performance degradation, increased costs, or functional failure, thus forming a non-obvious but highly industrially applicable technological innovation solution. Example

[0035] Based on Embodiment 1, this embodiment discloses a vertical JFET power device manufactured by the above method, characterized in that it includes: The heavily doped gate active region located at the bottom of the trench is covered with a metal ohmic contact layer. A complete insulating layer structure covering the gate active region and its metal ohmic contact layer, which isolates the source metal layer of the device from the gate active region. The metal ohmic contact layer, extending from the gate contact point at the edge of the device to the active gate region of each internal cell, together constitutes a metal conduction path for reducing gate resistance and enhancing gate drive capability.

[0036] Preferably, the material of the metal ohmic contact layer is nickel. Example

[0037] A high-power circuit structure is characterized by employing the JFET power device of Example 2 obtained in Example 1.

[0038] In summary, this invention provides a vertical JFET power device with high drive capability and high process compatibility, along with its manufacturing solution. By innovatively utilizing a globally formed metal ohmic contact layer in the conventional JFET process flow, a low-resistance bypass network covering the surface of the high-resistance gate P+ active region is constructed, thus fundamentally solving the core problem of gate signal attenuation over long distances. Simultaneously, this invention cleverly designs a process for selectively retaining the insulating layer above the gate region, fundamentally eliminating the risk of gate-source short circuits while improving performance. This solution eliminates the need for non-standard process modules such as polysilicon, allowing for seamless integration into existing production lines. It achieves an excellent balance between drive performance, manufacturing cost, and process reliability, providing a superior semiconductor device option for high-voltage, high-current power applications.

[0039] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A method for manufacturing a vertical JFET power device with enhanced gate-end drive capability using ohmic contacts, characterized in that, Includes the following steps: S1: Provides a substrate and an epitaxial layer having a first conductivity type; S2: Global ion implantation is performed on the upper surface of the epitaxial layer to form a heavily doped source active region; S3: Under the protection of the first masking layer, trenches are etched in the epitaxial layer; S4: Using the same first masking layer as in step S3, ion implantation is performed into the bottom of the trench to form a heavily doped gate active region; S5: Globally sputter metal layers onto the surfaces of the source active region and the gate active region to form their respective ohmic contacts, and the ohmic contacts of the source and the gate are isolated from each other. S6: Globally deposit a second masking layer on the device surface where ohmic contacts are completed; S7: In the region corresponding to the area directly above the source active region, the second masking layer is selectively etched to form a source region via that exposes the source ohmic contact, while retaining the entire second masking layer covering the source metal layer directly above the gate active region and directly below it. S8: Form a source metal layer that is electrically connected to the source ohmic contact and a gate metal layer that is electrically connected to the gate ohmic contact located in the edge region of the device.

2. The method according to claim 1, characterized in that, In step S5, the globally sputtered metal layer is nickel.

3. The method according to claim 1 or 2, characterized in that, The second masking layer mentioned in step S6 is a second insulating layer deposited directly after the ohmic contact is formed in step S5, and its material is different from the insulating material of the masking layers used in steps S3 to S5.

4. The method according to claim 1, characterized in that, Before step S5, the following steps are also included: S4a: After etching trenches and implanting to form the gate active region, a first masking layer is deposited on the device surface and etched to form initial vias leading to the entire source active region and gate active region, respectively. In step S5, the globally sputtered metal layer covers the surface of the first masking layer and the bottom and sidewalls of the initial via, and forms an ohmic contact with the semiconductor active region at the bottom of the via through a self-aligned process.

5. The method according to claim 4, characterized in that, The first masking layer is a residual portion of the masking layer used in step S3 or a separately deposited masking layer.

6. The method according to claim 1, characterized in that, In step S7, when selectively etching the second masking layer to form a source region via, a gate contact hole leading to the gate ohmic contact is simultaneously etched at the device edge corresponding to the position where the gate metal layer is connected.

7. The method according to claim 1, characterized in that, In step S7, the entire second masking layer covering the source metal layer directly above the gate active region is retained. The purpose of this is to achieve electrical isolation between the subsequently formed source metal layer and the gate active region and its surface metal ohmic contact, thereby preventing gate-source short circuit.

8. A vertical JFET power device with enhanced gate-end drive capability via an ohmic contact, manufactured by the method according to any one of claims 1 to 7, characterized in that, include: The heavily doped gate active region located at the bottom of the trench is covered with a metal ohmic contact layer. A complete insulating layer structure covering the gate active region and its metal ohmic contact layer, which isolates the source metal layer of the device from the gate active region. The metal ohmic contact layer, extending from the gate contact point at the edge of the device to the active gate region of each internal cell, together constitutes a metal conduction path for reducing gate resistance and enhancing gate drive capability.

9. The vertical JFET power device according to claim 8, characterized in that, The material of the metal ohmic contact layer is nickel.

10. A high-power circuit structure, characterized by: The JFET power device of any one of claims 8-9 obtained by using the method of any one of claims 1-7.

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