An efficient control circuit for a synchronous converter

Abstract

The present invention provides an efficient control circuit for a synchronous converter, comprising: a power switch unit, the power switch unit including a power transistor, a synchronous rectifier, a first controller and a second controller; a zero-crossing detection unit, a detection end of the zero-crossing detection unit being connected to a switching node, an output end of the zero-crossing detection unit being connected to the second controller; an output unit, a first end of the output unit being connected to the switching node, a second end of the output unit being connected to a second end of the synchronous rectifier; a self-regulation control unit, a first end of the self-regulation control unit being connected to a first end of the power transistor, a second end of the self-regulation control unit being connected to the second controller, the self-regulation control unit including a clock module, a first sample-and-hold module, a second sample-and-hold module, an operational amplifier and a first comparator.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and more specifically, to an efficient control circuit for a synchronous converter. Background Art

[0002] As Figure 1 shown, in the case of a conventional controller operating in the DCM mode, during the PWM_OFF phase, the lower switch signal LS turns on the lower switch Q2, and the inductor current continues to flow until the ZCD detects that the inductor current crosses zero, and the lower switch is turned off in the current cycle; when an existing synchronous converter or controller operates in the light load DCM mode, during the PWM off phase, the lower switch (freewheeling diode) is turned on until the inductor current crosses zero, and the low Ron of the switching transistor is utilized to save the conduction loss; however, there will be a switching loss when the lower switch is turned on once in a cycle; when the load current is small, the switching loss of turning on the lower switch once will exceed the loss saved by the body diode freewheeling, and thus turning on the lower switch for freewheeling will instead reduce the efficiency. Summary of the Invention

[0003] The object of the present invention is to provide an efficient control circuit for a synchronous converter.

[0004] The present invention aims to solve the problems existing in the existing synchronous converters.

[0005] Compared with the prior art, the technical solution and its beneficial effects of the present invention are as follows:

[0006] An efficient control circuit for a synchronous converter, comprising: a power switch unit, the power switch unit including a power transistor, a synchronous rectifier, a first controller, and a second controller; a zero-crossing detection unit, a detection end of the zero-crossing detection unit being connected to a switching node, and an output end of the zero-crossing detection unit being connected to the second controller; an output unit, a first end of the output unit being connected to the switching node, and a second end of the output unit being connected to a second end of the synchronous rectifier; a self-regulating control unit, a first end of the self-regulating control unit being connected to a first end of the power transistor, and a second end of the self-regulating control unit being connected to the second controller, the self-regulating control unit including a clock module, a first sample-and-hold module, a second sample-and-hold module, an operational amplifier, a first comparator, and a sampling resistor, a positive-phase input end of the operational amplifier being connected to one end of the sampling resistor, and a negative-phase input end of the operational amplifier being connected to the other end of the sampling resistor.

[0007] As a further improvement, the first end of the first sample-and-hold module is connected to the positive-phase input terminal of the first comparator, the second end of the first sample-and-hold module is connected to the first end of the clock module, and the third end of the first sample-and-hold module is connected to the output terminal of the operational amplifier; the first end of the second sample-and-hold module is connected to the output terminal of the operational amplifier, the second end of the second sample-and-hold module is connected to the second end of the clock module, and the third end of the second sample-and-hold module is connected to the negative-phase input terminal of the first comparator.

[0008] As a further improvement, the self-regulating control unit further includes: a first transmission gate, the first end of the first transmission gate is connected to the fourth end of the clock module, the input end of the first transmission gate is connected to the third end of the clock module, and the output end of the first transmission gate is connected to the second controller; a second transmission gate, the first end of the second transmission gate is connected to the second end of the first transmission gate, the second end of the second transmission gate is connected to the fourth end of the clock module, the input end of the second transmission gate is connected to the output end of the first comparator, and the output end of the second transmission gate is connected to the second controller; a NOT gate, the input end of the NOT gate is connected to the fourth end of the clock module, and the output end of the NOT gate is connected to the second end of the first transmission gate.

[0009] As a further improvement, the first sample-and-hold module includes: a first capacitor, one end of the first capacitor is connected to the positive-phase input terminal of the first comparator, and the other end of the first capacitor is grounded; a first switch, one end of the first switch is connected to the other end of the first capacitor, and the control end of the first switch is connected to the first end of the clock module.

[0010] As a further improvement, the second sample-and-hold module includes: a second switch, one end of the second switch is connected to the other end of the first switch, the other end of the second switch is connected to the negative-phase input terminal of the first comparator, and the control end of the second switch is connected to the second end of the clock module; a second capacitor, one end of the second capacitor is connected to the other end of the second switch, and the other end of the second capacitor is grounded.

[0011] As a further improvement, the output unit includes: a first inductor, the first inductor is connected to the switching node; a third capacitor, the third capacitor is connected in series between the first inductor and the second end of the synchronous rectifier; a load resistor, the load resistor is connected in parallel across both ends of the third capacitor.

[0012] As a further improvement, the power transistor is an enhancement-mode NMOS transistor, and the synchronous rectifier is an enhancement-mode NMOS transistor.

[0013] As a further improvement, the zero-crossing detection unit includes a second comparator. The positive input terminal of the second comparator is connected to the switching node, the negative input terminal of the second comparator is grounded, and the output terminal of the second comparator is connected to the second controller.

[0014] As a further improvement, the first controller and the second controller are integrated into the same controller.

[0015] The beneficial effects of the present invention are as follows: The present invention adopts a combination of a power switch unit, a zero-crossing detection unit, an output unit, and a self-regulating control unit, and proposes a control method for a synchronous converter or controller. By determining the magnitude of the input average current in different modes, it realizes a control method that selects the minimum input average current in the synchronous mode and the asynchronous mode for the self-regulating system, and at the same time updates periodically to adapt to system changes, achieving the best efficiency operation.

[0016] The present invention proposes an efficient self-regulating control method. By determining the magnitude of the input average current when the lower transistor is turned on for freewheeling and when it is not turned on for freewheeling, it selects the operation mode with the minimum input average current, that is, the highest efficiency, namely whether to switch the lower transistor for freewheeling, so as to realize the operation mode with the highest efficiency of the synchronous converter in self-regulation. Description of the Drawings

[0017] Figure 1 is the control circuit diagram of the existing synchronous converter provided by the background art.

[0018] Figure 2 is the first schematic diagram of an efficient control circuit of a synchronous converter provided by an embodiment of the present invention.

[0019] Figure 3 is Figure 2 the circuit signal diagram of

[0020] Figure 4 is the second schematic diagram of an efficient control circuit of a synchronous converter provided by an embodiment of the present invention.

[0021] Figure 5 is the flowchart of an efficient control circuit of a synchronous converter provided by an embodiment of the present invention.

[0022] Figure 6 is the third schematic diagram of an efficient control circuit of a synchronous converter provided by an embodiment of the present invention.

[0023] In the figure:

[0024] 1. Power switch unit 11. First controller 12. Second controller

[0025] 2. Zero-crossing detection unit 3. Output unit 4. Self-regulating control unit Detailed implementation manners

[0026] To make the objectives, technical solutions and advantages of the implementation manners of the present invention clearer, the technical solutions in the implementation manners of the present invention will be clearly and completely described below with reference to the accompanying drawings in the implementation manners of the present invention. Obviously, the described implementation manners are part rather than all of the implementation manners of the present invention. Based on the implementation manners in the present invention, all other implementation manners obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. Therefore, the detailed description of the implementation manners of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected implementation manners of the present invention. Based on the implementation manners in the present invention, all other implementation manners obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0027] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0028] Referring to Figures 2 to 3 As shown, a high-efficiency control circuit for a synchronous converter includes: a power switch unit 1, where the power switch unit 1 includes a power transistor Q1, a synchronous rectifier diode Q2, a first controller 11, and a second controller 12; a zero-crossing detection unit 2, where the detection end of the zero-crossing detection unit 2 is connected to a switching node, and the output end of the zero-crossing detection unit 2 is connected to the second controller 12; an output unit 3, where the first end of the output unit 3 is connected to the switching node, and the second end of the output unit 3 is connected to the second end of the synchronous rectifier diode Q2; a self-regulating control unit 4, where the first end of the self-regulating control unit 4 is connected to the first end of the power transistor Q1, the second end of the self-regulating control unit 4 is connected to the second controller 12, and the self-regulating control unit 4 includes a clock module CLK, a first sample-and-hold module, a second sample-and-hold module, an operational amplifier opa, and a first comparator COMP2.

[0029] The self - regulating control unit 4 further includes a sampling resistor Rsense. The positive input terminal of the operational amplifier opa is connected to one end of the sampling resistor Rsense, and the negative input terminal of the operational amplifier opa is connected to the other end of the sampling resistor Rsense. The first end of the first sample - and - hold module is connected to the positive input terminal of the first comparator COMP2, the second end of the first sample - and - hold module is connected to the first end of the clock module CLK, and the third end of the first sample - and - hold module is connected to the output terminal of the operational amplifier opa. The first end of the second sample - and - hold module is connected to the output terminal of the operational amplifier opa, the second end of the second sample - and - hold module is connected to the second end of the clock module CLK, and the third end of the second sample - and - hold module is connected to the negative input terminal of the first comparator COMP2.

[0030] The self - regulating control unit 4 further includes: a first transmission gate TG1, the first end of the first transmission gate TG1 is connected to the fourth end of the clock module CLK, the input terminal of the first transmission gate TG1 is connected to the third end of the clock module CLK, and the output terminal of the first transmission gate TG1 is connected to the second controller 12; a second transmission gate TG2, the first end of the second transmission gate TG2 is connected to the second end of the first transmission gate TG1, the second end of the second transmission gate TG2 is connected to the fourth end of the clock module CLK, the input terminal of the second transmission gate TG2 is connected to the output terminal of the first comparator COMP2, and the output terminal of the second transmission gate TG2 is connected to the second controller 12; a NOT gate N, the input terminal of the NOT gate N is connected to the fourth end of the clock module CLK, and the output terminal of the NOT gate N is connected to the second end of the first transmission gate TG1.

[0031] The first sample - and - hold module includes: a first capacitor C1, one end of the first capacitor C1 is connected to the positive input terminal of the first comparator COMP2, and the other end of the first capacitor C1 is grounded; a first switch S1, one end of the first switch S1 is connected to the other end of the first capacitor C1, and the control terminal of the first switch S1 is connected to the first end of the clock module CLK.

[0032] The second sample - and - hold module includes: a second switch S2, one end of the second switch S2 is connected to the other end of the first switch S1, the other end of the second switch S2 is connected to the negative input terminal of the first comparator COMP2, and the control terminal of the second switch S2 is connected to the second end of the clock module CLK; a second capacitor C2, one end of the second capacitor C2 is connected to the other end of the second switch S2, and the other end of the second capacitor C2 is grounded.

[0033] The output unit 3 includes: a first inductor L, which is connected to the switching node; a third capacitor Cout, which is connected in series between the first inductor L and the second terminal of the synchronous rectifier transistor Q2; and a load resistor Rload, which is connected in parallel across both ends of the third capacitor Cout.

[0034] The power transistor Q1 is an enhancement-mode NMOS transistor, and the synchronous rectifier transistor Q2 is an enhancement-mode NMOS transistor.

[0035] The zero-crossing detection unit 2 includes a second comparator COMP1. The non-inverting input terminal of the second comparator COMP1 is connected to the switching node, the inverting input terminal of the second comparator COMP1 is grounded, and the output terminal of the second comparator COMP1 is connected to the second controller 12.

[0036] The first controller 11 and the second controller 12 are integrated in the same controller.

[0037] Refer to Figures 2 to 5 As shown, the working principle of an efficient control circuit for a synchronous converter provided by the present invention is as follows:

[0038] Generally, a non-synchronous converter or controller relies on a diode for freewheeling, which has a relatively large conduction loss and no switching loss; while a synchronous controller or converter uses the low Ron of the lower transistor for freewheeling to reduce the conduction loss, but the switching of the lower transistor will generate switching loss.

[0039] Especially when the load is light, the total loss of the synchronous converter or controller may exceed the loss of the non-synchronous control or converter, that is, the efficiency of the synchronous converter or controller may be relatively low.

[0040] At the same time, in a DC-DC application, when the output voltage and output current are determined, there is a fixed output power, and at the same time, the input voltage is also a stable input voltage. Thus, the change in the input average current reflects the change in the input power, that is, it also reflects the change in the efficiency; when the input average current is large, the input power is large and the efficiency is low; when the input average current is small, the input power is small and the efficiency is high.

[0041] Based on the above two points, a self-regulating control method is designed to achieve the best efficiency operation; when it is determined that the current is a light load, enter the self-regulating cycle: in the comparison stage 1, execute the synchronous mode, that is, turn on the lower transistor for freewheeling, and at the same time collect the input average current of this mode; in the comparison stage 2, execute the asynchronous mode, that is, turn off the lower transistor for freewheeling, and at the same time collect the input average current of this mode; compare the magnitudes of the average currents of the two modes, and select the control mode with the smallest current; that is, when the synchronous mode current is smaller, execute the synchronous mode in the execution stage; when the asynchronous mode current is smaller, execute the asynchronous mode in the execution stage.

[0042] In addition, referring to Figure 6 as shown, it should be noted that the first / second sample and hold module of the present invention can be replaced by an ADC and a Latch latch, and at the same time, the first comparator COMP1 is replaced by a digital comparator.

[0043] The above embodiments are only used to explain the technical solutions of the present invention rather than to limit it. Those skilled in the art should understand that any modification and equivalent replacement without departing from the spirit and scope of the present invention should fall within the protection scope of the claims of the present invention.

Claims

1. An efficient control circuit for a synchronous converter, characterized in that, Comprising: A power switch unit, which includes a power transistor, a synchronous rectifier, a first controller and a second controller; A zero-crossing detection unit, whose detection end is connected to the switching node, and whose output end is connected to the second controller; An output unit, whose first end is connected to the switching node, and whose second end is connected to the second end of the synchronous rectifier; An auto-regulation control unit, whose first end is connected to the first end of the power transistor, and whose second end is connected to the second controller. The auto-regulation control unit includes a clock module, a first sample-and-hold module, a second sample-and-hold module, an operational amplifier, a first comparator and a sampling resistor. The positive input terminal of the operational amplifier is connected to one end of the sampling resistor, and the negative input terminal of the operational amplifier is connected to the other end of the sampling resistor; The auto-regulation control unit performs sampling and comparison: turn on the synchronous rectifier to enter the synchronous mode and collect the input average current in this mode, turn off the synchronous rectifier to enter the asynchronous mode and collect the input average current in this mode; compare the magnitudes of the average currents in the two modes. When the input average current in the synchronous mode is smaller, the synchronous mode is executed. When the input average current in the asynchronous mode is smaller, the asynchronous mode is executed.

2. The efficient control circuit for a synchronous converter according to claim 1, characterized in that, The first end of the first sample-and-hold module is connected to the positive input terminal of the first comparator, the second end of the first sample-and-hold module is connected to the first end of the clock module, and the third end of the first sample-and-hold module is connected to the output terminal of the operational amplifier; The first end of the second sample-and-hold module is connected to the output terminal of the operational amplifier, the second end of the second sample-and-hold module is connected to the second end of the clock module, and the third end of the second sample-and-hold module is connected to the negative input terminal of the first comparator.

3. The efficient control circuit for a synchronous converter according to claim 2, characterized in that, The auto-regulation control unit further includes: A first transmission gate, whose first end is connected to the fourth end of the clock module, whose input end is connected to the third end of the clock module, and whose output end is connected to the second controller; A second transmission gate, whose first end is connected to the second end of the first transmission gate, whose second end is connected to the fourth end of the clock module, whose input end is connected to the output terminal of the first comparator, and whose output end is connected to the second controller; A NOT gate, whose input end is connected to the fourth end of the clock module, and whose output end is connected to the second end of the first transmission gate.

4. The efficient control circuit for a synchronous converter according to claim 1, characterized in that, The first sample-and-hold module includes: A first capacitor, one end of which is connected to the positive input terminal of the first comparator, and the other end of which is grounded; A first switch, one end of which is connected to the other end of the first capacitor, and whose control end is connected to the first end of the clock module.

5. The efficient control circuit for a synchronous converter according to claim 4, characterized in that, The second sample-and-hold module includes: A second switch, one end of the second switch is connected to the other end of the first switch, the other end of the second switch is connected to the inverting input terminal of the first comparator, and the control terminal of the second switch is connected to the second terminal of the clock module; A second capacitor, one end of the second capacitor is connected to the other end of the second switch, and the other end of the second capacitor is grounded.

6. The efficient control circuit for a synchronous converter according to claim 1, characterized in that, The output unit includes: A first inductor, the first inductor is connected to the switching node; A third capacitor, the third capacitor is connected in series between the first inductor and the second terminal of the synchronous rectifier tube; A load resistor, the load resistor is connected in parallel across both ends of the third capacitor.

7. The efficient control circuit for a synchronous converter according to claim 1, characterized in that, The power tube is an enhancement-mode NMOS transistor, and the synchronous rectifier tube is an enhancement-mode NMOS transistor.

8. The efficient control circuit for a synchronous converter according to claim 1, characterized in that, The zero-crossing detection unit includes a second comparator, the non-inverting input terminal of the second comparator is connected to the switching node, the inverting input terminal of the second comparator is grounded, and the output terminal of the second comparator is connected to the second controller.

9. The efficient control circuit for a synchronous converter according to claim 1, characterized in that, The first controller and the second controller are integrated in the same controller.

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