A GaN power amplifier negative gate voltage bias protection circuit and working method thereof

Abstract

The present invention provides a GaN power amplifier negative gate voltage bias protection circuit and a working method thereof, wherein the GaN power amplifier negative gate voltage bias protection circuit comprises a power module, an AMC chip U1, a reverse amplifier U2, a logic AND gate U3, a depletion-type GaN power amplifier tube T1, a PMOS power switch tube T2 and an NMOS switch tube T3. The present invention outputs a negative gate voltage through the AMC chip U1, and adopts the reverse amplifier U2 to clamp it to a high level, and then uses the logic AND gate U3 to make the reverse amplifier U2 output a positive voltage clamped to a high level only when the positive voltage outputted by the reverse amplifier U2 and the 5G mobile communication service-level TDD timing level are both high levels, and then cooperates with the PMOS power switch tube T2 and the NMOS switch tube T3 to realize the 5G mobile communication TDD timing level to control the rapid switching of the GaN power amplifier tube between the on and off states, so as to achieve the purpose of reducing power consumption and not interfering with the receiving channel.

Description

Technical Field

[0001] The present invention relates to the technical field of 5G mobile communication base station side equipment, and in particular to a GaN power amplifier negative gate voltage bias protection circuit and a working method thereof. Background Art

[0002] The third-generation wide-bandgap semiconductor power gallium nitride (GaN) power amplifier tube is particularly suitable for use in high-frequency, high-power RF power amplifiers, especially in the 5G era, due to its advantages such as large bandgap width, high breakdown field strength, and high saturated electron drift rate.

[0003] GaN power amplifier tube is a depletion-type device. Depletion-type semiconductor devices require a negative gate bias in both normal operation and cut-off state. Without this negative bias, the device may be over-opened and burned out. Depletion-type devices need to have timing requirements for powering on or off during application, and the power-on and power-off sequence requirements for the gate voltage and drain voltage are extremely stringent, that is, the power-on requirement requires that the gate negative voltage must be earlier than the drain positive voltage in timing. If the gate voltage of the GaN power amplifier tube drops to zero before the drain voltage at the time of power-off, the GaN power amplifier tube will be burned out. Therefore, the design of the bias control protection circuit of the GaN power amplifier tube is particularly important.

[0004] The bias control protection circuit of the existing GaN power amplifier tube is as follows:

[0005] The Chinese patent document with publication number CN107528553A discloses a GaN power amplifier tube bias protection circuit, including a GaN power amplifier tube, a gate voltage stabilization circuit, a gate voltage adjustment circuit, a voltage follower circuit, and a gate drain power-on protection circuit. It can well realize the power amplifier bias power-on timing protection and the rapid switching of the power amplifier switch and the controllable power amplifier gain. In this patent, the Vg reference input is provided by a sliding rheostat, and the temperature variation compensation is performed by a thermistor to adjust the gate voltage. This patent cannot realize the rapid switching of the GaN power amplifier tube between the on and off states of the 5G mobile communication TDD timing level control.

[0006] The Chinese patent document with publication number CN111817669A discloses a GaN power amplifier control system, including a gate control unit and a drain control unit. The patent solves the problem that there is not enough time difference between the power-on and power-off of the gate and drain of the GaN power amplifier to protect it, and realizes the beneficial effect of delayed power-on of the drain of the GaN power amplifier, rapid discharge of the drain when powered off, and protecting the GaN power amplifier from damage when powered on or off. The patent cannot realize the fast switching of the GaN power amplifier between the on and off states of the 5G mobile communication TDD timing level control.

[0007] The Chinese patent document with publication number CN111628760A discloses a gate voltage switching device, including a negative power supply, a positive power supply, an inverting amplifier module, a switch circuit and a resistor matching network, which can realize the control of the gate of the GaN power amplifier to quickly switch between closing and opening. This patent cannot realize the switching back and forth of the drain of the GaN power amplifier tube to open or close.

[0008] The Chinese patent document with publication number CN110048677A discloses a power supply control method and device for a power amplifier. When the power amplifier is powered on, the gate is powered first, and after the gate is normal, the drain is powered. Under the premise of meeting the power-on and power-off timing of the power amplifier, the slow start circuit, the MOS on the Vd line and the large-capacity energy storage capacitor on the Vg output are saved, the circuit reliability is improved, and the single board area and cost are saved. This patent cannot realize the fast switching of the GaN power amplifier tube between the on and off states of the 5G mobile communication TDD timing level control.

[0009] The Chinese patent document with publication number CN102265682A discloses a power supply control method and device for a negative gate voltage power tube, a power amplifier device, and a base station. The method includes: when the first path is working, the first path supplies power to the gate voltage; when the first path is not working, the second path is working, and the second path supplies power to the gate voltage. It effectively avoids the burning of the negative gate voltage power tube and improves the reliability of the negative gate voltage power tube. This patent cannot achieve the fast switching of the 5G mobile communication TDD timing level control GaN power amplifier tube between the on and off states.

[0010] The summary of the bias control protection circuit of the above existing GaN power amplifier tube is as follows:

[0011] In terms of GAN power amplifier bias protection, Chinese patent documents CN107528553A, CN111817669A, CN111628760A, CN110048677A, and CN102265682A cannot achieve the rapid switching of the 5G mobile communication TDD timing level control GaN power amplifier tube between the on and off states to achieve the purpose of power saving; in addition, in terms of the way of applying negative gate voltage, Chinese patent document CN107528553A uses a sliding rheostat to achieve adjustable negative gate voltage input; in terms of temperature compensation, CN107528553A and CN111628760A both use thermistors to achieve temperature variation compensation of GaN power amplifier tubes. Summary of the invention

[0012] The present invention aims to provide a GaN power amplifier negative gate voltage bias protection circuit and a working method thereof, so as to solve the problem that the bias control protection circuits of the existing GaN power amplifier tubes cannot realize the fast switching of the GaN power amplifier tubes between the on and off states in the 5G mobile communication TDD timing level control.

[0013] The present invention provides a GaN power amplifier negative gate voltage bias protection circuit, comprising a power module, an AMC chip U1, a reverse amplifier U2, a logic AND gate U3, a depletion-type GaN power amplifier tube T1, a PMOS power switch tube T2 and an NMOS switch tube T3;

[0014] The AMC chip U1 has a bipolar DAC unit capable of generating a negative gate voltage; the power module is connected to the power input port of the AMC chip U1; the SPI input port of the AMC chip U1 is used to connect to the SPI control bus output port of the control unit; the output port of the AMC chip U1 is connected to the reverse input end of the reverse amplifier U2 via the resistor R1 on the one hand, and is connected to the gate of the depletion-type GaN power amplifier tube T1 via the resistor R10 and the choke coil choke1 on the other hand, and the gate of the GaN power amplifier tube T1 is also input with the RF input signal Rfin;

[0015] The reverse input terminal of the reverse amplifier U2 is connected to the output port of the reverse amplifier U2 via the resistor R3, the positive input terminal of the reverse amplifier U2 is grounded via the resistor R2, the positive power supply port of the reverse amplifier U2 is connected to the positive voltage power supply VDD, and the negative power supply port of the reverse amplifier U2 is connected to the negative voltage power supply VSS; the first input port of the logic AND gate U3 is connected to the 5G mobile communication service-level TDD timing level output port, the second input port of the logic AND gate U3 is connected to the output port of the reverse amplifier U2, and the output port of the logic AND gate U3 is connected to the gate of the NMOS switch tube T3 via the resistor R4; the source of the NMOS switch tube T3 is grounded, and the NMOS switch The drain of the gate tube T3 is connected to the input port of the resistor R5; the output port of the resistor R5 is connected to the gate of the PMOS power switch tube T2 on one hand, and is connected to the input port of the resistor R6 on the other hand; the source of the PMOS power switch tube T2 is connected to the 48V power supply; the electrical connection point between the source of the PMOS power switch tube T2 and the 48V power supply is connected to the output port of the resistor R6; the drain of the PMOS power switch tube T2 is connected to the drain of the depletion-type GaN power amplifier tube T1 through the choke coil choke2, and the drain of the depletion-type GaN power amplifier tube T1 also outputs the radio frequency output signal RFout; the source of the depletion-type GaN power amplifier tube T1 is grounded.

[0016] Furthermore, the GaN power amplifier negative gate voltage bias protection circuit also includes a current sensor Rsense; two ends of the current sensor Rsense are respectively connected to a current sensing signal positive input port +sense and a current sensing signal negative input port -sense of the AMC chip U1.

[0017] Furthermore, the GaN power amplifier negative gate bias protection circuit also includes an NPN transistor Q2 for realizing internal and external temperature monitoring of the AMC chip U1; the base and collector of the NPN transistor Q2 are both connected to the temperature sensing signal positive input port Remote Temperature Sensor D+ of the AMC chip U1; and the emitter of the NPN transistor Q2 is connected to the temperature sensing signal negative input port Remote Temperature Sensor D- of the AMC chip U1.

[0018] Furthermore, the GaN power amplifier negative gate voltage bias protection circuit also includes a transistor temperature compensation adaptive module; the transistor temperature compensation adaptive module includes an NPN transistor Q1, a resistor R7, a resistor R8 and a resistor R9; the collector of the NPN transistor Q1 is grounded, and the base of the transistor Q1 is connected to the collector of the NPN transistor Q1 via the resistor R7 on the one hand, and connected to the emitter of the NPN transistor Q1 via the resistor R8 on the other hand; the emitter of the NPN transistor Q1 is connected to the input port of the resistor R9; the electrical connection point between the resistor R10 and the choke choke1 is connected to the output port of the resistor R9.

[0019] Furthermore, the power supply module includes a power conversion module 1 and a power conversion module 2; the power conversion module 1 is used to provide the AMC chip U1 with the positive voltage it needs; the power conversion module 2 is used to provide the AMC chip U1 with the negative voltage it needs.

[0020] The working method of the GaN power amplifier negative gate voltage bias protection circuit comprises the following steps:

[0021] S1, the power module supplies power to the AMC chip U1;

[0022] S2, the control unit controls the AMC chip U1 to output a negative gate voltage through the bipolar DAC unit. The negative gate voltage is input to the reverse input terminal of the reverse amplifier U2 on the one hand, and reaches the gate of the depletion-type GaN power amplifier tube T1 through the choke coil choke1 on the other hand; the choke coil choke1 enables the negative gate voltage reaching the gate of the GaN power amplifier tube T1 to coexist with the RF input signal Rfin;

[0023] S3, after the negative gate voltage at the reverse input end of the input reverse amplifier U2 is reversely amplified by the reverse amplifier U2, a positive voltage clamped to a high level is output to the second input port of the logic AND gate U3; the first input port of the logic AND gate U3 inputs the 5G mobile communication service level TDD timing level; in the logic AND gate U3, when the positive voltage clamped to a high level output by the reverse amplifier U2 and the 5G mobile communication service level TDD timing level are both high levels, the logic AND gate U3 outputs a high level, otherwise the logic AND gate U3 outputs a low level; wherein:

[0024] (1) When the logic AND gate U3 outputs a low level, the NMOS switch tube T3 cannot be turned on, resulting in the failure of normal voltage division between the resistors R5 and R6. The resistors R5 and R6 are both subjected to the same potential of 48V, which causes the PMOS power switch tube T2 to be unable to be turned on. Ultimately, the 48V voltage during the normal operation of the depletion-type GaN power amplifier tube T1 cannot be provided to the drain of the depletion-type GaN power amplifier tube T1, and the depletion-type GaN power amplifier tube T1 is in a turned-off state;

[0025] (2) When the output of the logic AND gate U3 is high, the NMOS switch tube T3 is turned on, the resistors R5 and R6 divide the voltage normally, the gate voltage of the PMOS power switch tube T2 is 48V×(1+R5 / R6), and the voltage Vgs between the gate and the source of the PMOS power switch tube T2 meets the conduction condition, so that the PMOS power switch tube T2 is turned on, and finally the 48V voltage when the depletion-type GaN power amplifier tube T1 is working normally is indirectly provided to the drain of the depletion-type GaN power amplifier tube T1 through the PMOS power switch tube T2, and the depletion-type GaN power amplifier tube T1 is in the turned-on state.

[0026] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0027] 1. The present invention outputs a negative gate voltage through the AMC chip U1, and adopts the reverse amplifier U2 to clamp it to a high level, and then uses the logic AND gate U3 to make the reverse amplifier U2 output a high level only when the positive voltage clamped to a high level and the 5G mobile communication service-level TDD timing level are both high levels, and then cooperates with the PMOS power switch tube T2 and the NMOS switch tube T3 to realize the 5G mobile communication TDD timing level control GaN power amplifier tube fast switching between the on and off states, so as to achieve the purpose of reducing power consumption and not interfering with the receiving channel.

[0028] 2. The present invention can achieve the stringent timing requirements of the depletion-type GaN power amplifier tube, that is, the negative gate voltage appears before the drain positive voltage in the power-on stage, and the negative gate voltage drops to zero after the drain positive voltage in the power-off stage.

[0029] 3. The present invention adopts a bipolar DAC unit to generate a negative gate voltage, which solves the problem that the negative gate voltage is manually turned by a sliding rheostat, resulting in large simulation errors and insufficient precision.

[0030] 4. The present invention utilizes the temperature characteristics of the transistor itself to solve the problem that the simulation error of the depletion-type GaN power amplifier tube with temperature changes using temperature compensation resistors is large and the accuracy is not high enough. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 It is a structural diagram of a negative gate bias protection circuit for a GaN power amplifier according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Example

[0036] like Figure 1 As shown, this embodiment proposes a GaN power amplifier negative gate bias protection circuit, including a power module, an AMC (Analog Monitor Control) chip U1, a reverse amplifier U2, a logic AND gate U3, a depletion-type GaN power amplifier tube T1, a PMOS power switch tube T2 and an NMOS switch tube T3.

[0037] The AMC chip U1 has a bipolar DAC unit capable of generating a negative gate voltage. The bipolar DAC unit is a 12-bit Bipolar DAC that can generate both -5V to 0V and 0V to 5V, so that the AMC chip U1 can output both a positive gate voltage of 0V to 5V and a negative gate voltage of -5V to 0V.

[0038] The power module is connected to the power input port of the AMC chip U1; optionally, the power module includes a power conversion module 1 and a power conversion module 2; the power conversion module 1 is used to provide the AMC chip U1 with the required positive voltage, such as +5V and +3.3V; the power conversion module 2 is used to provide the AMC chip U1 with the required negative voltage, such as -5V.

[0039] The SPI input port of the AMC chip U1 is used to connect to the SPI control bus output port of the control unit; optionally, the control unit can be implemented using an MCU or an FPGA.

[0040] The output port of the AMC chip U1 is connected to the reverse input terminal of the reverse amplifier U2 via the resistor R1 on the one hand, and is connected to the gate of the depletion-type GaN power amplifier tube T1 via the resistor R10 and the choke choke1 on the other hand. At the same time, the gate of the GaN power amplifier tube T1 is also input with the RF input signal Rfin; wherein the choke choke1 has the function of blocking AC and passing DC, thereby ensuring that the negative gate voltage input to the gate of the GaN power amplifier tube T1 can coexist with the RF input signal RFin, thereby realizing DC and AC regional management.

[0041] The reverse input terminal of the reverse amplifier U2 is connected to the output port of the reverse amplifier U2 via the resistor R3, the positive input terminal of the reverse amplifier U2 is grounded via the resistor R2, the positive power supply port of the reverse amplifier U2 is connected to the positive power supply VDD (+5V), and the negative power supply port of the reverse amplifier U2 is connected to the negative power supply VSS (-5V); when the negative gate voltage is -5V, the reverse amplifier U2 reversely amplifies the negative gate voltage of -5V to achieve the conversion from negative voltage to positive voltage, thereby clamping the output to a high level, and the reverse amplification factor of the reverse amplifier U2 is -R3 / R1, so the voltage output by the reverse amplifier U2 is -(R3*negative gate voltage) / R1, and by setting appropriate resistors R1 and R3, the voltage output by the reverse amplifier U2 can be clamped to +5V. It should be noted that there is almost no current at the input terminal of the reverse amplifier U2, and the negative gate voltage has no function of pulling down the voltage, which is in line with expectations.

[0042] The first input port of the logic AND gate U3 is connected to the 5G mobile communication service-level TDD timing level output port, the second input port of the logic AND gate U3 is connected to the output port of the reverse amplifier U2, and the output port of the logic AND gate U3 is connected to the gate of the NMOS switch tube T3 via the resistor R4; the source of the NMOS switch tube T3 is grounded, and the drain of the NMOS switch tube T3 is connected to the input port of the resistor R5; the output port of the resistor R5 is connected to the gate of the PMOS power switch tube T2 on the one hand, and to the input port of the resistor R6 on the other hand; the source of the PMOS power switch tube T2 is connected to the 48V power supply; the electrical connection point between the source of the PMOS power switch tube T2 and the 48V power supply is connected to the output port of the resistor R6; the drain of the PMOS power switch tube T2 is connected to the drain of the depletion-type GaN power amplifier tube T1 via the choke choke2, and the drain of the depletion-type GaN power amplifier tube T1 also outputs the radio frequency output signal RFout; the source of the depletion-type GaN power amplifier tube T1 is grounded.

[0043] The working principle of the above-mentioned GaN power amplifier negative gate bias protection circuit is as follows:

[0044] A. GaN power amplifier power-on principle:

[0045] In the logic AND gate U3, when the positive voltage (+5V) clamped to a high level output by the reverse amplifier U2 and the 5G mobile communication service-level TDD timing level are both high levels, the logic AND gate U3 outputs a high level, otherwise the logic AND gate U3 outputs a low level; wherein: (1) when the logic AND gate U3 outputs a low level, the NMOS switch tube T3 cannot be turned on, resulting in the resistor R5 and the resistor R6 not being able to divide the voltage normally, and the resistor R5 and the resistor R6 are both at the same potential of 48V, which causes the PMOS power switch tube T2 to be unable to be turned on, and ultimately causes the 48V voltage when the depletion-type GaN power amplifier tube T1 is working normally to be unable to be provided to the depletion-type GaN power amplifier tube T1. The drain of the depletion-type GaN power amplifier tube T1 is in the off state; (2) When the output of the logic AND gate U3 is high, the NMOS switch tube T3 is turned on, the resistors R5 and R6 divide the voltage normally, the gate voltage of the PMOS power switch tube T2 is 48V×(1+R5 / R6), and the voltage Vgs between the gate and the source of the PMOS power switch tube T2 meets the conduction condition, so that the PMOS power switch tube T2 is turned on, and finally the 48V voltage when the depletion-type GaN power amplifier tube T1 is working normally is indirectly provided to the drain of the depletion-type GaN power amplifier tube T1 through the PMOS power switch tube T2, and the depletion-type GaN power amplifier tube T1 is in the on state. This also meets the inherent timing rule requirement that the negative gate voltage must be earlier than the positive drain voltage in timing when the GaN power amplifier tube is powered on.

[0046] B. GaN power amplifier TDD business stage principle:

[0047] When the 5G mobile communication service-level TDD timing level is high, the high level represents that the transmission channel is open and in the transmission slot. When the 5G mobile communication service-level TDD timing level is low, the low level represents that the receiving channel is open and in the receiving slot, requiring the transmission channel to be closed. When the 5G mobile communication service-level TDD timing level is low, the negative gate voltage of the depletion-type GaN power amplifier tube T1 continues to be supplied, so the level output by the reverse amplifier U2 is still clamped to a high level. At this time, the level output by the logic AND gate U3 is low, so that the NMOS switch tube T3 cannot be turned on, resulting in the resistor R5 and the resistor R6 cannot be divided normally. The resistor R5 and the resistor R6 are both equipotential 48V voltages, which causes the PMOS power switch tube T2 to be unable to be turned on, and ultimately causes the 48V voltage of the depletion-type GaN power amplifier tube T1 to work normally. It cannot be provided to the drain of the depletion-type GaN power amplifier tube T1, and the depletion-type GaN power amplifier tube T1 is in a closed state to avoid interfering with the normal reception of the receiving channel. This meets the scenario requirements in TDD mode in 5G mobile communications.

[0048] C. GaN power dissipation power-on stage principle:

[0049] During the power-off phase, the TDD timing in the actual 5G mobile communication service is turned off first, that is, the 5G mobile communication service-level TDD timing level is low. At this time, the negative gate voltage of the depletion-type GaN power amplifier tube T1 continues to be supplied (note that the negative gate voltage of the depletion-type GaN power amplifier tube T1 drops to zero before the drain voltage, which will cause the depletion-type GaN power amplifier tube T1 to burn out due to excessive opening). Before turning off the drain voltage, the negative gate voltage on the gate must not be turned off. At this time, the output level of the logic AND gate U3 is low, and the NMOS switch tube T3 cannot be turned on, resulting in the failure of normal voltage division between resistors R5 and R6. The resistors R5 and R6 are both at the same potential of 48V, which causes the PMOS power switch tube T2 to be unable to be turned on, and ultimately causes the 48V voltage of the depletion-type GaN power amplifier tube T1 to be unable to be provided to the drain of the depletion-type GaN power amplifier tube T1 when it is working normally. The depletion-type GaN power amplifier tube T1 is in the off state, but the gate has a negative gate voltage, which puts the depletion-type GaN power amplifier tube T1 in a protection state. This also meets the requirement that the gate voltage of the depletion-type GaN power amplifier tube T1 drops to zero after the drain voltage. In addition, after the TDD timing is turned off, the drain voltage of the depletion-mode GaN power amplifier tube T1 is cut off, and the depletion-mode GaN power amplifier tube T1 is not in an amplification state, but only in a Vgs conduction state. The next step is to let the bipolar DAC output a negative gate voltage of -5V, so that the depletion-mode GaN power amplifier tube T1 can be in a deep protection state. At this time, the gate of the depletion-mode GaN power amplifier tube T1 is also in a state that cannot be turned on, thereby protecting the life of the depletion-mode GaN power amplifier tube T1.

[0050] Optionally, the GaN power amplifier negative gate voltage bias protection circuit further includes a current sensor Rsense; the two ends of the current sensor Rsense are respectively connected to the current sensing signal positive input port +sense and the current sensing signal negative input port -sense of the AMC chip U1. Thus, the drain current of the depletion-mode GaN power amplifier tube T1 is monitored by the current sensor Rsense and the CODE value of the bipolar DAC unit is adjusted in time to achieve closed-loop control of the drain current of the depletion-mode GaN power amplifier tube T1, thereby maintaining the drain current of the depletion-mode GaN power amplifier tube T1 at the desired static operating point.

[0051] Optionally, the GaN power amplifier negative gate bias protection circuit further includes an NPN transistor Q2 for realizing internal and external temperature monitoring of the AMC chip U1; the base and collector of the NPN transistor Q2 are both connected to the positive input port of the temperature sensing signal of the AMC chip U1, Remote Temperature Sensor D+; the emitter of the NPN transistor Q2 is connected to the negative input port of the temperature sensing signal of the AMC chip U1, Remote Temperature Sensor D-. Thus, the temperature compensation correction of the AMC chip is performed through the temperature characteristics of the NPN transistor Q2 itself.

[0052] Optionally, the GaN power amplifier negative gate voltage bias protection circuit also includes a transistor temperature compensation adaptive module; the transistor temperature compensation adaptive module includes an NPN transistor Q1, a resistor R7, a resistor R8 and a resistor R9; the collector of the NPN transistor Q1 is grounded, the base of the transistor Q1 is connected to the collector of the NPN transistor Q1 through the resistor R7 on the one hand, and is connected to the emitter of the NPN transistor Q1 through the resistor R8 on the other hand; the emitter of the NPN transistor Q1 is connected to the input port of the resistor R9; the electrical connection point between the resistor R10 and the choke coil choke1 is connected to the output port of the resistor R9. The transistor temperature compensation adaptive module can make full use of the temperature characteristics of the transistor, and correct the temperature variation characteristics of the depletion-type GaN power amplifier tube T1 by building a topological network that reverses the GaN temperature variation trend, thereby achieving a stable GaN power amplifier state without being affected by external temperature variations.

[0053] Furthermore, the working method of the above-mentioned GaN power amplifier negative gate voltage bias protection circuit is characterized by comprising the following steps:

[0054] S1, the power module supplies power to the AMC chip U1;

[0055] S2, the control unit controls the AMC chip U1 to output a negative gate voltage through the bipolar DAC unit. The negative gate voltage is input to the reverse input terminal of the reverse amplifier U2 on the one hand, and reaches the gate of the depletion-type GaN power amplifier tube T1 through the choke coil choke1 on the other hand; the choke coil choke1 enables the negative gate voltage reaching the gate of the GaN power amplifier tube T1 to coexist with the RF input signal Rfin;

[0056] S3, after the negative gate voltage at the reverse input end of the input reverse amplifier U2 is reversely amplified by the reverse amplifier U2, a positive voltage clamped to a high level is output to the second input port of the logic AND gate U3; the first input port of the logic AND gate U3 inputs the 5G mobile communication service level TDD timing level; in the logic AND gate U3, when the positive voltage clamped to a high level output by the reverse amplifier U2 and the 5G mobile communication service level TDD timing level are both high levels, the logic AND gate U3 outputs a high level, otherwise the logic AND gate U3 outputs a low level; wherein:

[0057] (1) When the logic AND gate U3 outputs a low level, the NMOS switch tube T3 cannot be turned on, resulting in the failure of normal voltage division between the resistors R5 and R6. The resistors R5 and R6 are both subjected to the same potential of 48V, which causes the PMOS power switch tube T2 to be unable to be turned on. Ultimately, the 48V voltage during the normal operation of the depletion-type GaN power amplifier tube T1 cannot be provided to the drain of the depletion-type GaN power amplifier tube T1, and the depletion-type GaN power amplifier tube T1 is in a turned-off state;

[0058] (2) When the output of the logic AND gate U3 is high, the NMOS switch tube T3 is turned on, the resistors R5 and R6 divide the voltage normally, the gate voltage of the PMOS power switch tube T2 is 48V×(1+R5 / R6), and the voltage Vgs between the gate and the source of the PMOS power switch tube T2 meets the conduction condition, so that the PMOS power switch tube T2 is turned on, and finally the 48V voltage when the depletion-type GaN power amplifier tube T1 is working normally is indirectly provided to the drain of the depletion-type GaN power amplifier tube T1 through the PMOS power switch tube T2, and the depletion-type GaN power amplifier tube T1 is in the turned-on state.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A GaN power amplifier negative gate bias protection circuit, characterized in that: It includes a power module, an AMC chip U1, a reverse amplifier U2, a logic AND gate U3, a depletion-type GaN power amplifier tube T1, a PMOS power switch tube T2 and an NMOS switch tube T3; The AMC chip U1 has a bipolar DAC unit capable of generating a negative gate voltage; the power module is connected to the power input port of the AMC chip U1; the SPI input port of the AMC chip U1 is used to connect to the SPI control bus output port of the control unit; the output port of the AMC chip U1 is connected to the reverse input end of the reverse amplifier U2 via the resistor R1 on the one hand, and is connected to the gate of the depletion-type GaN power amplifier tube T1 via the resistor R10 and the choke coil choke1 on the other hand, and the gate of the GaN power amplifier tube T1 is also input with the RF input signal Rfin; The reverse input terminal of the reverse amplifier U2 is connected to the output port of the reverse amplifier U2 via the resistor R3, the positive input terminal of the reverse amplifier U2 is grounded via the resistor R2, the positive power supply port of the reverse amplifier U2 is connected to the positive voltage power supply VDD, and the negative power supply port of the reverse amplifier U2 is connected to the negative voltage power supply VSS; the first input port of the logic AND gate U3 is connected to the 5G mobile communication service-level TDD timing level output port, the second input port of the logic AND gate U3 is connected to the output port of the reverse amplifier U2, and the output port of the logic AND gate U3 is connected to the gate of the NMOS switch tube T3 via the resistor R4; the source of the NMOS switch tube T3 is grounded, and the NMOS switch The drain of the gate tube T3 is connected to the input port of the resistor R5; the output port of the resistor R5 is connected to the gate of the PMOS power switch tube T2 on one hand, and is connected to the input port of the resistor R6 on the other hand; the source of the PMOS power switch tube T2 is connected to the 48V power supply; the electrical connection point between the source of the PMOS power switch tube T2 and the 48V power supply is connected to the output port of the resistor R6; the drain of the PMOS power switch tube T2 is connected to the drain of the depletion-type GaN power amplifier tube T1 through the choke coil choke2, and the drain of the depletion-type GaN power amplifier tube T1 also outputs the radio frequency output signal RFout; the source of the depletion-type GaN power amplifier tube T1 is grounded.

2. The GaN power amplifier negative gate bias protection circuit according to claim 1, characterized in that: The GaN power amplifier negative gate voltage bias protection circuit also includes a current sensor Rsense; two ends of the current sensor Rsense are respectively connected to a current sensing signal positive input port +sense and a current sensing signal negative input port -sense of the AMC chip U1.

3. The GaN power amplifier negative gate bias protection circuit according to claim 1, characterized in that: The GaN power amplifier negative gate bias protection circuit also includes an NPN transistor Q2 for realizing internal and external temperature monitoring of the AMC chip U1; the base and collector of the NPN transistor Q2 are both connected to the temperature sensing signal positive input port Remote Temperature Sensor D+ of the AMC chip U1; the emitter of the NPN transistor Q2 is connected to the temperature sensing signal negative input port Remote Temperature Sensor D- of the AMC chip U1.

4. The GaN power amplifier negative gate bias protection circuit according to claim 1, characterized in that: The GaN power amplifier negative gate voltage bias protection circuit also includes a transistor temperature compensation adaptive module; the transistor temperature compensation adaptive module includes an NPN transistor Q1, a resistor R7, a resistor R8 and a resistor R9; the collector of the NPN transistor Q1 is grounded, and the base of the NPN transistor Q1 is connected to the collector of the NPN transistor Q1 through the resistor R7 on the one hand, and connected to the emitter of the NPN transistor Q1 through the resistor R8 on the other hand; the emitter of the NPN transistor Q1 is connected to the input port of the resistor R9; the electrical connection point between the resistor R10 and the choke choke1 is connected to the output port of the resistor R9.

5. The GaN power amplifier negative gate bias protection circuit according to claim 1, characterized in that: The power supply module includes a power conversion module 1 and a power conversion module 2; the power conversion module 1 is used to provide the AMC chip U1 with the positive voltage it needs; the power conversion module 2 is used to provide the AMC chip U1 with the negative voltage it needs.

6. A working method of the GaN power amplifier negative gate bias protection circuit according to claim 1, characterized in that: The steps include: S1, the power module supplies power to the AMC chip U1; S2, the control unit controls the AMC chip U1 to output a negative gate voltage through the bipolar DAC unit. The negative gate voltage is input to the reverse input terminal of the reverse amplifier U2 on the one hand, and reaches the gate of the depletion-type GaN power amplifier tube T1 through the choke coil choke1 on the other hand; the choke coil choke1 enables the negative gate voltage reaching the gate of the GaN power amplifier tube T1 to coexist with the RF input signal Rfin; S3, after the negative gate voltage at the reverse input end of the input reverse amplifier U2 is reversely amplified by the reverse amplifier U2, a positive voltage clamped to a high level is output to the second input port of the logic AND gate U3; the first input port of the logic AND gate U3 inputs the 5G mobile communication service level TDD timing level; in the logic AND gate U3, when the positive voltage clamped to a high level output by the reverse amplifier U2 and the 5G mobile communication service level TDD timing level are both high levels, the logic AND gate U3 outputs a high level, otherwise the logic AND gate U3 outputs a low level; wherein: (1) When the logic AND gate U3 outputs a low level, the NMOS switch tube T3 cannot be turned on, resulting in the failure of normal voltage division between resistors R5 and R6. The resistors R5 and R6 are both subjected to the same potential of 48V, which causes the PMOS power switch tube T2 to be unable to be turned on. Ultimately, the 48V voltage during the normal operation of the depletion-type GaN power amplifier tube T1 cannot be provided to the drain of the depletion-type GaN power amplifier tube T1, and the depletion-type GaN power amplifier tube T1 is in the off state; (2) When the output of the logic AND gate U3 is high, the NMOS switch tube T3 is turned on, the resistors R5 and R6 divide the voltage normally, the gate voltage of the PMOS power switch tube T2 is 48V×(R5 / (R5+R6)), and the voltage Vgs between the gate and the source of the PMOS power switch tube T2 meets the conduction condition, so that the PMOS power switch tube T2 is turned on, and finally the 48V voltage when the depletion-type GaN power amplifier tube T1 is working normally is indirectly provided to the drain of the depletion-type GaN power amplifier tube T1 through the PMOS power switch tube T2, and the depletion-type GaN power amplifier tube T1 is in the turned-on state.

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