A Digital Automatic Gain Control Device and Control Method Based on Double Buffering

Abstract

The present invention discloses a digital automatic gain control device and a control method based on double buffering. The control device includes a serial-to-parallel conversion module, a ping-pong buffer module, a gain calculation module, and an output buffer module. The serial-to-parallel conversion module is respectively connected to the output buffer module through the ping-pong buffer module and the gain calculation module. The serial-to-parallel conversion module receives the digital serial data to be controlled and converts it into multiple paths of parallel data. The ping-pong buffer module performs ping-pong buffering on the parallel data according to frames. The gain calculation module calculates the gain value based on each path of parallel data. The output buffer module obtains the current frame of parallel data from the ping-pong buffer module and multiplies it by the gain value output by the gain calculation module to obtain the gain-adjusted data for output. The present invention can eliminate the hysteresis of gain adjustment, and has the advantages of simple structure, low cost, small delay, high control precision, and strong flexibility.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic gain control (AGC), and particularly to a digital automatic gain control device and a control method based on dual buffers. Background Art

[0002] Digital automatic gain control (DAGC) is to automatically control the gain of digital signals, which is widely used in various application scenarios. For example, truncation in algorithms based on FPGA will generate truncation quantization noise, resulting in signal-to-noise ratio loss. After using multi-stage algorithm cascading, the performance of such loss is particularly serious. Therefore, digital automatic gain control needs to be used between algorithms to reduce such loss and solve the truncation error problem of FPGA.

[0003] To solve the truncation error problem of FPGA as described above, the digital automatic gain control adopted in the prior art usually calculates the signal gain according to the input signal envelope, mainly including the following solutions:

[0004] 1. Feedforward digital AGC (automatic gain control): This type of digital AGC amplifies the signal to near the full scale of the signal to keep the significant bits in the high positions of the data bits as much as possible. As Figure 1 shown, the envelope mean of a section of data is obtained based on the input signal, and then the amplification gain is calculated according to the set threshold. The amplification gain is appropriately filtered to reduce the jitter of the amplification multiple. The input signal is the result of multiplying and amplifying the gain.

[0005] 2. Calculate the multiple to be amplified according to the variance of the input signal, and amplify the input signal to an appropriate number of bits. When applied to FPGA calculations, it can ensure small signal-to-noise ratio loss after truncation. As Figure 2 shown, first calculate the mean square deviation of a section of data based on the input signal, then calculate the error from the reference value. After multiple iterations, the error value converges. Calculate the gain according to the error, and finally multiply the input and output gains to output the result.

[0006] However, in the above digital automatic gain control schemes, the currently calculated gain is applied to the next frame of data, which will cause a lag in gain adjustment and requires a complex adjustment process. For example, in the first type of feedforward digital AGC, the threshold value and filter coefficients need to be adjusted, and in the second type of digital AGC, the reference value also needs to be adjusted. The entire implementation process is relatively complex, with poor adaptive performance, and due to the slow convergence process, it is difficult to meet the application scenarios of high-speed signal processing such as high-speed signal sampling. Summary of the Invention

[0007] The technical problem to be solved by the present invention lies in: aiming at the technical problems existing in the prior art, the present invention provides a digital automatic gain control device and control method based on double buffering, which has a simple structure, low cost, small delay, high control accuracy and strong flexibility, and can eliminate the hysteresis of gain adjustment and reduce the delay of gain control adjustment.

[0008] To solve the above technical problems, the technical solution proposed by the present invention is:

[0009] A digital automatic gain control device based on double buffering, including a serial-to-parallel conversion module, a ping-pong buffer module, a gain calculation module and an output buffer module. The serial-to-parallel conversion module is respectively connected to the output buffer module through the ping-pong buffer module and the gain calculation module. The serial-to-parallel conversion module receives the digital serial data to be controlled and converts it into multiple paths of parallel data. The ping-pong buffer module performs ping-pong buffering on each path of the parallel data according to frames. The gain calculation module calculates the gain value according to each path of the parallel data. The output buffer module obtains the current frame of parallel data from the ping-pong buffer module and multiplies it by the gain value output by the gain calculation module to obtain the data output after gain adjustment.

[0010] Further, the gain calculation module includes a maximum value calculation unit and a gain determination unit connected to each other. The maximum value calculation unit is used to calculate the maximum value in each path of the parallel data, and the gain determination unit is used to determine the gain value according to the calculated maximum value.

[0011] Further, the maximum value calculation unit includes an absolute value circuit, a bitwise OR circuit and a maximum value circuit connected in sequence. The absolute value circuit performs an absolute value operation on each path of the parallel data and outputs it to the bitwise OR circuit. The bitwise OR circuit performs a bitwise OR operation on each path of the parallel data after taking the absolute value with the data of the previous moment respectively, and then the maximum value circuit calculates the maximum value of each path of the parallel data.

[0012] Further, the ping-pong buffer module includes a ping-pong control input unit, a ping-pong buffer unit and a ping-pong control output unit connected in sequence. When the ping-pong control input unit controls to store the current frame of the parallel data in a storage area of the ping-pong buffer unit, the ping-pong control output unit controls to output the previous frame of the parallel data to cache the parallel data in real time according to the ping-pong buffer mechanism.

[0013] Further, a parallel filter module is also provided at the output end of the serial-to-parallel conversion module for performing low-pass filtering on each path of the parallel data.

[0014] Further, the output buffer module includes an input buffer unit, a multiplication unit, and an output unit connected in sequence. The input buffer unit caches the parallel data of the current frame received from the ping-pong buffer module according to the ping-pong control method, and controls the output to the multiplication unit. The multiplication unit multiplies the parallel data of the current frame by the determined gain value to obtain the gain-adjusted result corresponding to the current frame data, and outputs it through the output unit.

[0015] A digital automatic gain control method based on dual buffering, the steps include:

[0016] S01. Receive the digital serial data to be controlled and convert it into multiplex parallel data;

[0017] S02. Perform ping-pong buffering on each path of the parallel data according to frames, and obtain the gain value according to each path of the parallel data;

[0018] S03. Obtain the parallel data of the current frame from the data in the ping-pong buffer, multiply it by the obtained gain value, and output the gain-adjusted data.

[0019] Further, in step S02, performing ping-pong buffering on the parallel data according to frames includes: according to the ping-pong buffering mechanism, when controlling to store the parallel data of the current frame in one storage area, controlling to output the parallel data of the previous frame, and when outputting the parallel data of the current frame, controlling to store the parallel data of the next frame in another storage area.

[0020] Further, in step S02, obtaining the gain value according to each path of the parallel data includes: performing an absolute value operation on each path of the parallel data, and after performing a bitwise OR operation on each path of the parallel data after taking the absolute value with the data at the previous moment respectively, obtaining the maximum value of each path of the parallel data.

[0021] Further, step S03 includes: according to the ping-pong control method, controlling to receive and cache the parallel data of the current frame in the ping-pong buffer, and multiplying the parallel data of the current frame by the determined gain value to output the gain-adjusted result corresponding to the current frame data.

[0022] Compared with the prior art, the advantages of the present invention are:

[0023] 1. The present invention uses ping-pong buffering to keep the parallel data stream sent to the output buffer module in real time and continuously for automatic gain adjustment calculation, so that the gain value obtained each time during automatic gain adjustment can exactly act on the current frame data in real time without lag, eliminating the lag of automatic gain adjustment.

[0024] 2. By combining a parallel structure and a double-buffer structure, the present invention can effectively improve the accuracy and efficiency of automatic gain adjustment, enabling it to meet the high-performance requirements of high-speed serial data for automatic gain adjustment, with flexible use and strong adaptability.

[0025] 3. The present invention does not need to rely on an additional adjustment process during the entire adjustment process. It can reduce the complexity of the entire adjustment process while ensuring the adjustment efficiency and accuracy. At the same time, it does not require a complex iteration process during the adjustment process, so there is no convergence problem, and it is not only easy to implement but also has a stable output. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic structural diagram of the traditional first feed-forward digital AGC.

[0027] Figure 2 It is a schematic structural diagram of the traditional second digital AGC.

[0028] Figure 3 It is a schematic structural diagram of the digital automatic gain control device based on a double buffer in Embodiment 1 of the present invention.

[0029] Figure 4 It is a schematic timing diagram for implementing automatic gain control in Embodiment 1 of the present invention.

[0030] Figure 5 It is a schematic flowchart for implementing the digital automatic gain control method based on a double buffer in Embodiment 2 of the present invention.

[0031] Figure 6 It is a schematic diagram of the implementation principle for implementing digital automatic gain control in Embodiment 3 of the present invention.

[0032] Legend Explanation: 1. Serial-to-parallel conversion module; 2. Ping-pong buffer module; 21. Ping-pong control input unit; 22. Ping-pong buffer unit; 23. Ping-pong control output unit; 3. Gain calculation module; 31. Maximum value calculation unit; 311. Absolute value circuit; 312. Bitwise OR circuit for data; 313. Maximum value circuit; 32. Gain determination unit; 4. Output buffer module; 41. Input unit; 42. Multiplication unit; 43. Output unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0034] Embodiment 1:

[0035] As Figure 3As shown in the figure, the digital automatic gain control device based on dual buffering in this embodiment includes a serial-to-parallel conversion module 1, a ping-pong buffering module 2, a gain calculation module 3, and an output buffering module 4. The serial-to-parallel conversion module 1 is connected to the output buffering module 4 through the ping-pong buffering module 2 and the gain calculation module 3 respectively. Specifically, the output end of the serial-to-parallel conversion module 1 is connected to the ping-pong buffering module 2 and the gain calculation module 3 respectively, and the output ends of the ping-pong buffering module 2 and the gain calculation module 3 are connected to the input end of the output buffering module 4 respectively. The serial-to-parallel conversion module 1 receives the digital serial data to be controlled and converts it into multiple paths of parallel data. The ping-pong buffering module 2 performs ping-pong buffering on the parallel data according to frames. Ping-pong buffering means that according to the ping-pong buffering mechanism, when receiving a frame of data and writing it into the buffer, the previous frame of data is output at the same time. The gain calculation module 3 calculates the gain value according to each path of parallel data. The output buffering module 4 obtains the current frame of parallel data from the ping-pong buffering module 2 and multiplies it by the gain value output by the gain calculation module 3 to obtain the gain-adjusted data for output.

[0036] In this embodiment, the serial-to-parallel conversion module 1 converts the digital serial data into parallel data to form a parallel processing structure. At the same time, the ping-pong buffering module 2 first performs ping-pong buffering on each path of parallel data, calculates the gain value at the same time, and then the output buffering module 4 caches the current frame of data buffered by the ping-pong buffering module again and multiplies it by the gain value corresponding to the current frame of data, realizing automatic gain adjustment based on the dual-buffering structure. Since the parallel data has passed through the ping-pong buffering, each automatic gain adjustment acts on the current frame of data every time, and there will be no lag adjustment of the gain, effectively eliminating the lag of the gain adjustment and avoiding the delay of the gain adjustment. Combining the parallel structure and the dual-buffering structure can effectively improve the accuracy and efficiency of the automatic gain adjustment, enabling it to meet the high-performance requirements of high-speed serial data for automatic gain adjustment. Moreover, the entire adjustment process does not need to rely on an additional adjustment process, and can also reduce the complexity of the entire adjustment process while ensuring the adjustment efficiency and accuracy.

[0037] In this embodiment, first, the serial-to-parallel conversion module 1 converts the original serial data of A / D (analog-to-digital conversion) into N paths of parallel data x01(k)~x0N(k), and the specific value of N can be determined according to actual requirements.

[0038] In this embodiment, a parallel filtering module 5 is further provided at the output end of the serial-to-parallel conversion module 1, which is used to perform low-pass filtering on each path of parallel data to obtain the filtered signals x11(k)~x1N(k). After low-pass filtering, the signal spikes can be removed.

[0039] In this embodiment, the gain obtaining module 3 includes a maximum value calculation unit 31 and a gain determination unit 32 which are connected to each other. The maximum value calculation unit 31 is used to calculate the maximum value XW(k) in each path of parallel data, that is, the largest path of parallel data. The gain determination unit 32 is used to determine the gain value A according to the calculated maximum value, that is, the number of bits by which the data needs to be shifted and amplified. By obtaining the maximum value in each path of parallel data to determine the gain value, only a small amount of computing resources are required to quickly and efficiently obtain the real-time gain value.

[0040] In this embodiment, the maximum value calculation unit 31 specifically includes an absolute value circuit 311, a data bitwise OR circuit 312, and a maximum value circuit 313 which are connected in sequence. The absolute value circuit 311 performs an absolute value operation on each path of parallel data and outputs it to the data bitwise OR circuit 312. After the data bitwise OR circuit 312 performs a bitwise OR operation on each path of parallel data after taking the absolute value with the data of the previous moment respectively, the maximum value circuit 313 obtains the maximum value of each path of parallel data. The above maximum value calculation unit 31 forms an open-loop circuit structure through the absolute value circuit 311, the data bitwise OR circuit 312, and the maximum value circuit 313. By obtaining the maximum value in real time through the data bitwise OR method, the gain value can be obtained. Based on the open-loop circuit structure, the gain value can be obtained in real time and quickly, without relying on additional parameter adjustment, which can further reduce the computing resources and complexity of gain adjustment and improve the adjustment efficiency.

[0041] In this embodiment, the filtered signals x11(k) to x1N(k) output by the parallel filtering module 5 are taken the absolute value by the absolute value circuit 311 to obtain h11(k) = |x11(k)|,..., h12(k) = |x12(k)|, and the parallel data h11(k) to h1N(k) after taking the absolute value are obtained. The parallel data h11(k) to h1N(k) after taking the absolute value pass through the data bitwise OR circuit 312, and perform a bitwise OR operation on each path of data with the data of the previous moment, that is, w11(k) = w11(k - 1)|h11(k),..., w1N(k - 1)|h1N(k), to obtain the highest bit w11(k) to w1N(k - 1) of the maximum value of each path of parallel data. After passing through the maximum value circuit 313, the maximum value XW(k) of w11(k) to w1N(k - 1) is obtained to obtain the maximum value of the total data.

[0042] It can be understood that, in addition to adopting the above structure, the maximum value calculation unit 31 can of course also adopt other structures such as bubble comparison to implement, and can be specifically determined according to actual needs.

[0043] In this embodiment, the gain determination unit 32 specifically adopts a moving average filter circuit. The moving average circuit performs moving average filtering on the maximum value signal determined by the maximum value calculation unit 31 and outputs the gain value A, that is, the amplification factor. Specifically, the gain determination unit 32 obtains the maximum value of the XW(k) data frame with a length of L through bubble comparison, and smooths the maximum value T times according to the maximum value. That is, before obtaining a total of T maximum values, the output is based on the currently obtained amplification factor. When the number of times is greater than T, the maximum value is subjected to moving average filtering, and the gain value A is output. It can be understood that in addition to adopting the above-mentioned moving average filter circuit, the gain determination unit 32 can of course also be implemented using a low-pass filter such as IIR or FIR according to actual requirements, or even implemented using other types of filters. The above cache length L can also be specifically configured according to actual requirements.

[0044] In this embodiment, the ping-pong cache module 2 includes a ping-pong control input unit 21, a ping-pong cache unit 22, and a ping-pong control output unit 23 that are connected in sequence. When the ping-pong control input unit 21 controls the storage of the current frame parallel data in a storage area of the ping-pong cache unit 22, the ping-pong control output unit 23 controls the output of the previous frame parallel data. When the ping-pong control output unit 23 controls the output of the current frame parallel data, the ping-pong control input unit 21 controls the storage of the next frame parallel data in another storage area of the ping-pong cache unit 22 to cache the real-time access parallel data according to the ping-pong cache mechanism. A ping-pong cache area with a length of L is specifically configured in the ping-pong cache unit 22, and the specific length value of L can be configured according to actual requirements.

[0045] Such as Figure 4As shown in the figure, when the ping-pong buffer module 2 performs ping-pong buffering, at the initial moment (moment 0), the current frame parallel data x11(0)~x1N(0) is cached into buffer 1. At the same time, at the current moment, the gain calculation module 3 calculates the corresponding gain A for the current frame parallel data x11(0)~x1N(0). During the same time period (moment 0) when the current frame parallel data x11(0)~x1N(0) is cached, the output buffer module 4 does not work at this time; at the next moment (moment 1), the previous frame parallel data x11(0)~x1N(0) and the calculated gain are output to the output buffer module 4, and the next frame parallel data x11(1)~x1N(1) is cached into another buffer 2. The gain calculation module 3 calculates the corresponding gain A for the parallel data x11(1)~x1N(1). At this time, the output buffer module 4 outputs the result of multiplying the output buffer 1 (at this time, it is the parallel data x11(0)~x1N(0)) by the gain; at the next moment (moment 2), the previous frame parallel data x11(1)~x1N(1) and the calculated gain are output to the output buffer module 4, and the next frame parallel data x11(2)~x1N(2) is cached into buffer 1. At this time, the output buffer module 4 outputs the result of multiplying the output buffer 2 (at this time, it is the parallel data x11(1)~x1N(1)) by the gain. This process is repeated until the gain control is completed.

[0046] In this embodiment, the ping-pong buffer is used to keep the parallel data stream sent to the output buffer module 4 in real-time and continuously for automatic gain adjustment calculation, so that the gain value obtained each time during automatic gain adjustment can exactly act on the current frame data in real-time without lag, eliminating the lag of automatic gain adjustment. And based on the ping-pong buffer mechanism, the caching and output of parallel data can be executed synchronously, which can ensure the continuous output of the parallel data stream for gain adjustment, so as to meet the real-time and efficient processing requirements of high-speed serial data. By adjusting the data cache length, different application scenarios can be adapted, making the application highly flexible.

[0047] In this embodiment, the input buffer module 4 is used to multiply the cached parallel data by the gain to obtain the gain result, as Figure 4 shown, the parallel data is alternately input to the input buffer 4 module through the ping-pong buffer output control to calculate the gain result. In this embodiment, the output buffer module 4 specifically includes an input buffer unit 41, a multiplication unit 42, and an output unit 43 connected in sequence. The input buffer unit 41 caches the current frame parallel data received from the ping-pong buffer module 2 in accordance with the ping-pong control method and controls the output to the multiplication unit 42. The multiplication unit 42 multiplies the current frame parallel data by the determined gain value to obtain the gain-adjusted result corresponding to the current frame data, and outputs it through the output unit 43.

[0048] In a specific application embodiment, when the output buffer module 4 works, it outputs the parallel data of the current frame cached by the ping-pong buffer module 2 in real time, multiplies it by the gain value A obtained by the gain calculation module 3, and outputs N-way parallel data to achieve ping-pong caching of data again; for the next frame of data, the serial conversion module 1 is restarted. At this time, the difference is that the next frame of data is stored in another cache, and the output is also from another cache during ping-pong output, so as to use the ping-pong cache mechanism to ensure that the gain calculated each time acts on the current data.

[0049] In the above digital automatic gain adjustment device of the present invention, each gain adjustment acts on the current frame of data. Because the adjustment has no delay and is executed in parallel, it can meet the requirements of high-speed data processing, is flexible to use and has strong adaptability. At the same time, there is no need for a complex iteration process during the adjustment, so there is no convergence problem. It is not only easy to implement but also has a stable output. It can achieve timely adjustment of the gain and ensure the maximum gain to reduce the precision loss of backend data processing.

[0050] The present invention can specifically be applied between different algorithm processing modules to reduce the influence of the truncation precision loss of the upper-level algorithm module on the processing structure of the lower-level module, or be applied to provide a full-scale input for the lower-level algorithm to ensure that as many significant bits of the data are retained as possible after truncation processing to reduce the signal-to-noise ratio loss of digital processing. It can also be directly applied to automatic gain adjustment after the original data of analog-to-digital conversion.

[0051] Embodiment 2:

[0052] Such as Figure 5 shown, the steps of the digital automatic gain control method based on dual caching in this embodiment include:

[0053] S01. Receive the digital serial data to be controlled and convert it into multiplexed parallel data;

[0054] S02. Perform ping-pong caching on the parallel data according to frames, and calculate the gain value according to each path of parallel data;

[0055] S03. Obtain the parallel data of the current frame from the data cached by the ping-pong buffer, and multiply it by the calculated gain value to obtain the gain-adjusted data for output.

[0056] In this embodiment, the method is adopted. Since the parallel data has passed through the ping-pong cache, each automatic gain adjustment acts on the current frame data, and there will be no lag adjustment of the gain, which effectively eliminates the lag of the gain adjustment and avoids the gain adjustment delay. Combined with the parallel structure and the double cache structure, the accuracy and efficiency of the automatic gain adjustment can be effectively improved, so that the high performance requirements of the automatic gain adjustment of high-speed serial data can be met, and the entire adjustment process does not need to rely on an additional adjustment process. It can also reduce the complexity of the entire adjustment process while ensuring the adjustment efficiency and accuracy.

[0057] In step S02 of this embodiment, the parallel data is ping-pong cached according to the frame, including: according to the ping-pong cache mechanism, when the current frame parallel data is stored in a storage area, the previous frame parallel data is controlled to be output, and when the current frame parallel data is output, the next frame parallel data is controlled to be stored in another storage area. The parallel data stream is kept to be sent to the automatic gain adjustment calculation in real time and continuously through the ping-pong cache, so that the gain value obtained each time during the automatic gain adjustment can be just in real time Act on the current frame data without lag, eliminating the lag of the automatic gain adjustment, and based on the ping-pong cache mechanism, the caching and output of the parallel data can be performed synchronously, which can ensure that the parallel data stream is continuously output for gain adjustment, so that the real-time and efficient processing requirements of high-speed serial data can be met.

[0058] In step S02 of this embodiment, obtaining the gain value according to each parallel data includes: performing an absolute value operation on each parallel data, performing a bitwise OR operation on each parallel data after the absolute value is obtained and the data at the previous moment, and then obtaining the maximum value of each parallel data. Specifically, the maximum value obtaining circuit or other gain value obtaining structure as in embodiment 1 can be used to implement this step.

[0059] This embodiment further includes a step of performing low-pass filtering on each channel of parallel data after step S01 and before step S02 to remove burrs in the signal.

[0060] In this embodiment, step S03 includes: according to the ping-pong control mode, controlling the current frame parallel data received in the ping-pong buffer to be cached, and multiplying the current frame parallel data by the determined gain value to obtain a gain-adjusted result output corresponding to the current frame data.

[0061] The digital automatic gain control method based on double buffering of the present invention corresponds to the digital automatic gain control device based on double buffering described above one by one, and the principles of the two are the same, which will not be described one by one here.

[0062] Embodiment 3:

[0063] In this embodiment, the digital automatic gain control is implemented using the same principle as in Embodiments 1 and 2 in a specific application embodiment. Here, the number of parallel paths N is taken as 4. As Figure 6 shown, the detailed process of implementing the digital automatic gain control is as follows:

[0064] Step 1: Convert the original serial signal of A / D (analog-to-digital conversion) into N parallel signals, and parallel-convert them into data x01(k), x02(k), x03(k), and x04(k);

[0065] Step 2: After the original parallel data signal passes through parallel low-pass filtering, remove the glitch components in the signal to obtain x11(k), x12(k), x13(k), and x14(k). At the same time, send the data into a ping-pong buffer with a length of L;

[0066] Step 3: Take the absolute value of each path of filtered data, h11(k) = |x11(k)|, h12(k) = |x12(k)|, h13(k) = |x13(k)|, h14(k) = |x14(k)|. The processing of the absolute value can be completed within a single clock;

[0067] Step 4: Perform a bitwise OR operation on each path of parallel data with the data of the previous moment, that is, w11(k) = w11(k - 1) | h11(k), w12(k) = w12(k - 1) | h12(k), w13(k) = w13(k - 1) | h13(k), w14(k) = w14(k - 1) | h14(k);

[0068] Step 5: Obtain the maximum value XW(k) of the four paths of data;

[0069] Step 6: Obtain the maximum value of the data frame with a length of L, and smooth the maximum value T times according to the maximum value. That is, before obtaining the maximum value T times in total, output according to the amplification factor obtained currently. When the number of times is greater than T times, perform a moving average filter on the maximum value and output the gain value A;

[0070] Step 7: Start outputting the data stored in the buffer in Step 2, multiply it by the gain value A, and output N parallel paths of data to ping-pong buffer the data again;

[0071] Step 8: Receive the next frame of data and return to Step 1. When executing to Step 2, store the parallel data in another buffer, and also output from another buffer during ping-pong output to ensure that the gain obtained each time acts on the current data;

[0072] Step 9: Repeat the above process to achieve timely adjustment of the gain and ensure maximum gain, so as to reduce the accuracy loss of the subsequent data processing.

[0073] The above are only the preferred embodiments of the present invention and do not impose any formal restrictions on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A digital automatic gain control device based on double buffering, characterized in that: It includes a serial-parallel conversion module (1), a ping-pong buffer module (2), a gain calculation module (3), and an output buffer module (4). The serial-parallel conversion module (1) is connected to the output buffer module (4) through the ping-pong buffer module (2) and the gain calculation module (3) respectively. The serial-parallel conversion module (1) receives the digital serial data to be controlled and converts it into multi-channel parallel data. The ping-pong buffer module (2) performs ping-pong buffering on each channel of the parallel data according to frames. The gain calculation module (3) calculates the gain value based on each channel of the parallel data. The output buffer module (4) obtains the current-frame parallel data from the ping-pong buffer module (2) and multiplies it by the gain value output by the gain calculation module (3) to obtain the data output after gain adjustment. The gain calculation module (3) includes a maximum value calculation unit (31) and a gain determination unit (32) connected to each other. The maximum value calculation unit (31) is used to calculate the maximum value in each channel of the parallel data, and the gain determination unit (32) is used to determine the gain value based on the calculated maximum value. The ping-pong buffer module (2) includes a ping-pong control input unit (21), a ping-pong buffer unit (22), and a ping-pong control output unit (23) connected in sequence. When the ping-pong control input unit (21) controls to store the current-frame parallel data in a storage area of the ping-pong buffer unit (22), the ping-pong control output unit (23) controls to output the previous-frame parallel data, so as to cache the parallel data in real time according to the ping-pong buffer mechanism.

2. The digital automatic gain control device based on double buffering according to claim 1, wherein The maximum value calculation unit (31) includes an absolute value taking circuit (311), a bitwise OR circuit (312), and a maximum value taking circuit (313) connected in sequence. The absolute value taking circuit (311) performs an absolute value taking operation on each channel of the parallel data and outputs it to the bitwise OR circuit (312). The bitwise OR circuit (312) performs a bitwise OR operation on each channel of the parallel data after taking the absolute value with the data at the previous moment respectively, and then the maximum value taking circuit (313) calculates the maximum value of each channel of the parallel data.

3. The digital automatic gain control device based on double buffering according to any one of claims 1 to 2, characterized in that A parallel filter module (5) is further provided at the output end of the serial-parallel conversion module (1) for performing low-pass filtering on each channel of the parallel data.

4. The digital automatic gain control device based on double buffering according to any one of claims 1 to 2, characterized in that: The output buffer module (4) includes an input buffer unit (41), a multiplication unit (42), and an output unit (43) connected in sequence. The input buffer unit (41) caches the current-frame parallel data of the ping-pong buffer module (2) according to the ping-pong control method and controls to output it to the multiplication unit (42). The multiplication unit (42) multiplies the current-frame parallel data by the determined gain value to obtain the result of the gain adjustment corresponding to the current-frame data, and outputs it through the output unit (43).

5. A digital automatic gain control method based on double buffering, characterized in that the steps It includes: S01. Receive the digital serial data to be controlled and convert it into multi-channel parallel data; S02. Perform ping-pong buffering on each channel of the parallel data according to frames, and calculate the gain value based on each channel of the parallel data; S03. Obtain the parallel data of the current frame from the data in the ping-pong buffer, multiply it by the obtained gain value, and output the data after gain adjustment; In step S02, obtaining the gain value according to the parallel data of each path includes: performing an absolute value operation on the parallel data of each path, and after performing a bitwise OR operation on the parallel data of each path after taking the absolute value with the data at the previous moment respectively, obtaining the maximum value of the parallel data of each path; In step S02, storing the parallel data in a ping-pong buffer according to frames includes: according to the ping-pong buffer mechanism, when controlling to store the parallel data of the current frame in one storage area, controlling to output the parallel data of the previous frame, and when outputting the parallel data of the current frame, controlling to store the parallel data of the next frame in another storage area.

6. The digital automatic gain control method based on double buffering according to claim 5, characterized in that Step S03 includes: according to the ping-pong control method, controlling to receive and cache the parallel data of the current frame in the ping-pong buffer, and multiplying the parallel data of the current frame by the determined gain value to output the result after gain adjustment corresponding to the data of the current frame.

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