Level conversion circuit and conversion method for chip IO port level to serial port level

Abstract

The present invention discloses a level conversion circuit and method for converting chip IO port level to serial port level. Existing serial port chips are expensive. The level conversion circuit of the present invention includes a filter resistor, a ceramic capacitor, a Schottky diode, a PNP transistor, two control resistors, and three return resistors. The filter resistor and ceramic capacitor form a low-pass filter. The PNP transistor serves as an electronic switch, and the two control resistors control the on and off state of the PNP transistor. During use, the positive power input and negative power input of the level conversion circuit are connected to the positive power supply and negative power supply of the chip PCB, respectively. The chip-side level terminal is connected to the chip's IO port, and the serial port-side level terminal is connected to the communication port of an external device requiring a serial port level. The chip IO level can be converted to a standard serial port level by the conversion circuit. The present invention ensures safe and reliable serial port level conversion through a simple and stable circuit, and can freely adjust the voltage at the serial port level terminal.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a level conversion circuit and a conversion method for converting a chip IO port level to a serial port level. Background Art

[0002] Chips are large-scale integrated circuits (LICIs) containing numerous digital and analog modules. However, the voltage levels of their IO ports are relatively low (mostly 3.3V). If the chip communicates with higher voltages, such as the commonly used RS232 serial peripheral, which specifies a high voltage range of -3V to -15V and a low voltage range of 3V to 15V, a level conversion circuit is required to convert the chip's IO voltage levels to RS232 serial port voltage levels. Currently, the chip industry offers serial port chips, such as the MAX232 / MAX3232, to address this issue. While these serial port chips are convenient to use, they are expensive. Especially with the current shortage and high cost of integrated chips, and given the high overall chip cost, level conversion circuits designed with simple discrete components such as transistors, resistors, and diodes are highly desirable. Summary of the Invention

[0003] One object of the present invention is to address the deficiencies in the prior art and to provide a level conversion circuit for converting a chip IO port level to a serial port level.

[0004] The level conversion circuit of the present invention includes a filter resistor R, a ceramic capacitor C, a Schottky diode D, a PNP transistor Q, two control resistors and three return resistors; the filter resistor R and the ceramic capacitor C are used to form a low-pass filter; the PNP transistor Q serves as an electronic switch, and the two control resistors control the conduction and shutdown of the PNP transistor Q.

[0005] One end of the first return resistor Rh1 is connected to one end of the first control resistor Rk1, serving as the chip-side level terminal. The other end of the first control resistor Rk1 and one end of the second control resistor Rk2 are connected to the base of the PNP transistor Q. The other end of the second control resistor Rk2 is connected to the emitter of the PNP transistor Q, serving as the positive power input terminal VDD. One end of the second return resistor Rh2 is connected to the cathode of the Schottky diode D, serving as the negative power input terminal VCC. One end of the third return resistor Rh3 and one end of the filter resistor R are connected to the collector of the PNP transistor Q. The other end of the third return resistor Rh3 is connected to the anode of the Schottky diode D. The other end of the filter resistor R is connected to one end of the ceramic capacitor C, serving as the serial port-side level terminal. The other ends of the first return resistor Rh1, the second return resistor Rh2, and the ceramic capacitor C are grounded.

[0006] The resistance value R1 of the first control resistor Rk1 and the resistance value R2 of the second control resistor Rk2 are set to meet the following conditions:

[0007] Among them, V EB is the emitter-base junction threshold voltage of the PNP transistor Q, V DD is the voltage of the positive power input terminal VDD, V IOL V is the low level voltage output by the chip IO port. IOH It is the high level voltage output by the chip IO port.

[0008] The resistance value R3 of the third reflux resistor Rh3 and the resistance value R4 of the filter resistor R are set to meet the conditions: Among them, V CC is the voltage of the negative power input terminal VCC, V D is the conduction voltage drop of Schottky diode D, R L It is the load resistance of the external device communication end at the serial port level.

[0009] Furthermore, R1 = 4.3 to 5.1 KΩ, R2 = 1.1 to 1.5 KΩ, R3 = 430 to 510 Ω, and R4 = 27 to 47 Ω.

[0010] Another object of the present invention is to provide a method for converting chip IO port level to serial port level.

[0011] Connect the positive power input terminal VDD of the level circuit to the positive power supply of the chip PCB printed board, connect the negative power input terminal VCC to the negative power supply of the chip PCB printed board, connect the chip side level terminal to the IO port of the chip, and connect the serial port side level terminal to the communication port of the external device that requires serial port level;

[0012] After the chip PCB is powered on, the positive power input terminal VDD and the negative power input terminal VCC are powered by positive and negative power.

[0013] When the chip IO port outputs a low level, the voltage V1 at the positive power input terminal VDD passes through the second control resistor Rk2 and the first control resistor Rk1, and then flows back to the ground through the chip side level terminal and the first return resistor Rh1 respectively; the voltage V1 generates a voltage V2 on the second control resistor Rk2 that is greater than the emitter-base junction threshold voltage VEB of the PNP transistor Q, the PNP transistor Q is saturated and turned on, and the voltage V2 is clamped at the threshold voltage VEB by the emitter-base junction of the PNP transistor Q; the voltage V1 at the positive power input terminal VDD passes through the emitter junction of the PNP transistor Q, and then passes through the third return resistor Rh3, the Schottky diode D and the second return resistor Rh2 to the return ground, and the other way passes through the filter resistor R to obtain a positive voltage V3 at the serial port side level terminal with a voltage value close to the voltage V1. The positive voltage V3 meets the serial port low level standard.

[0014] When the chip IO port outputs a high level, the voltage V1 at the positive power input terminal VDD flows back to ground after passing through the second control resistor Rk2, the first control resistor Rk1, and the first return resistor Rh1. At the same time, the high level output by the chip IO port flows back to ground through the first return resistor Rh1. The voltage V1 generates a voltage V4 on the second control resistor Rk2 that is less than the emitter-base junction threshold voltage VEB of the PNP transistor Q, causing the PNP transistor Q to be cut off. The voltage V1 at the positive power input terminal VDD is disconnected by the emitter junction of the PNP transistor Q. The serial port side level end passes through the filter resistor R, the third return resistor Rh3, and the Schottky diode D, and then flows back to ground through the negative power input terminal VCC and the second return resistor Rh2 respectively. The serial port side level end obtains a negative voltage V5, which meets the standard of the serial port high level.

[0015] The on and off states of the PNP transistor Q are determined by the preset adjustment of the first control resistor Rk1 and the second control resistor Rk2, and the voltage value of the level end on the serial port side is determined by the preset adjustment of the filter resistor R and the third return resistor Rh3.

[0016] The present invention disposes a PNP transistor switch, an RC filter circuit, a Schottky diode, three return resistors, and two control resistors between the chip-side level terminal and the serial port-side level terminal. When the chip-side level terminal signals a low level, the PNP transistor switch turns on, and the serial port-side level terminal receives the voltage provided by the positive power input terminal VDD. When the chip-side level terminal signals a high level, the PNP transistor switch turns off, and the serial port-side level terminal receives the voltage provided by the negative power input terminal VCC. The method of the present invention is safe and reliable, ensuring safe and reliable serial port level conversion through a simple and stable circuit. The present invention can freely adjust the voltage of the RS232 level terminal, and the level conversion circuit and level conversion method are safe and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the level conversion circuit of the present invention. DETAILED DESCRIPTION

[0018] The technical solution of the present invention is further described below with reference to the embodiments.

[0019] like Figure 1 As shown in the figure, the chip's IO port level-to-serial port level conversion circuit includes a filter resistor R, a ceramic capacitor C, a Schottky diode D, a PNP transistor Q, two control resistors, and three return resistors. The filter resistor R and the ceramic capacitor C form a low-pass filter. The PNP transistor Q acts as an electronic switch, and the two control resistors control its on and off states.

[0020] One end of the first return resistor Rh1 is connected to one end of the first control resistor Rk1 as a chip side level end;

[0021] The other end of the first control resistor Rk1 and one end of the second control resistor Rk2 are connected to the base of the PNP transistor Q, and the other end of the second control resistor Rk2 is connected to the emitter of the PNP transistor Q as the positive power input terminal VDD (+5V); one end of the second return resistor Rh2 is connected to the cathode of the Schottky diode D as the negative power input terminal VCC (-12V);

[0022] One end of the third return resistor Rh3 and one end of the filter resistor R are connected to the collector of the PNP transistor Q. The other end of the third return resistor Rh3 is connected to the anode of the Schottky diode D. The other end of the filter resistor R is connected to one end of the ceramic capacitor C to serve as the serial port side level terminal.

[0023] The other ends of the first return resistor Rh1 , the second return resistor Rh2 , and the ceramic capacitor C are grounded.

[0024] During use, connect the positive power input terminal VDD of the level circuit to the positive power supply (+5V) of the chip PCB printed board, connect the negative power input terminal VCC to the negative power supply (-12V) of the chip PCB printed board, connect the chip side level terminal to the IO port of the chip, and connect the serial port side level terminal to the communication port of the external device that requires serial port level.

[0025] After the chip PCB printed board is powered on, the positive power input terminal VDD and the negative power input terminal VCC are powered by positive and negative power.

[0026] When the chip's IO port outputs a low level, voltage V1 at the positive power input terminal VDD flows through the second control resistor Rk2 and the first control resistor Rk1, then returns to ground via the chip-side level terminal and the first return resistor Rh1. Voltage V1 generates a voltage V2 across the second control resistor Rk2, which is greater than the emitter-base threshold voltage VEB of PNP transistor Q. PNP transistor Q saturates and conducts, with voltage V2 clamped at the emitter-base junction of PNP transistor Q at the threshold voltage VEB. Voltage V1 at the positive power input terminal VDD flows through the emitter junction of PNP transistor Q, then flows through the third return resistor Rh3, Schottky diode D, and the second return resistor Rh2 to return ground. It then flows through filter resistor R, generating a positive voltage V3 at the serial port-side level terminal with a voltage close to voltage V1. Positive voltage V3 meets the serial port low level standard.

[0027] When the chip IO port outputs a high level, voltage V1 at the positive power input terminal VDD flows back to ground through the second control resistor Rk2, the first control resistor Rk1, and the first return resistor Rh1. Simultaneously, the high level output from the chip IO port flows back to ground through the first return resistor Rh1. Voltage V1 generates a voltage V4 across the second control resistor Rk2 that is less than the emitter-base threshold voltage VEB of PNP transistor Q, turning off PNP transistor Q. The voltage V1 at the positive power input terminal VDD is disconnected by the emitter-base junction of PNP transistor Q. The serial port level terminal flows back to ground through the filter resistor R, the third return resistor Rh3, and the Schottky diode D, respectively, through the negative power input terminal VCC and the second return resistor Rh2. This generates a negative voltage V5 at the serial port level terminal, which meets the serial port high level standard.

[0028] The on and off states of the PNP transistor Q are determined by the preset adjustment of the first control resistor Rk1 and the second control resistor Rk2, and the voltage value of the level end on the serial port side is determined by the preset adjustment of the filter resistor R and the third return resistor Rh3.

[0029] When the chip side level terminal outputs a low level, if it is found that the PNP transistor Q fails to saturate and conduct, and when the chip side level terminal outputs a high level, the PNP transistor Q fails to cut off, it is necessary to adjust the resistance value of the first control resistor Rk1 and the resistance value of the second control resistor Rk2. The settings of the resistance value R1 of the first control resistor Rk1 and the resistance value R2 of the second control resistor Rk2 meet the conditions: and V EB is the emitter-base junction threshold voltage of the PNP transistor Q (about 0.5V), V DD is the positive power input voltage (+5V), V IOL is the low level voltage (approximately 0) output by the chip IO port, V IOH It is the high level voltage output by the chip IO port.

[0030] V DD is 5V, V IOH When the voltage is 3.3V, preferably R1 = 4.3-5.1KΩ, R2 = 1.1-1.5KΩ. In this embodiment, R1 = 4.7KΩ, R2 = 1.3KΩ.

[0031] When the chip-side level terminal outputs a high level and the PNP transistor Q is turned off, if it is found that the negative voltage obtained by the RS232 level terminal is insufficient, it is necessary to adjust the resistance value R3 of the third return resistor Rh3 and the resistance value R4 of the filter resistor R. The settings of the resistance value R3 of the third return resistor Rh3 and the resistance value R4 of the filter resistor R meet the following conditions: V CC is the negative power input voltage (-12V), V Dis the conduction voltage drop of Schottky diode D (about 0.7V), R L It is the load resistor of the external device communication end at RS232 serial port level.

[0032] V CC When the voltage is -12 V, preferably R3 = 430-510Ω, R4 = 27-47Ω, and this embodiment uses R3 = 470Ω, R4 = 33Ω. The resistance values ​​of the first return resistor Rh1 and the second return resistor Rh2 are conventionally designed and set as needed.

Claims

1. A method for converting chip IO port level to serial port level, characterized in that: The following level conversion circuit is used: including a filter resistor R, a ceramic capacitor C, a Schottky diode D, a PNP transistor Q, two control resistors and three return resistors; the filter resistor R and the ceramic capacitor C are used to form a low-pass filter; the PNP transistor Q is used as an electronic switch, and the two control resistors control the conduction and shutdown of the PNP transistor Q; One end of the first return resistor Rh1 is connected to one end of the first control resistor Rk1 as a chip side level end; The other end of the first control resistor Rk1 and one end of the second control resistor Rk2 are connected to the base of the PNP transistor Q, and the other end of the second control resistor Rk2 is connected to the emitter of the PNP transistor Q as the positive power input terminal VDD; one end of the second return resistor Rh2 is connected to the cathode of the Schottky diode D as the negative power input terminal VCC; One end of the third return resistor Rh3 and one end of the filter resistor R are connected to the collector of the PNP transistor Q. The other end of the third return resistor Rh3 is connected to the anode of the Schottky diode D. The other end of the filter resistor R is connected to one end of the ceramic capacitor C to serve as the serial port side level terminal. The other ends of the first return resistor Rh1, the second return resistor Rh2, and the ceramic capacitor C are grounded; The specific conversion method is as follows: Connect the positive power input terminal VDD of the level circuit to the positive power supply of the chip PCB printed board, connect the negative power input terminal VCC to the negative power supply of the chip PCB printed board, connect the chip side level terminal to the IO port of the chip, and connect the serial port side level terminal to the communication port of the external device that requires serial port level; After the chip PCB is powered on, the positive power input terminal VDD and the negative power input terminal VCC are powered by positive and negative power. When the chip IO port outputs a low level, the voltage V1 at the positive power input terminal VDD passes through the second control resistor Rk2 and the first control resistor Rk1, and then flows back to the ground through the chip side level terminal and the first return resistor Rh1 respectively; the voltage V1 generates a voltage V2 on the second control resistor Rk2 that is greater than the emitter-base junction threshold voltage VEB of the PNP transistor Q, the PNP transistor Q is saturated and turned on, and the voltage V2 is clamped at the threshold voltage VEB by the emitter-base junction of the PNP transistor Q; the voltage V1 at the positive power input terminal VDD passes through the emitter junction of the PNP transistor Q, and then passes through the third return resistor Rh3, the Schottky diode D, and the second return resistor Rh2 to the return ground, and then passes through the filter resistor R to obtain a positive voltage V3 at the serial port side level terminal with a voltage value close to the voltage V1. The positive voltage V3 meets the serial port low level standard; When the chip IO port outputs a high level, the voltage V1 of the positive power input terminal VDD flows back to the ground after passing through the second control resistor Rk2, the first control resistor Rk1, and the first return resistor Rh1. At the same time, the high level output by the chip IO port flows back to the ground through the first return resistor Rh1; the voltage V1 generates a voltage V4 on the second control resistor Rk2 that is less than the emitter-base junction threshold voltage VEB of the PNP transistor Q, causing the PNP transistor Q to be cut off, and the voltage V1 of the positive power input terminal VDD is blocked by the PNP transistor Q. The emitter junction is disconnected; the serial port side level end passes through the filter resistor R, the third return resistor Rh3, and the Schottky diode D, and then returns to the ground through the negative power input terminal VCC and the second return resistor Rh2 respectively. The serial port side level end obtains a negative voltage V5, which meets the serial port high level standard; The on and off states of the PNP transistor Q are determined by the preset adjustment of the first control resistor Rk1 and the second control resistor Rk2, and the voltage value of the level end on the serial port side is determined by the preset adjustment of the filter resistor R and the third return resistor Rh3.

2. The method for converting chip IO port level to serial port level according to claim 1, wherein: The resistance value R1 of the first control resistor Rk1 and the resistance value R2 of the second control resistor Rk2 are set to meet the following conditions: and Among them, V EB is the emitter-base junction threshold voltage of the PNP transistor Q, V DD is the voltage of the positive power input terminal VDD, V IOL V is the low level voltage output by the chip IO port. IOH It is the high level voltage output by the chip IO port; The resistance value R3 of the third reflux resistor Rh3 and the resistance value R4 of the filter resistor R are set to meet the conditions: Among them, V CC is the voltage of the negative power input terminal VCC, V D is the conduction voltage drop of Schottky diode D, R L It is the load resistance of the external device communication end at the serial port level.

3. The method for converting chip IO port level to serial port level according to claim 2, wherein: The resistance value of the first control resistor Rk1 is R1=4.3~5.1KΩ, the resistance value of the second control resistor Rk2 is R2=1.1~1.5KΩ, the resistance value of the third return resistor Rh3 is R3=430~510Ω, and the resistance value of the filter resistor R is R4=27~47Ω.

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