The invention discloses a nuclear hardening D-latch, and belongs to the field of anti-nuclear reinforcement in integrated circuit reliability. The problem that according to existing anti-radiation D-latches, more hardware is needed, power consumption is high, delay time is long, and fault tolerance for flipped double nodes cannot be realized is solved. The latch of the invention includes two inverters I1 and I2, 28 NMOS transistors N1 to N28, and 12 PMOS transistors P1 to P12. Used devices are few, volume is small, a structure is simple, and due to that the used devices are few, power consumption of the entire latch is reduced, and hardware overheads are lower. A signal at an input end of the latch can be transmitted to an output port simply through one transmission gate, data transmissiontime is short, fault tolerance for any-single-node and double-node flipping can also be realized, and thus fault tolerance protection against single-node and double-node flipping is realized. The latch of the invention can provide protection for application of integrated circuit chips in high-radiation environments (such as aerospace and terrestrial nuclear power plants).