Method for forming an inductively coupled high density plasma film for a thin film transistor structure

Abstract

Embodiments of the present disclosure generally relate to methods of fabricating thin film transistors (TFTs). More specifically, the embodiments described herein relate to methods of depositing an insulating layer over a metal oxide layer using an inductively coupled plasma high density plasma process to improve electron mobility. The high density plasma includes an electron or ion plasma density greater than 1.0E11 / cm 3 3. The metal oxide layer is pre-treated with an inductively coupled plasma formed from N2O gas or a mixture of N2O gas and argon gas. An inductively coupled plasma formed from SiH4 gas and N2O gas is used to deposit the insulating layer, such as a silicon oxide layer. The silicon oxide layer serves as an etch stop layer, or the silicon oxide layer serves as a passivation layer for the TFT structure. The present disclosure is applicable to MO TFT structures and complementary MO TFT and LTPS TFT structures.

Description

[0001] Background

[0002] Field

[0003] Embodiments of the present disclosure generally relate to methods of fabricating thin film transistors (TFTs). More specifically, embodiments described herein relate to methods of depositing layers in thin film transistors having high electron mobility.

[0004] Description of the Related Art

[0005] Thin film transistors (TFTs) are metal-oxide layer semiconductor devices used in integrated circuits and displays to control pixel operation. Due to the high resolution, low power consumption, and high-speed operation of TFTs for LCD and OLED displays, they have generated great interest in display applications. Since the current materials used in the layers constituting the TFT typically have limited electron mobility with respect to each other and with respect to the method of depositing layers relative to the metal-oxide layer of the TFT.

[0006] Accordingly, there is a need in the art for improved TFTs and methods of fabricating TFTs. In particular, there is a need for insulating layers, such as passivation layers and etch stop layers for TFTs having a lower hydrogen content, higher density, lower wet etch rate, and lower plasma damage. Summary of the Invention

[0007] In one embodiment, a method of forming a thin film transistor is provided, including depositing a buffer layer over a substrate and forming a gate layer over the buffer layer. Etching a portion of the gate layer to form a gate electrode and depositing a gate insulating (GI) layer over the buffer layer and the gate electrode. Depositing a metal oxide layer over the GI layer. Depositing a passivation layer over the metal oxide layer using high density plasma chemical vapor deposition (HDP CVD) with inductively coupled plasma (ICP). The high density plasma includes an electron or ion plasma density greater than 1.0E11 / cm 3 of.

[0008] In another embodiment, a method of fabricating a thin film transistor is provided, including depositing a buffer layer over a substrate and forming a gate layer at least partially over the buffer layer. Depositing a gate insulating (GI) layer over the buffer layer and the gate layer, and depositing a metal oxide layer over the GI layer. Depositing an etch stop layer using high density plasma chemical vapor deposition (HDP CVD) with inductively coupled plasma (ICP), and forming source and drain electrodes in the etch stop layer. Depositing a passivation layer thereon using an inductively coupled plasma (ICP)- or capacitively coupled plasma (CCP)-based chemical vapor deposition process such as HDP CVD.

[0009] In another embodiment, a method is provided that includes forming a low-temperature polysilicon thin-film transistor (LTPS TFT) on a substrate and forming a metal-oxide thin-film transistor (MO TFT) on the substrate. The MO TFT includes a metal-oxide channel layer. A silicon oxide layer is deposited over the metal-oxide channel layer of the MO TFT and the layers of the LTPS TFT by using HDP CVD of ICP. The HDP includes an electron or ion plasma density greater than 1.0E11 / cm 3 2. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more particular description of the features briefly summarized above, reference may be had to the embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered as limiting the scope of the disclosure, and other equivalent embodiments are contemplated.

[0011] Figure 1 is a schematic cross-sectional view of a chamber according to one embodiment.

[0012] Figures 2A - 2H is a schematic cross-sectional view of a metal-oxide TFT at various stages of fabrication according to one embodiment.

[0013] Figure 2I is a schematic cross-sectional view of a metal-oxide TFT having a passivation layer according to one embodiment.

[0014] Figure 3 is a schematic cross-sectional view of a metal-oxide TFT having two passivation layers according to one embodiment.

[0015] Figure 4 is a schematic cross-sectional view of a metal-oxide TFT having an etch stop layer (ESL) and a passivation layer according to one embodiment.

[0016] Figure 5 is a schematic cross-sectional view of a metal-oxide TFT having two etch stop layers and a passivation layer according to one embodiment.

[0017] Figure 6 is a flow chart of an example method of fabricating an MO TFT structure according to one embodiment.

[0018] Figures 7A - 7G is a schematic cross-sectional view of a metal-oxide TFT and a low-temperature polysilicon (LTPS) TFT at various stages of fabrication according to one embodiment.

[0019] Figure 7GSchematic cross-sectional view of an MO TFT and an LTPS TFT having a passivation layer according to an embodiment.

[0020] Figure 8 Schematic cross-sectional view of an MO TFT and an LTPS TFT having a passivation layer and an etch stop layer according to an embodiment.

[0021] Figure 9 Schematic cross-sectional view of an MO TFT and an LTPS TFT having a passivation layer according to an embodiment.

[0022] Figure 10 Schematic cross-sectional view of an MO TFT and an LTPS TFT having an etch stop layer and a passivation layer according to an embodiment.

[0023] Figure 11 Flow chart of an exemplary inductively coupled plasma (ICP) high density plasma (HDP) process according to an embodiment.

[0024] For ease of understanding, the same reference numerals are used to denote the same elements common to the drawings whenever possible. It is contemplated that elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation. Detailed Description

[0025] The present disclosure generally relates to a method of manufacturing a TFT. The TFT has an active channel including a metal oxide such as indium gallium zinc oxide (IGZO) and / or zinc oxide. One or more passivation layers and / or one or more etch stop layers (ESLs) are disposed over the metal oxide. The interface between the metal oxide and the layer disposed over the metal oxide provides for predetermined TFT characteristics in some TFT applications. In particular, the method of processing and depositing layers over the metal oxide affects the TFT characteristics.

[0026] Methods of manufacturing thin film transistors (TFTs) are provided herein, including depositing a layer over a metal oxide channel layer using an inductively coupled plasma high density plasma process to improve the electron mobility of the interface between the metal oxide channel layer and / or the MO channel layer and the layer deposited by high density plasma chemical vapor deposition using inductively coupled plasma. As used herein, the term "high density plasma" refers to a plasma of electrons or ions having a density greater than, where the high density plasma includes greater than 1.0E11 / cm 3The electron or ion plasma density. The deposition process includes pretreating the metal oxide layer with N2O gas or with N2O gas and argon gas, exciting the gas to form an inductively coupled plasma, and then introducing SiH4 gas to deposit an interface layer containing silicon oxide. The interface layer is an etch stop layer, or the interface layer is a passivation layer of the TFT structure.

[0027] Figure 1 is a schematic cross-sectional view of chamber 100 that can be used to implement the embodiments described herein. Suitable chambers can be obtained from Applied Materials, Inc. of Santa Clara, California. It should be understood that the chambers described below are exemplary chambers, and other chambers including chambers from other manufacturers can be used together or modified to accomplish aspects of the present disclosure. Chamber 100 is configured to generate an inductively coupled high-density plasma.

[0028] Chamber 100 includes a chamber body 104, a lid assembly 106, and a substrate support assembly 108. The lid assembly 106 is disposed at the upper end of the chamber body 104. The substrate support assembly 108 is at least partially disposed within the interior space of the chamber body 104. The substrate support assembly 108 includes a substrate support 110 and a shaft 112 extending from the substrate support 110. The substrate support 110 has a support surface 114 for supporting at least one substrate 102. In one embodiment that can be combined with other embodiments described herein, the substrate 102 is a large area substrate, such as a substrate having a surface area generally of about 1 square meter or greater. However, the substrate 102 is not limited to any particular size or shape. In one aspect, the term "substrate" refers to any polygonal, square, rectangular, curved, or other non-circular workpiece.

[0029] The lid assembly 106 includes a diffuser 116 that extends across at least a portion of the upper end of the chamber body 104. One or more gas inlets 118 are coupled through the lid assembly to communicate a process gas from at least one gas source 120 to the diffuser 116. One or more gases from the gas source 120 flow through the diffuser 116 and into a processing region 124 located between the diffuser 116 and the substrate support 110. One or more gases are provided to the processing region 124 through a plurality of holes or openings (not shown) in the processing region 124 on a side facing the diffuser 116. A flow controller 122 (e.g., a mass flow control (MFC) device) is disposed between each diffuser inlet 118 and the gas source 120 to control the flow rate of the gas from the gas source 120 to the diffuser 116. In one embodiment, which may be combined with other embodiments described herein, the diffuser 116 is composed of a ceramic material, such as Al2O3. A pump 126 is in fluid communication with the interior space of the chamber and thus with the processing region 124. The pump 126 may be operated in conjunction with the mass flow controller 122 to control the pressure within the processing region 124 and to exhaust gases and by-products from the processing region 124.

[0030] Here, the lid assembly 106 includes at least one recess 128 that extends inwardly from the upper outer surface of the recess 128 and has one or more inductively coupled plasma generating components, coils 130, located therein and supported above at least one dielectric plate 132. Each dielectric plate 132 provides a physical barrier between the processing region 124 and the exterior of the chamber 100 and has the structural strength required to withstand the structural loads generated by the presence of atmospheric pressure in the recess 128 and a vacuum pressure in the interior space of the chamber body 104. Each coil 130 is connected to a power source 134 and to ground 138. In one embodiment, which may be combined with other embodiments described herein, each coil 130 is connected to the power source 134 through a matching box 136 that has a matching circuit for adjusting the electrical characteristics (such as impedance) of the coil 130 to "match" the electrical characteristics of the plasma formed in the processing region 124. Each coil 130 is configured to generate an electromagnetic field within the processing region that excites the gas in the processing region 124 into an inductively coupled high density plasma. A controller 158 is coupled to the chamber 100 and is configured to control various aspects of the chamber 100 during processing.

[0031] Figures 2A - 2I is a schematic diagram of a metal oxide (MO) TFT 200 at various manufacturing stages. As Figure 2AAs shown, the TFT 200 is fabricated by first depositing a buffer layer 202 over a substrate 102. The substrate 102 can include any suitable material, such as glass, soda-lime glass, polymers, and semiconductors for use in fabricating flat panel displays. Suitable substrates 102 include silicon-based substrates, insulating substrates, germanium-based substrates, and one or more common layers typically present in CMOS structures. It should be understood that other materials are also contemplated. The buffer layer 202 is formed by physical vapor deposition or other suitable deposition methods, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD). In some embodiments, which can be combined with other embodiments described herein, the buffer layer 202 is conformally formed using capacitively coupled plasma (CCP) or by high density plasma (HDP), such as inductively coupled high density plasma in chamber 100, as referenced Figure 1 as described. The buffer layer 202 is composed of a material that includes p-type silicon (e.g., boron-doped silicon), metal nitrides (e.g., aluminum nitride or tungsten nitride), metal oxides (e.g., vanadium oxide), or combinations thereof. In some embodiments, which can be combined with other embodiments described herein, the buffer layer 202 includes silicon oxide (SiO x ), silicon nitride (Si x N y ), and at least one of their combinations. Unless otherwise specified, any layer of the TFT can be deposited using any suitable deposition method known in the industry and / or described herein.

[0032] As Figure 2B shown, a gate layer 203 is deposited over the buffer layer 202. Suitable materials for the gate layer 203 include chromium, molybdenum, copper, aluminum, tungsten, titanium, and combinations thereof. The gate layer 203 can be formed by physical vapor deposition (PVD) or other suitable deposition methods, such as electroplating, electroless plating, or chemical vapor deposition (CVD). As Figure 2C shown, the gate layer 203 is patterned to form a gate electrode 204. Patterning includes forming a photolithographic mask or hard mask (not shown) over the gate layer 203 and exposing the gate layer 203 to an etchant mentioned herein as "etching". Depending on the material used in the gate layer 203, the gate layer 203 is patterned by exposing the portions of the gate layer 203 not covered by the mask to a wet etchant, or by exposing the portions of the gate layer 203 not covered by the mask to an etch plasma. In some embodiments, which can be combined with other embodiments described herein, the gate layer 203 is patterned by etching the portions of the gate layer 203 not covered by the mask with an etch plasma that includes sulfur hexafluoride gas, oxygen, chlorine, or combinations thereof. The described etch plasmas and etching processes can be used for any patterning and etching of any layer described herein.

[0033] As Figure 2D shown, a gate insulation (GI) layer 206 is deposited over a gate electrode 204. The GI layer 206 is formed using any deposition method described herein and known in the art. In some embodiments that may be combined with other embodiments described herein, the GI layer 206 is formed using HDP CVD or CCP CVD. In CCP, opposing electrodes are provided, such as parallel plate electrodes, with one of the electrodes coupled to ground and the other coupled to a power source, and a gas is introduced therebetween to form a virtual capacitor. By powering the energized electrode, electrical energy is capacitively coupled into the gas to form a plasma of the gas. The ion density of the plasma is a function of the power delivered to the gas. In contrast, in an ICP plasma, a coil surrounds or is above the gas region where the plasma is to be formed, and the electrical energy flowing through the coil is electromagnetically coupled into the gas to ionize or otherwise excite gas atoms or molecules. Again, the plasma ion density is a function of the energy coupled into the gas. In a CCP system, one of the electrodes is typically also the substrate support, so the power that can be coupled into the gas is limited by the potential negative impact of that power on the substrate. In contrast, using an ICP arrangement, the power that ionizes gas atoms and molecules is decoupled from the circuit components that hold the substrate in place, and higher power can be used to impart higher energy to the plasma, thereby achieving a higher ion density in the plasma without adversely affecting the substrate.

[0034] As Figure 2E shown, an active layer such as a metal oxide (MO) layer 207 is provided over the GI layer 206. The MO layer 207 is deposited by a suitable deposition method such as physical vapor deposition (PVD). The MO layer 207 is patterned using any patterning method described herein, such as by a wet etching process. In one embodiment that may be combined with other embodiments described herein, the MO channel layer 208 comprises oxygen (O) and at least one of the following: indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and hafnium (Hf). Examples of the MO channel layer 208 include but are not limited to InGaZnO, InZnO, InGaSnO, InZnSnO, InGaZnSnO, InSnO, HfInZnO, GaZnO, InO, AlSnZnO, ZnO, ZnSnO, AlZnO, AlZnSnO, HfZnO, SnO, and AlSnZnInO. Suitable materials for the MO layer 207 include IGZO and / or zinc oxide. As Figure 2F shown, the MO layer 207 is patterned by etching to form the MO channel layer 208. Any MO layer and / or MO channel layer may be a 1114 mol% InGaZnO layer.

[0035] As Figure 2G shown, the metal layer 210 is formed over the MO channel layer 208 and the exposed GI layer 206 by physical vapor deposition (PVD) or other suitable deposition methods, such as electroplating, electroless plating, or chemical vapor deposition (CVD). Unless otherwise specified, any process of PVD, electroplating, electroless plating, or CVD can be used for any metal layer described herein. The metal layer 210 is then patterned to form the source electrode 210A and the drain electrode 210B, and an opening 211 formed therebetween. The metal layer 210 is patterned using any suitable method described herein, such as a back-channel etching (BCE) process. Unless otherwise stated, each of the source electrode, drain electrode, and gate electrode described herein may include a conductive material, such as copper, titanium, tantalum, or any conductive metal. It should be understood that other materials are also contemplated.

[0036] The opening 211 over the MO channel layer 208 exposes a portion of the MO channel layer 208 at the bottom of the MO channel layer 208. As Figure 2I shown, a passivation layer 212 is formed over the MO channel layer 208, the exposed GI layer 206, and the source electrode 210A and the drain electrode 210B by a HDP CVD process using inductively coupled plasma. In Figures 2A to 2I the processes shown and described, the fabrication of an embodiment of a gate covered by a passivation layer is disclosed. The MO channel layer 208 within the opening 211 is pretreated before the HDP CVD process using ICP, after the source electrode and the drain electrode are formed, but before a passivation or etch stop layer is deposited on the source electrode and the drain electrode. The top surface of the MO channel layer 208 and / or the interface between the MO channel layer 208 and the layer to be deposited on the MO channel layer 208 (e.g., ESL or passivation layer) is considered to be chemically modified to have a high electron mobility.

[0037] Reference is made herein to Figure 11 the operating sequence of the HDP CVD process using inductively coupled plasma. The passivation layer (e.g., 212) is typically the topmost layer of the TFT device to protect the device from environmental damage, including chemically or mechanically induced damage. The passivation layer also provides stable and reliable TFT performance to resist long-term thermal and electrical bias stresses. Due to the sensitivity of metal oxide layers to hydrogen and other environmental chemicals, a high-quality, low-hydrogen oxide, such as the silicon oxide described herein, is provided as the passivation layer 212. In particular, in embodiments where the passivation layer is directly disposed over and in contact with the metal oxide layer of the gate, the HDP CVD process using inductively coupled plasma provides a silicon oxide composition with a low hydrogen content compared to silicon oxides produced by other forms of deposition. Although the passivation layer 212 is inFigure 2I is depicted as a single layer, but multiple passivation layers are contemplated, and reference is made to those described herein Figure 3 Provide one such example.

[0038] Figure 3 A first passivation layer 302 formed over the source electrode 210A, drain electrode 210B, and a portion of the MO channel layer 208 using a CCP CVD process is depicted, followed by a second passivation layer 304 deposited using an HDP CVD process with inductively coupled plasma to form a bottom-gate TFT 300. Here, since the second passivation layer 304 formed on the outermost or topmost layer of the TFT is formed using an HDP CVD process with inductively coupled plasma, it has a high-quality, stable, and low hydrogen content composition that can protect the MO channel layer from environmental damage and enhance electron mobility in the MO channel. In some embodiments that can be combined with other embodiments described herein, the MO channel layer 208 is pretreated with capacitively coupled plasma before depositing the first passivation layer 302 using CCP CVD. The first passivation layer 302 has a thickness of less than 100 nm. The second passivation layer 304 has a thickness of about 10 nm to about 300 nm. Without being bound by theory, it is believed that depositing the second passivation layer 304 over the first passivation layer 302 can increase the electron mobility of the MO channel layer 208 disposed below the first passivation layer 302.

[0039] Figure 4 An embodiment of a bottom-gate TFT 400 having an etch stop layer 402 deposited over the gate insulating layer 206 and gate electrode 204 is depicted. The etch stop layer 402 is deposited using an HDP CVD process with inductively coupled plasma and then patterned to form source electrode 410A and drain electrode 410B using any of the methods described herein for forming source and drain electrodes.

[0040] A passivation layer 404 is deposited over the source electrode 410A and drain electrode 410B and over the etch stop layer 402. The passivation layer 404 is deposited using any of the deposition methods disclosed herein, such as CCP CVD or HDP CVD. Figure 5 An embodiment of a bottom-gate TFT500 is depicted having a first etch stop layer 502 deposited using a CCP CVD deposition process, followed by a second etch stop layer 504 deposited using an HDP CVD process with inductively coupled plasma. Source electrode 510A and drain electrode 510B are formed in the first etch stop layer 502 and the second etch stop layer 504. A passivation layer 506 is deposited thereon using any of the methods disclosed herein, such as by CCP CVD, or by an HDP CVD process with inductively coupled plasma.

[0041] Figure 6 is a flow chart of an exemplary method of manufacturing an MO TFT structure according to one embodiment. In operation 602, a buffer layer (e.g., 202) is formed over a substrate (e.g., 102). In operation 604, a gate layer (e.g., 203) is deposited over the buffer layer, and in operation 606, at least a portion of the gate layer is etched to form a gate electrode (e.g., 204). In operation 608, a GI layer (e.g., 206) is deposited over the gate electrode, and in operation 610, a patterned metal oxide layer (e.g., 208) is formed over the GI layer. In operation 612, a passivation layer or an etch stop layer is deposited over the patterned metal oxide layer using HDP CVD with inductively coupled plasma.

[0042] Figures 7A - 7G is a schematic cross-sectional view of MO TFT 730 and LTPS TFT 720 (collectively referred to as TFT 700) at various stages of manufacture according to one embodiment. A first buffer layer 702 is formed over a substrate 102 in a manner similar to that described with reference Figure 2A above. A silicon layer is deposited over the buffer layer 702 and then etched using any of the methods described herein to form a low temperature polycrystalline silicon (LTPS) layer 704. A GI layer 706 is deposited over the low temperature polycrystalline silicon layer 704 and a gate 708 is formed using the patterning methods described herein. An interlayer dielectric (ILD) layer 710 is deposited over the GI layer 706 and the gate 708. Suitable materials for the ILD layer include silicon nitride, silicon oxide, and silicon oxynitride. Additionally, although shown as a single layer, it is contemplated that the ILD layer 710 may include multiple layers, each layer may include a different chemical composition. The ILD layer is deposited using any of the methods described herein, such as using HDPCVD or CCP CVD. A portion of the ILD layer 710 and a portion of the GI layer 706 are etched down to the LTPS layer 704 to form a first lower opening 711A and a second lower opening 711B. A first metal layer 713 (as Figure 7B shown) is formed. As Figure 7C shown, the first metal layer 713 is patterned to form a lower source via 712A, an intermediate source electrode pad 712C, an intermediate drain electrode pad 712D, and a lower drain via 712B of the LTPS TFT 720. Additionally, the first metal layer 713 is patterned to form a gate electrode 714 of the MO TFT 730.

[0043] Regarding the LTPS TFT 720, the lower source via 712A extends upward to the intermediate source electrode pad 712C, and the lower drain via 712B extends upward to the intermediate drain electrode pad 712D. As Figure 7D shown, a second buffer layer 716 is then formed thereover. As Figure 7EAs shown, a metal oxide layer 717 is deposited over the second buffer layer 716, and in Figure 7F , a portion of the metal oxide layer 717 is patterned to form the MO channel layer 718 of the MO TFT 730. The second buffer layer 716 is patterned to form a first upper opening 721A extending downward to the intermediate source electrode pad 712C and a second upper opening 721B extending downward to the intermediate drain electrode pad 712D of the LTPS TFT 720. A second metal layer (not shown) is deposited and patterned to form an upper source via 722A extending from the intermediate source electrode pad 712C to the upper source electrode pad 722C and an upper drain electrode via 722B extending from the intermediate drain electrode pad 712D to the upper drain electrode pad 722D of the LTPS TFT 720, as Figure 7G shown. The lower source via 712A, the intermediate source electrode pad 712C, the upper source via 722A, and the upper source electrode pad 722C together form the source electrode 742A. The lower drain via 712B, the intermediate drain electrode pad 712D, the upper drain electrode via 722B, and the upper drain electrode pad 722D together form the drain electrode 742B of the LTPS TFT 720.

[0044] The MO TFT source electrode 732A and the MO TFT drain electrode 732B are formed over the MO channel layer 718 of the MO TFT 730. The passivation layer 724 is deposited by an HDP CVD process using inductively coupled plasma to form the MO TFT 730 and the LTPS TFT 720 of the structure 700.

[0045] Figure 8 is a schematic cross-sectional view of a TFT structure 800 including an MO TFT 830 and an LTPS TFT 820 having a passivation layer 804 and an etch stop layer 802 according to an embodiment. The layers of the TFT structure 800 are deposited in a manner similar to that Figures 7A - 7E shown. The etch stop layer 802 is deposited over the MO channel layer 718 of the MO TFT 830 by an HDP CVD process using inductively coupled plasma. The etch stop layer 802 is patterned and an MO TFT source electrode via 832A is formed extending from the MO channel layer 718 to the MO TFT source electrode pad 832C. The MO TFT drain electrode 832B is formed to extend from the MO channel layer 718 to the MO TFT drain pad 832D in the MOTFT 830. The passivation layer 804 is deposited by CCP CVD or by HDP CVD.

[0046] Refer to Figure 8The LTPS TFT 820 depicted forms an upper source electrode via hole 822A extending from an intermediate source electrode pad 712C to an upper source electrode pad 822C, and forms an upper drain electrode via hole 822B extending from an intermediate drain electrode pad 712D to an upper drain electrode pad 822D of the LTPS TFT 820. The lower source via hole 712A, the intermediate source electrode pad 712C, the upper source via hole 822A, and the upper source electrode pad 822C together form a source electrode 842A. The lower drain via hole 712B, the intermediate drain electrode pad 712D, the upper drain electrode via hole 822B, and the upper drain electrode pad 822D together form a drain electrode 842B of the LTPS TFT 820.

[0047] Figure 9 is a schematic cross-sectional view of a TFT structure 900 including an MO TFT 930 and an LTPS TFT 920 having a passivation layer 906 according to one embodiment. The layers 702, 706, 708, and 710 of the TFT structure 900 are formed in the manner described with reference to Figure 7A FIG. In the same plane as the LTPS gate 708, an MO TFT gate 908 is formed in the MO TFT 930. The ILD layer 710 is formed thereon, and a second buffer layer 902 is formed on the ILD layer 710. Source electrodes 922A and drain electrodes 922B are formed in the second buffer layer 902, the ILD layer 710, and the GI layer 706 extending to the LTPS layer 704 of the LTPS TFT 920. Source electrodes 932A and drain electrodes 932B are formed around the metal oxide layer 904 in the MO TFT 930. The passivation layer 906 is formed thereon by HDP CVD using inductively coupled plasma. It has been found that a complementary structure including a p-type LTPS TFT and an n-type MO TFT can be formed and is suitable for applications such as semiconductor-based circuits. Conventional n-type MO TFT structures include an MO channel layer having an electron mobility of less than 30 cm 2 / Vsec, such as about 10 cm 2 / Vsec. In contrast, conventional p-type LTPS TFT structures include a layer having an electron mobility of about 80 cm 2 / Vsec to about 100 cm 2 / Vsec. Thus, the present disclosure has found that by using the methods described herein to increase the electron mobility in the MO channel layer of the MO TFT structure, the electron mobility difference between the LTPS TFT structure and the MO TFT structure can be improved. The electron mobility of the MO channel layer of the present disclosure is greater than 30 cm 2 / Vsec, such as greater than 50 cm 2 / Vsec, such as about 80 cm 2from about 100 cm / Vsec to about 100 cm / Vsec, or about 100 cm / Vsec 2 from about 100 cm / Vsec to about 400100 cm / Vsec 2 from about 100 cm / Vsec to about 400100 cm / Vsec 2 In addition, compared with the conventional method of forming a structure including an LTPS TFT and an MO TFT, the method described herein uses fewer masks.

[0048] Figure 10 is a schematic cross-sectional view of an MO TFT 1030 and an LTPS TFT 1020 (collectively referred to as the TFT structure 1000) having an etch stop layer (ESL) 1006 and a passivation layer 1008 according to an embodiment. In the TFT structure 1000, a second buffer layer 1002 is formed over the ILD layer 710. An MO channel layer 1004 is formed in the ESL 1006, and the ESL 1006 is formed using a HDP CVD process with inductively coupled plasma. Source electrodes 1022A and drain electrodes 1022B are formed in the LTPS TFT 1020, and source electrodes 1032A and drain electrodes 1032B are formed in the MO TFT 1030. The passivation layer 1008 is formed by CCP CVD or HDP CVD. In some embodiments that can be combined with other embodiments described herein, the MO channel layer of the MO TFT is disposed in the same plane as the gate of the LTPS TFT. In some embodiments that can be combined with other embodiments described herein, the MO channel layer of the MO TFT is disposed in a plane different from the gate electrode of the LTPS TFT. In some aspects thereof, the MO channel layer may undergo a pretreatment process before depositing a layer over the MO channel layer using HDP CVD with ICP. Figure 11 Example pretreatment and deposition processes are shown in the method 1100 and summarized in Table 1 below.

[0049] Table 1: Examples of HDP CVD Pretreatment and Deposition Using an ICP Process

[0050]

[0051] Figure 11 The operation 1102 includes a pretreatment process of pretreating its film layer using a pretreatment gas. In Figure 11 the operation 1102, the pretreatment gas includes nitrous oxide gas, argon gas, or a combination of oxygen-containing gas and argon gas to the processing region 124 of the processing chamber. The oxygen-containing gas is one or more of N2O gas, NO gas, O2 gas, O3 gas, such as N2O gas.

[0052] Before operation 1102, the substrate 102 is positioned within the processing region 124 to provide a spacing of from about 100 mm to about 300 mm between the diffuser 116 and the substrate 102. The introduction of the pretreatment gas includes introducing N2O gas at from about 0.3 sccm / cm 2 to about 0.7 sccm / cm 2 and introducing argon gas at from about 0 sccm / cm 2 to about 0.7 sccm / cm 2 As used herein, the unit "sccm / cm 2 " refers to the volumetric flow rate of gas in standard cubic centimeters per square centimeter of the surface area of the substrate. The pretreatment gas introduced into the processing space includes an N2O gas to argon gas ratio of from about 1:0 to about 1:2 by volume, such as from about 3:1 to about 1:1. In some embodiments that can be combined with other embodiments described herein, argon gas is not used together with the N2O gas.

[0053] The pretreatment processing pressure of the processing space is from about 10 mT to about 150 mT, such as from about 12 mT to about 120 mT. The pretreatment processing temperature of the substrate is from about 70 °C to about 350 °C, such as from about 70 °C to about 250 °C, and the pretreatment processing time is from about 5 seconds to about 60 seconds, such as from about 10 seconds to about 40 seconds. In some embodiments that can be combined with other embodiments described herein, the pretreatment gas is introduced into the processing space before being excited into a plasma.

[0054] In operation 1104, a plasma pretreatment is provided, including exciting the pretreatment gas within the processing space with ICP coil energy supplied at a frequency of from about 1 MHz to about 30 MHz, such as from about 2 MHz to about 15 MHz. In some embodiments that can be combined with other embodiments described herein, the plasma processing conditions described in Table 1 and operation 1104 are used to pretreat the MO channel layer after operation 1102. Alternatively, the conditions provided in operation 1104 can be used to pretreat the MO channel layer without using the conditions provided in reference operation 1102 for pretreatment. It has been found that a low ICP coil frequency reduces damage associated with exciting the plasma, increases uniformity, and reduces energy consumption. High plasma energy frequencies, such as those used in microwave chemical vapor deposition, use power with a frequency exceeding 100 MHz, such as 100 GHz, in the process of microwave chemical vapor deposition. High frequencies can be used for the HDP process described herein. However, an ICP coil frequency of from about 1 MHz to about 30 MHz, such as from about 2 MHz to about 15 MHz, excites the pretreatment gas to generate a plasma. Exciting the pretreatment gas includes from about 2.3 W / cm 2 to about 5.3 W / cm 2The power density provides electricity. As used herein, the term "power density" refers to the amount of electrical power provided per square centimeter of the exposed surface area of the substrate. The temperature of the substrate is maintained at about 70 °C to about 350 °C, such as about 70 °C to about 250 °C. The plasma pretreatment time is about 2 seconds to about 32 seconds. In some embodiments that can be combined with other embodiments described herein, the pretreatment gas is converted into an in-situ formed plasma before depositing the silicon oxide layer as described herein. Alternatively, the plasma is formed ex-situ and introduced into the processing space. It is believed that the plasma pretreatment process enhances the characteristics and performance of the metal oxide TFT under thermal bias stress. The plasma pretreatment is performed before forming the etch stop layer and / or the passivation layer. In some embodiments that can be combined with other embodiments described herein, the combination of the ranges of gas flow rate, power density, and frequency produces a low plasma density, which is sufficient to prepare the exposed film surface for subsequent silicon oxide layer deposition and provides a low potential and low ion bombardment that damages the fabricated TFT structure.

[0055] In operation 1106, at about 0.02 sccm / cm 2 to about 0.09 sccm / cm 2Silane (SiH4) gas is introduced to form a silicon oxide interface (e.g., an ESL or a passivation layer connected to the MO channel layer interface). In some embodiments, which can be combined with other embodiments described herein, the plasma conditions in operation 1104 are maintained during and after the addition of SiH4 gas at a ratio of N2O gas flow to SiH4 gas flow of about 5:1 to about 40:1 by volume. In some embodiments, the MO channel layer is not exposed to the pretreatment processes described in operations 1102 and 1104. In particular, the process conditions of operation 1106 described in the "deposition" column of Table 1 are applied to the MO channel layer without pretreatment. The spatial pressure in the processing region 124 is maintained at about 80 mT to about 12 mT. SiH4 gas is introduced for about 26 seconds to about 260 seconds. The silicon oxide interface layer (e.g., a passivation layer or an ESL) is formed to have a thickness of about 200 angstroms to about 2000 angstroms, such as about 500 angstroms to about 2000 angstroms. Based on atomic percentage, the hydrogen content of the silicon oxide interface layer produced by HDP CVD using inductively coupled plasma is about 1.9% at 250 °C, while the hydrogen content of the interface layer produced by CCP is about 3.5% at 250 °C. Additional operations (e.g., the post-deposition column described in Table 1) include annealing for about 5 seconds to about 15 seconds to maintain a temperature of about 70 °C to about 250 °C. Without being bound by theory, it is believed that the top surface of the exposed MO channel layer and / or the interface between the MO channel layer and the layer deposited thereon by HDP CVD using ICP are chemically and / or physically modified by one or more of operation 1102, operation 1104, operation 1106, and the post-deposition operation. It is believed that high electron mobility is achieved by increasing the electron carrier density in the MO channel layer and / or at the interface between the MO channel layer and the layer deposited on the MO channel layer. The mobility of the MO channel layer is greater than 30 cm / Vsec, such as greater than 60 cm / Vsec.

[0056] Example

[0057] An exemplary silicon oxide deposition process is provided and summarized in Table 2.

[0058] Table 2: Example process conditions for HDP CVD using ICP

[0059]

[0060]

[0061] Several TFT samples with a silicon oxide layer deposited therein were formed using the process conditions summarized in Table 2. It can be seen that each deposited layer provides a wet etch rate (WER) of less than 2600 Å / min, even at low substrate processing temperatures, such as 80 °C and 85 °C. The WER performance is significantly better than the typical WER of other deposition forms, which is usually higher than 4000, or higher than 6000, or higher than 8000 Å / min. The WER value is normalized to the thermal oxide WER, which is 1000 A / min. It was found that the Si-O peak position remained high throughout a wide temperature range from about 100 °C to about 300 °C, indicating high film quality and controllability over a wide range. The column "pitch" is defined by the distance (in mils) between the diffuser and the substrate.

[0062] In addition, for example films deposited by HDP CVD using inductively coupled plasma, the hydrogen concentration and film density were measured. Especially at low temperatures, the hydrogen content is much lower than that typically found using other processes. Other processes typically have a hydrogen concentration greater than 5%, for example about 6% at temperatures below 150 °C. The hydrogen concentration measured in the example films deposited by HDP CVD using inductively coupled plasma was about 2.7% at about 120 °C, 1.8% at about 225 °C, and 1.7% at about 340 °C. The film density of the example films deposited by HDP CVD using inductively coupled plasma had a film density of about 2.3 g / cm 3 The film density, measured by x-ray reflectivity, is higher than the typical film density of silicon oxide films deposited by other depositions. The film density of these films at about 250 °C is 2.2 g / cm 3 or lower.

[0063] Compared with complementary metal oxide semiconductors (CMOS), such as p-type polysilicon + n-type polysilicon structures, the TFT structures described herein use p-type LTPS TFTs and n-type MO TFTs to reduce the number of masks required to form a TFT structure with improved performance, stability, and electron mobility.

[0064] In summary, a method of manufacturing a thin film transistor (TFT) is provided, including depositing an interface layer on a metal oxide layer using an inductively coupled plasma high density plasma process to improve electron mobility. The deposition process includes pretreating the metal oxide layer with N2O gas or with N2O gas and argon, exciting the gas to form an inductively coupled plasma, and then introducing SiH4 gas to deposit an interface layer containing silicon oxide. The interface layer is an etch stop layer, or the interface layer is a passivation layer of the TFT structure.

[0065] While the foregoing is directed to examples of the present disclosure, other and further examples can be devised without departing from its basic scope, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A method of forming a thin film transistor, comprising the following steps: Depositing a buffer layer over a substrate; Forming a gate layer over the buffer layer; Etching at least a portion of the gate layer to form a gate electrode; Depositing a gate insulating layer over the buffer layer and the gate electrode; Forming a metal oxide channel layer over the gate insulating layer; And Depositing a passivation layer by high-density plasma chemical vapor deposition using inductively coupled plasma, wherein the high-density plasma comprises an electron or ion plasma density greater than 1.0E11 / cm 3 and wherein the electron mobility of the metal oxide channel layer is greater than 30 cm 2 / Vsec, Wherein the method further comprises pretreating the metal oxide channel layer, the pretreatment comprising: At a N2O gas flow rate of 0.3 sccm / cm 2 to 0.7 sccm / cm 2 the N2O gas is introduced into the processing space of the processing chamber, where the substrate is disposed in the processing space; at a power density of 2.3 W / cm 2 to 5.3 W / cm 2 excite the N2O gas; and Introduce SiH4 gas at a flow rate of 0.02 sccm / cm 2 to 0.09 sccm / cm 2 of SiH4 gas flow rate.

2. The method according to claim 1, wherein depositing the passivation layer comprises depositing an interface passivation layer by chemical vapor deposition using capacitively coupled plasma and depositing an upper passivation layer by high density plasma chemical vapor deposition using inductively coupled plasma.

3. The method according to claim 1, wherein pretreating the metal oxide channel layer is before depositing the passivation layer, and wherein pretreating the metal oxide channel layer comprises exposing the metal oxide channel layer to inductively coupled plasma.

4. The method according to claim 3, wherein the inductively coupled plasma is formed by nitrous oxide (N2O), Ar, or a combination thereof.

5. The method according to claim 1, wherein depositing the passivation layer comprises exciting N2O gas and silane (SiH4) gas to form the inductively coupled plasma and exposing the inductively coupled plasma to the metal oxide channel layer.

6. A method of forming a thin film transistor, comprising: Depositing a buffer layer over a substrate; Forming a gate layer at least partially over the buffer layer; Depositing a gate insulating layer over the buffer layer and the gate layer; Forming a metal oxide channel layer over the gate insulating layer; Depositing an etch stop layer by high density plasma chemical vapor deposition using inductively coupled plasma, wherein the high density plasma comprises an electron or ion plasma density greater than 1.0E11 / cm 3 ; Forming source and drain electrodes in the etch stop layer; and Depositing a passivation layer, wherein the electron mobility of the metal oxide channel layer is greater than 30 cm 2 / Vsec, Wherein the method further comprises pretreating the metal oxide channel layer, the pretreatment comprising: At a N2O gas flow rate of 0.3 sccm / cm 2 to 0.7 sccm / cm 2 the N2O gas is introduced into the processing space of the processing chamber, where the substrate is disposed in the processing space; With a power density of 2.3 W / cm 2 to 5.3 W / cm 2 excite the N2O gas; and Introduce SiH4 gas at a flow rate of 0.02 sccm / cm 2 to 0.09 sccm / cm 2 of SiH4 gas flow rate.

7. The method according to claim 6, wherein depositing the etch stop layer comprises depositing an interface etch stop layer by chemical vapor deposition using capacitively coupled plasma and depositing an upper etch stop layer by high density plasma chemical vapor deposition using inductively coupled plasma.

8. The method according to claim 6, wherein depositing the etch stop layer by high density plasma chemical vapor deposition comprises introducing N2O gas and SiH4 gas into the processing space at a ratio of N2O gas to SiH4 gas of 5:1 to 40:

1.

9. The method according to claim 8, wherein depositing the etch stop layer by high density plasma chemical vapor deposition comprises setting the inductively coupled plasma coil energy at a frequency of 1 MHz to 15 MHz.

10. The method according to claim 6, wherein introducing N2O gas into the processing space comprises introducing argon gas into the processing space, and wherein the processing space has a pressure of 15 mT to 120 mT and a processing temperature of 70 °C to 350 °C.

11. A method of forming a thin film transistor, comprising: Forming a low temperature polycrystalline silicon thin film transistor on a substrate; And A metal-oxide thin-film transistor including a metal-oxide channel layer is formed on the substrate, wherein forming the low-temperature polycrystalline silicon thin-film transistor and forming the metal-oxide thin-film transistor include depositing a silicon oxide layer on the metal-oxide channel layer by using inductively coupled plasma-enhanced chemical vapor deposition, wherein the high-density plasma includes an electron or ion plasma density greater than 1.0E11 / cm 3 and wherein the electron mobility of the metal-oxide channel layer is greater than 30 cm 2 / Vsec. The method further includes preprocessing the metal oxide channel layer, and the preprocessing includes: At a N2O gas flow rate of 0.3 sccm / cm 2 to 0.7 sccm / cm 2 the N2O gas is introduced into the processing space of the processing chamber, where the substrate is disposed in the processing space; at a power density of 2.3 W / cm 2 to 5.3 W / cm 2 excite the N2O gas; and Introduce SiH4 gas at a SiH4 gas flow rate of 0.02 sccm / cm 2 to 0.09 sccm / cm 2 .

12. The method according to claim 11, wherein forming the low temperature polycrystalline silicon thin film transistor and forming the metal oxide thin film transistor include the following steps: Depositing a first buffer layer on the substrate; Forming a low temperature polycrystalline silicon layer on the first buffer layer; Depositing a gate insulating layer on the first buffer layer and the low temperature polycrystalline silicon layer; Forming a gate layer at least partially on the gate insulating layer; Depositing an interlayer dielectric layer on the gate insulating layer and the gate layer; Depositing a second buffer layer; Forming the metal oxide channel layer on the second buffer layer; Depositing the silicon oxide layer on the metal oxide channel layer by high density plasma chemical vapor deposition using inductively coupled plasma.

13. The method according to claim 12, wherein forming the low temperature polycrystalline silicon thin film transistor further includes forming low temperature polycrystalline silicon source and drain electrodes before depositing the silicon oxide layer, and forming the metal oxide thin film transistor further includes forming metal oxide source and drain electrodes before depositing the silicon oxide layer, wherein the silicon oxide layer is an etch stop layer.

14. The method according to claim 12, wherein forming the low temperature polycrystalline silicon thin film transistor further includes forming low temperature polycrystalline silicon source and drain electrodes after depositing the silicon oxide layer, and forming the metal oxide thin film transistor further includes forming metal oxide source and drain electrodes after depositing the silicon oxide layer, wherein the silicon oxide layer is a passivation layer.

15. The method according to claim 11, wherein the silicon oxide layer has a thickness of 500 angstroms to 2000 angstroms.

16. The method according to claim 11, wherein the metal oxide channel layer is preprocessed with inductively coupled plasma containing nitrogen and oxygen, and the preprocessing of the metal oxide channel layer and the deposition of the silicon oxide layer include a processing time of 80 seconds to 350 seconds.

17. The method according to claim 16, wherein depositing the silicon oxide layer includes: at a SiH4 gas flow rate of 0.02 sccm / cm 2 to 0.09 sccm / cm 2 and introducing SiH4 gas at a processing temperature of 70°C to 350°C to form the silicon oxide layer.

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