Method for preparing a semiconductor structure

Abstract

The embodiments of the present application relate to a method for preparing a semiconductor structure and a semiconductor structure. The method comprises: forming a first patterned layer on a hard mask layer, the first patterned layer comprising a first mandrel and a second mandrel, the first patterned layer being formed based on the layout of an integrated circuit, the layout of the integrated circuit being decomposed into a mandrel region and a non-mandrel region, the mandrel region being used to reflect the characteristic dimensions of the layout, the first mandrel being filled in the mandrel region at intervals, and the second mandrel being arranged in the non-mandrel region; forming sidewall deposits on the sidewalls of the first mandrel and the sidewalls of the second mandrel, the sidewall deposits forming a second patterned layer on the hard mask layer; etching the first mandrel and the second mandrel; patterning the hard mask layer based on the second patterned layer to form a first trench on the patterned region inside the hard mask layer; etching the second patterned layer to form a filling metal layer in the first trench. The present application can effectively improve the alignment accuracy of the machine to the semiconductor structure.

Description

Technical Field

[0001] The present application relates to semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the manufacturing process of semiconductor integrated circuits, as the technology nodes of semiconductor manufacturing continue to advance, the critical dimensions continue to shrink, which has exceeded the physical limits of the current mainstream lithography technology. Therefore, self-aligned double patterning technology (SADP) came into being and has been widely used.

[0003] Self-aligned double patterning (SADP) involves using non-photolithography steps (thin film deposition, etching, etc.) to spatially double the photolithographic pattern after a single photolithography step. Finally, another photolithography and etching step is used to remove the redundant pattern. Summary of the Invention

[0004] In response to the above problems, the present application provides a method for manufacturing a semiconductor structure and a semiconductor structure, which can effectively improve the alignment accuracy of a machine to the semiconductor structure.

[0005] In a first aspect, the present application provides a method for preparing a semiconductor structure, the semiconductor structure comprising a substrate, a hard mask layer, a first patterned layer, a second patterned layer, and a fill metal layer, wherein the hard mask layer is deposited on the substrate;

[0006] The preparation method comprises:

[0007] forming the first patterned layer on the hard mask layer, the first patterned layer including a first mandrel and a second mandrel, the first patterned layer being formed based on a layout of an integrated circuit, the layout of the integrated circuit being decomposed into a mandrel region and a non-mandrel region, the mandrel region being used to reflect a feature size of an image, the first mandrels being spaced and filled in the mandrel region, and the second mandrels being arranged in the non-mandrel region;

[0008] forming a sidewall deposit on a sidewall of the first mandrel and a sidewall of the second mandrel, wherein the sidewall deposit forms a second patterned layer on the hard mask layer;

[0009] etching the first mandrel and the second mandrel;

[0010] patterning the hard mask layer based on the second patterned layer to form a first trench on the patterned area within the hard mask layer;

[0011] The second patterned layer is etched to form a filling metal layer in the first trench.

[0012] Furthermore, the core shaft area and the non-core shaft area are spaced apart, and the second core shaft is spaced apart in the non-core shaft area adjacent to the core shaft area.

[0013] Furthermore, an area of ​​the second mandrel projected on the hard mask layer is larger than an area of ​​the first mandrel projected on the hard mask layer.

[0014] Furthermore, both the first core axis and the second core axis are amorphous semiconductor strip structures.

[0015] Furthermore, the semiconductor structure further includes a dielectric layer, wherein the dielectric layer covers a side surface of the first mandrel and a side surface of the second mandrel, a first surface of the first mandrel and the second mandrel facing away from the hard mask layer, and a second surface of the hard mask layer outside the first mandrel and the second mandrel structure;

[0016] The forming of sidewall deposits on the sidewalls of the first mandrel and the second mandrel comprises:

[0017] Performing anisotropic etching on the dielectric layer to form sidewall deposits on the sidewalls of the first mandrel and the second mandrel;

[0018] The hard mask layer is exposed between the sidewall deposits.

[0019] Furthermore, the dielectric layer has the same coverage thickness on the side surface of the first core shaft, the side surface of the second core shaft, the first surface, and the second surface.

[0020] Furthermore, the semiconductor structure further includes a sacrificial material layer and a photoresist layer, wherein the sacrificial material layer is deposited on the hard mask layer, and the photoresist layer is coated on the sacrificial material layer;

[0021] The step of forming a first patterned layer on the hard mask layer comprises:

[0022] performing exposure and development processes on the photoresist layer to form a third patterned layer;

[0023] patterning the sacrificial material layer based on the third patterned layer to form a fourth patterned layer;

[0024] The third patterned layer is etched to determine the fourth patterned layer as the first patterned layer formed on the hard mask layer.

[0025] Furthermore, the substrate is a semiconductor material.

[0026] Furthermore, forming a filling metal layer in the first trench includes:

[0027] A Damascene process is used to fill the first trench with metal to form a filling metal layer.

[0028] In a second aspect, the present application provides a semiconductor structure, which is prepared using the above-mentioned method for preparing a semiconductor structure.

[0029] The preparation method of the semiconductor structure provided in the embodiment of the present application is, on a substrate formed with a hard mask layer, by forming a first core shaft and a second core shaft on the hard mask layer, filling the first core shaft interval in the core shaft area for reflecting the layout feature size, and setting the second core shaft in the non-core shaft area, and then forming sidewall deposits on the sidewalls of the first core shaft and the sidewalls of the second core shaft, the sidewall deposits form a second patterned layer, and then etching the first core shaft and the second core shaft, and patterning the hard mask layer based on the second patterned layer, forming a first groove on the patterned area inside the hard mask layer, and finally etching the second patterned layer, filling the first groove with a metal layer. The present application sets a second mandrel on the non-mandrel area and performs sidewall deposition on the first mandrel in the mandrel area. This reduces the patterned area of ​​the hard mask layer without affecting the patterned layout, thereby reducing the area of ​​the metal layer filled inside the hard mask layer. When the machine aligns the semiconductor structure, the reduction in the area of ​​the filled metal layer can reduce the reflective effect of the metal layer, thereby improving the alignment accuracy of the machine and reducing alignment errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure according to an embodiment of the present application;

[0032] Figures 2a to 2e A schematic structural diagram of a semiconductor structure during a preparation process according to an embodiment of the present application;

[0033] Figure 3a to Figure 3b A schematic diagram of a structure for forming sidewall deposits on the sidewalls of a first mandrel and a second mandrel according to an embodiment of the present application;

[0034] Figure 4 A flow chart of forming a first patterned layer on a hard mask layer according to an embodiment of the present application;

[0035] Figures 5a to 5d Schematic diagram of the structure of forming a first patterned layer on a hard mask layer according to an embodiment of the present application.

[0036] Figure 6 This is a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0038] As semiconductor manufacturing technology continues to advance, the critical dimensions of circuit patterns continue to shrink, exceeding the physical limits of mainstream photolithography. Consequently, self-aligned double patterning (SAD) technology has emerged and is gaining widespread application. SAD utilizes spatial multiplication to form sidewalls around the primary pattern. These sidewalls serve as a mask for etching the semiconductor structure, resulting in a circuit pattern with even smaller critical dimensions.

[0039] In the manufacturing process of integrated circuits, it is necessary to repeatedly pattern different circuit patterns onto a hard mask layer, fill the patterned circuit patterns with a metal layer, and then connect different hard mask layers through circuit elements to achieve electrical connection between the different hard mask layers, thereby manufacturing a semiconductor structure with an integrated circuit.

[0040] After the hard mask layer is filled with metal, the machine uses the patterned circuit pattern within the metal layer as an alignment reference. Subsequent correction processes are performed on this alignment reference to complete circuit fabrication. Because the metal layer within the hard mask layer is relatively large, the metal layer will produce significant light reflections during machine alignment, making it difficult for the machine to accurately identify the position of the pattern on the hard mask layer, resulting in significant alignment errors.

[0041] Please refer to Figure 1 , provides a schematic flow chart of a method for preparing a semiconductor structure according to an embodiment of the present application. Figure 1 As shown, the preparation method of the embodiment of the present application may include the following steps S101-S104.

[0042] S101, forming a first patterned layer on the hard mask layer, the first patterned layer including a first core axis and a second core axis, the first patterned layer is formed based on the layout of the integrated circuit, the layout of the integrated circuit is decomposed into a core axis area and a non-core axis area, the core axis area is used to reflect the characteristic size of the layout, the first core axis is filled in the core axis area, and the second core axis is set in the non-core axis area.

[0043] Please refer to Figures 2a to 2e The semiconductor structure includes a substrate 10, a hard mask layer 20, a first patterned layer 30, a second patterned layer 40, and a fill metal layer 50. The present embodiment provides a semiconductor structure to be processed, so that subsequent fabrication methods are performed based on the semiconductor structure to be processed. The semiconductor structure to be processed includes a substrate 10 and a hard mask layer 20, and the hard mask layer 20 is deposited on the substrate 10.

[0044] The substrate 10 can be a semiconductor material. Further, the substrate 10 can be a Si substrate, a Ge substrate or a SiGe substrate, etc. In other embodiments, it can also be other element semiconductor substrates or compound semiconductor substrates, such as a GaAs substrate, a SiC substrate, an InP substrate, etc. The substrate 10 material selected in the embodiment of the present application is a Si substrate, and a hard mask layer 20 is deposited on the substrate 10.

[0045] Specifically, the hard mask layer 20 can be deposited onto the surface of the substrate 10 via a physical vapor deposition (PVD) process. The PVD process not only allows the hard mask layer 20 to be uniformly and densely deposited on the surface of the substrate 10, but also improves the tightness of the bonding between the hard mask layer 20 and the substrate 10. Preferably, the hard mask layer 20 in the embodiment of the present application can be formed by depositing titanium nitride via physical vapor deposition. The titanium nitride metal hard mask has good etching selectivity and can accurately control the formation of critical dimensions during the process. Moreover, when the titanium nitride metal hard mask is removed from the substrate 10, the integrity of the substrate 10 is not damaged by the removal of the titanium nitride metal hard mask.

[0046] like Figure 2a As shown, the first patterned layer 30 is formed based on the layout of the integrated circuit, and the first patterned layer 30 includes a first mandrel 31 and a second mandrel 32 .

[0047] In an embodiment of the present application, the layout of the integrated circuit is a hierarchical stack of multiple circuit sub-layouts. The layout of the integrated circuit is based on a semiconductor substrate 10, a hard mask layer 20 is stacked on the semiconductor substrate 10, and a circuit sub-layout is patterned inside each layer of the hard mask. The electrical connection of the circuit sub-layouts inside the hard mask between different levels is achieved through circuit elements, thereby forming an integrated circuit.

[0048] The layout of an integrated circuit is decomposed into mandrel regions 33 and non-mandrel regions 34. Mandrel regions 33 are used to reflect the layout's characteristic dimensions, which in turn reflect the pattern of the circuit sub-layout. Taking a certain layer of a mask as an example, first mandrels 31 are intermittently filled in mandrel regions 33. The placement of these first mandrels 31 can achieve spatial multiplication of mandrel regions 33 through subsequent non-photolithography process steps. After spatial multiplication, mandrel regions 33 form the pattern of the circuit sub-layout. Second mandrels 32 are placed in non-mandrel regions 34. The placement of these second mandrels 32 in these non-mandrel regions 34 can reduce the area of ​​the fill metal layer 50 on the surface of the hard mask layer 20 without affecting the patterned circuit sub-layout, thereby reducing the reflective effect of the metal layer during machine alignment. Furthermore, the locations of the second mandrels 32 are filled with the fill metal layer 50 in subsequent process steps. Since these second mandrels 32 do not reflect the characteristic dimensions of the circuit sub-layout, their placement serves as a new alignment reference for the machine when identifying the circuit sub-layout, reducing alignment errors during machine alignment.

[0049] Specifically, the embodiments of the present application do not limit the formation method of the first mandrels 31 and the second mandrels 32. The first mandrels 31 and the second mandrels 32 can both be deposited on the hard mask layer 20 through a chemical vapor deposition process, or can both be deposited on the hard mask layer 20 through a series of processes such as photolithography, stacking, and etching. It should be noted that all first mandrels 31 filled in the mandrel area 33 are arranged parallel to each other, the outline of the first mandrel 31 should be aligned with the edge of the mandrel area 33, and the distance between two adjacent first mandrels 31 is equal; the distance between two adjacent second mandrels 32 arranged in the non-mandrel area 34 is equal. Preferably, the second mandrels 32 are arranged parallel to the first mandrels 31.

[0050] Furthermore, the position and arrangement of the first mandrel 31 and the second mandrel 32 can be automatically generated by a computer program, or can be designed by a person skilled in the art, or can be obtained by modifying the design based on the design automatically generated by the computer program. Preferably, the first mandrel 31 and the second mandrel 32 use the same CVD (Chemical Vapor Deposition) material, such as SiO2 or Si3N4, etc., but this embodiment of the present application is not restricted to this. In other embodiments, the first mandrel 31 and the second mandrel 32 can also use different materials.

[0051] S102 , forming sidewall deposits on the sidewalls of the first mandrel and the sidewalls of the second mandrel, wherein the sidewall deposits form a second patterned layer on the hard mask layer.

[0052] like Figure 2bAs shown, the present embodiment does not limit the formation method of the sidewall deposits 41. The sidewall deposits 41 can be formed using a technique such as sidewall image transfer. It is understood that the sidewall deposits 41 are not only deposited on the sidewall surfaces of the first mandrel 31 and the second mandrel 32, but also deposited on the surface of the hard mask layer 20 to mask the hard mask layer 20, thereby achieving spatial multiplication of the area masked by the first mandrel 31 and the second mandrel 32. The first core shafts 31 are filled in the core shaft area 33 at intervals. Since the core shaft area 33 can obtain a complete circuit sub-layout after spatial multiplication, the area masked by the sidewall deposits 41 formed on the side wall surfaces of all first core shafts 31 can constitute a complete circuit sub-layout; since the second core shafts 32 are filled in the non-core shaft area 34, the area masked by the sidewall deposits 41 formed on the side wall surface of the second core shaft 32 will not affect the formation of the circuit sub-layout, and the sidewall deposits 41 formed on the side wall of the second core shaft 32 enable the area masked by the second core shaft 32 to be spatially multiplied, thereby reducing the filling area of ​​the metal layer.

[0053] In this step, sidewall deposits 41 are formed on the sidewalls of the first mandrel 31 to multiply the space of the mandrel region 33 and form a complete circuit sub-layout. Sidewall deposits 41 are also formed on the sidewalls of the second mandrel 32 to reduce the metal fill area. Sidewall deposits 41 form a second patterned layer 40 on the hard mask layer, allowing the second patterned layer 40 to not only mask the complete circuit sub-layout on the hard mask layer 20 but also reduce the metal fill area within the hard mask layer 20.

[0054] S103, etching the first mandrel and the second mandrel.

[0055] like Figure 2c As shown, in the embodiment of the present application, the first mandrel 31 and the second mandrel 32 are etched. It is understood that after etching the first mandrel 31 and the second mandrel 32, only the second patterned layer 40 is present on the hard mask layer 20. The second patterned layer 40 not only reflects the complete circuit sub-layout, but also reduces the metal filling area, simplifying subsequent process steps.

[0056] Specifically, in order to ensure the completeness of etching of the first mandrel 31 and the second mandrel 32 and to protect the integrity of the hard mask layer 20, the material of the first mandrel 31 and the material of the second mandrel 32 can be selected from materials with a relatively large selective etching ratio with the material of the hard mask layer 20. Etching selectivity refers to the relative etching rate of one material and another material under the same etching conditions. Therefore, by selecting an appropriate etching process, the first mandrel 31 and the second mandrel 32 can be selectively removed relative to the sidewall deposits 41. Preferably, in the embodiment of the present application, the material of the first mandrel 31 is the same as the material of the second mandrel 32. In other embodiments, the material of the first mandrel 31 and the material of the second mandrel 32 may also be different. In order to ensure the completeness of etching of the first mandrel 31 and the second mandrel 32 and to protect the integrity of the hard mask layer 20, the material of the first mandrel 31 and the material of the second mandrel 32 both have a relatively large selective etching ratio with the material of the hard mask layer 20.

[0057] S104 , patterning the hard mask layer based on the second patterned layer to form a first trench on the patterned region inside the hard mask layer.

[0058] like Figure 2d As shown, after removing the first mandrel 31 and the second mandrel 32, the hard mask layer 20 is patterned by an etching process with the second patterned layer 40 serving as an etching mask, thereby forming a first trench 42 within the hard mask layer 20. Preferably, to ensure complete etching of the hard mask layer 20 and protect the integrity of the second patterned layer 40, a large selective etching ratio is provided between the material of the hard mask layer 20 and the material of the second patterned layer 40.

[0059] S105 , etching the second patterned layer to form a filling metal layer in the first trench.

[0060] like Figure 2e As shown, the filling metal layer 50 makes the circuit sub-layout patterned inside the hard mask layer 20 conductive, so that the circuit sub-layout achieves the expected working effect.

[0061] In an embodiment of the present application, by setting a second mandrel in the non-mandrel area and performing sidewall deposition on the first mandrel in the mandrel area, the area of ​​the filling metal layer exposed to the surface of the hard mask layer is reduced without affecting the pattern layout during subsequent non-photolithography processes. When the machine performs alignment operations on the hard mask layer, the reduction in the area of ​​the filling metal layer can reduce the reflective effect of the filling metal layer, thereby improving the alignment accuracy of the machine and reducing alignment errors.

[0062] Specifically, in one embodiment, the area of ​​the second mandrel 32 projected onto the hard mask layer 20 is larger than the area of ​​the first mandrel 31 projected onto the hard mask layer 20. In the embodiment of the present application, by providing the second mandrel 32 with a larger projected area when projected onto the hard mask layer 20, the second mandrel 32 can increase the size of the second patterned layer 40 masked on the hard mask layer during spatial multiplication. This further reduces the area of ​​the fill metal layer 50 exposed within the hard mask layer 20 during the subsequent etching process, minimizing the reflective effect of the fill metal layer 50 when the tool is aligned with the hard mask layer 20, thereby achieving better alignment of the tool with the hard mask layer 20. The embodiment of the present application does not impose any restrictions on the projected areas of the first mandrel 31 and the second mandrel 32 projected onto the hard mask layer 20. However, it should be noted that the pattern of the first mandrel 31 projected onto the hard mask layer 20 must not exceed the outline of the mandrel region 33, and the pattern of the second mandrel 32 projected onto the hard mask layer 20 must not exceed the outline of the non-mandrel region 34.

[0063] The embodiment of the present application limits the area of ​​the second core axis projected on the hard mask layer to be larger than the area of ​​the first core axis projected on the hard mask layer. In the subsequent process, the area of ​​the exposed metal layer on the surface of the hard mask layer can be further reduced, so that the machine has a better alignment effect when aligning the hard mask layer.

[0064] Furthermore, in another specific embodiment, both the first mandrel 31 and the second mandrel 32 are amorphous semiconductor strip structures. Amorphous semiconductor materials are simple to prepare, low-cost, and easily formed into thin films for large-area coverage. The strip structure allows the first mandrel 31 to be more tightly packed within the mandrel region 33 and makes it easier to position the second mandrel 32 parallel to the first mandrel 31.

[0065] The embodiment of the present application limits the structure and material of the first mandrel and the second mandrel, so that the arrangement of the first mandrel and the second mandrel is denser, and it is easier to cover the mandrel area and the non-mandrel area.

[0066] The embodiment of the present application provides a feasible embodiment for the step of forming sidewall deposits on the sidewalls of the first mandrel and the sidewalls of the second mandrel. The step of forming sidewall deposits on the sidewalls of the first mandrel and the sidewalls of the second mandrel further includes the following steps:

[0067] The dielectric layer is anisotropically etched to form sidewall deposits on the sidewalls of the first mandrel and the second mandrel.

[0068] Please refer to Figure 3aThe semiconductor structure also includes a dielectric layer 60, which covers the side surface 61 of the first core shaft and the side surface 62 of the second core shaft, the first surface 63 of the first core shaft 31 and the second core shaft 32 facing away from the hard mask layer, and the second surface 64 on the hard mask layer outside the first core shaft 31 and the second core shaft 32 structure.

[0069] like Figure 3b As shown, the dielectric layer 60 covered by the side surface 61 of the first mandrel and the side surface 62 of the second mandrel, the first surface 63 and the second surface 64 is anisotropically etched to form the sidewall deposits 41 on the sidewalls of the first mandrel 31 and the second mandrel 32 .

[0070] It is understood that, in order to multiply the pattern of the mandrel region 33, the dielectric layer 60 covering the sidewalls of the first mandrel 31 and the second mandrel 32 should be retained; in order to enable the subsequent steps to etch the first mandrel 31 and the second mandrel 32, the dielectric layer 60 covering the first surface 63 should be etched; in order to enable the subsequent steps to etch the hard mask layer 20, the dielectric layer 60 covering the second surface 64 should be etched. Figure 3b As shown, it is not difficult to find that the etching directions of the dielectric layer 60 to be etched are different from those of the dielectric layer 60 to be retained. Specifically, in a spatial rectangular coordinate system, with coordinates (1, 1) and (0, 0) as references, if the etching direction of the dielectric layer 60 to be etched is from (0, 1) to (0, 0), then the etching direction of the dielectric layer 60 to be retained is from (1, 0) to (0, 0). In other words, when the etching solution is deposited on the dielectric layer 60, the etching solution longitudinally etches the dielectric layer 60 to be etched, while the etching solution laterally etches the dielectric layer 60 to be retained. This step leverages this phenomenon and applies the principle that the etching rate of the dielectric layer 60 to be etched varies along different etching directions. A wet etching process is selected to retain the dielectric layer 60 on the sidewalls of the first mandrel 31 and the sidewalls of the second mandrel 32 through anisotropic etching. After etching, the dielectric layer 60 located on the sidewalls of the first mandrel 31 and the sidewalls of the second mandrel 32 is also the sidewall deposit 41 .

[0071] In this embodiment, the dielectric layer is anisotropically etched to form sidewall deposits on the sidewalls of the first and second mandrels. This anisotropic etching process not only etches away the dielectric layer on the first and second surfaces but also multiplies the pattern in the mandrel region, facilitating subsequent process steps for patterning the circuit sub-layout.

[0072] Preferably, in some embodiments, the dielectric layer 60 has the same coverage thickness on the side surface 61 of the first mandrel, the side surface 62 of the second mandrel, the first surface 63, and the second surface 64. This same coverage thickness ensures that, during an anisotropic etching process, the projected areas of the sidewall deposits 41 formed on the side surface 61 of the first mandrel and the side surface 62 of the second mandrel on the hard mask layer 20 are relatively small, resulting in a more precise pattern of the resulting circuit sub-layout. In other embodiments, the dielectric layer 60 can be deposited uniformly on the hard mask layer 20 or deposited in a specific shape on the hard mask layer 20, thereby resulting in a specifically shaped sidewall deposit 41 of the dielectric layer 60 after anisotropic etching.

[0073] In the embodiment of the present application, the second patterned layer 40 composed of sidewall deposits 41 with different masking areas can be obtained by changing the type of etching solution and controlling the etching time.

[0074] In the embodiment of the present application, by ensuring that the dielectric layer has the same coverage thickness on the side of the first core axis, the side of the second core axis, the first surface, and the second surface, sidewall deposits with smaller structural differences are obtained in the subsequent anisotropic etching process, so that the pattern of the hard mask layer covered by the sidewall deposits can more accurately reflect the circuit sub-layout.

[0075] The present application provides a feasible embodiment for the step of forming a first patterned layer on the hard mask layer. Please refer to Figure 4 , forming a first patterned layer on the hard mask layer includes the following steps:

[0076] S201 , performing exposure and development processes on the photoresist layer to form a third patterned layer.

[0077] Please refer to Figure 5a The semiconductor structure further includes a sacrificial material layer 70 and a photoresist layer 80 . The sacrificial material layer 70 is deposited on the hard mask layer 20 , and the photoresist layer 80 is coated on the sacrificial material layer 70 .

[0078] like Figure 5b As shown, the mask is designed with a pattern of the first core axis 31 and the second core axis 32. The light source is irradiated to the photoresist layer 80 through the mask, so that a chemical effect occurs in the photoresist layer 80 in the exposed area; after the exposure process is completed, a developer is added, and the area where the chemical effect occurs can be dissolved in a specific developer. The undissolved photoresist layer 80 remains on the sacrificial material layer 70, thereby forming a third patterned layer 90.

[0079] Furthermore, photoresists can be categorized as positive and negative photoresists based on their properties, corresponding to the two basic photolithography processes of positive and negative photolithography, respectively. In positive photolithography, the exposed areas of the positive photoresist are destroyed and dissolved by the developer, resulting in the pattern on the photoresist being identical to the pattern on the mask. In negative photolithography, the exposed areas of the negative photoresist harden, rendering them insoluble, while the unexposed areas are dissolved by the developer, resulting in the pattern on the photoresist being the opposite of the pattern on the mask. In this step, regardless of whether positive or negative photolithography is used, the third patterned layer 90 formed after photolithography should meet the desired results achieved in subsequent steps.

[0080] S202 , patterning the sacrificial material layer based on the third patterned layer to form a fourth patterned layer.

[0081] like Figure 5c As shown, when the sacrificial material layer 70 is patterned, the third patterned layer 90 serves as a mask for the sacrificial material layer 70, so that the area of ​​the sacrificial material layer 70 exposed outside the third patterned layer 90 is etched, thereby forming a fourth patterned layer 100 in which the sacrificial material layer 70 and the third patterned layer 90 are superimposed.

[0082] S203 , etching the third patterned layer to determine the fourth patterned layer as the first patterned layer formed on the hard mask layer.

[0083] like Figure 5d As shown, after etching the third patterned layer 90 , the pattern of the fourth patterned layer 100 is the pattern of the first patterned layer 30 formed on the hard mask layer. Thus, the feasible steps of forming the first patterned layer 30 on the hard mask layer 20 are completed.

[0084] Furthermore, in order to prevent the sacrificial material layer 70 from being affected by the etching process, the material of the third patterned layer 90 is different from that of the sacrificial material layer 70 .

[0085] In the embodiments of the present application, a first patterned layer with a stable structure and accurate position is formed by exposing and developing the photoresist layer and etching the sacrificial material layer. It is understood that the method for preparing a semiconductor structure is to perform subsequent process steps based on the first patterned layer. The first patterned layer with a stable structure and accurate position can provide a good foundation for the subsequent process flow.

[0086] Preferably, in other embodiments, a damascene process is used to fill the first trench 42 with metal to form a filling metal layer 50 .

[0087] The metal filling layer 50 can be filled with aluminum or copper, and the two can be selectively filled based on the working properties of the device. Since aluminum and silicon easily melt together when heated, forming a short circuit, and the aluminum wires inside the integrated circuit are relatively slender and often bear high-density currents, the aluminum wires are prone to diffusion under the combined effects of the electric field and heat, affecting the conductivity of the aluminum filling layer. The aluminum filling layer formed by the Damascus process can reduce the diffusion of the aluminum layer. Since the contact resistance between copper and silicon is high and copper easily diffuses into silicon, causing device performance problems, the copper filling layer formed by the Damascus process can prevent copper from diffusing into silicon, thereby making the filling metal layer 50 have a better conductive effect.

[0088] In the embodiment of the present application, the filling metal layer formed by the Damascus process has the advantages of strong conductivity and stable structure.

[0089] The present application also provides a semiconductor structure, which is obtained by the preparation method described in the above steps. Figure 6 As shown, the semiconductor structure of the embodiment of the present application includes a substrate 10, a hard mask layer 20 and a filling metal layer 50. The hard mask layer 20 is deposited on the substrate 10, and a first trench 42 is etched inside the hard mask layer 20, and the first trench 42 is filled with the filling metal layer 50.

[0090] It can be understood that in the semiconductor structure obtained by the preparation method described above, the first trench 42 in the hard mask layer 20 not only reflects the circuit sub-layout, but also reduces the area of ​​the fill metal layer 50 exposed on the surface of the hard mask layer 20. When the machine aligns the semiconductor structure, on the one hand, reducing the metal area exposed on the surface of the hard mask layer 20 can reduce the reflective effect of the fill metal layer 50, thereby improving the machine's recognition accuracy of the circuit sub-layout and making it easier for the machine to align the circuit sub-layout. On the other hand, because the location of the second mandrel 32 is ultimately filled with the fill metal layer 50 in the above process steps, and the second mandrel 32 does not reflect the characteristic dimensions of the circuit sub-layout, the portion of the fill metal layer 50 that fills the location of the second mandrel 32 provides a new alignment reference for the machine when identifying the circuit sub-layout, thereby reducing alignment errors generated by the machine during alignment.

[0091] In the embodiment of the present application, the semiconductor structure obtained by the above-mentioned preparation method not only patterns the circuit sub-layout onto the semiconductor structure, but also reduces the exposed area of ​​the metal layer on the surface of the semiconductor structure. This allows the machine to improve the alignment accuracy and reduce the alignment error when performing alignment operations on the circuit sub-layout on the semiconductor structure, so that the semiconductor structure of the embodiment of the present application can also serve as an excellent alignment structure.

[0092] The same or similar numbers in the drawings of the embodiments of this application correspond to the same or similar items; in the description of this application, it should be understood that if the terms "upper", "lower", "left", "right", etc. indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the drawings. This is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0093] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure includes a substrate, a hard mask layer, a first patterned layer, a second patterned layer, and a filling metal layer, wherein the hard mask layer is deposited on the substrate; The preparation method comprises: forming a first patterned layer on the hard mask layer, the first patterned layer including a first mandrel and a second mandrel, the first patterned layer being formed based on a layout of an integrated circuit, the layout of the integrated circuit being decomposed into a mandrel region and a non-mandrel region, the mandrel region being used to reflect a feature size of the layout, the first mandrels being alternately filled in the mandrel region, and the second mandrels being arranged in the non-mandrel region; forming sidewall deposits on sidewalls of the first mandrel and sidewalls of the second mandrel, wherein the sidewall deposits form a second patterned layer on the hard mask layer; etching the first mandrel and the second mandrel; patterning the hard mask layer based on the second patterned layer to form a first trench on the patterned area inside the hard mask layer; etching the second patterned layer to form a filling metal layer in the first trench; The core shaft region is provided with a plurality of first core shafts spaced apart along a first direction, and the non-core shaft region is provided with a plurality of second core shafts spaced apart along the first direction; The core axis area and the non-core axis area are arranged along a second direction, and the first direction intersects with the second direction.

2. The preparation method according to claim 1, wherein The core shaft area and the non-core shaft area are spaced apart, and the second core shaft is spaced apart in the non-core shaft area adjacent to the core shaft area.

3. The preparation method according to claim 2, wherein An area of ​​the second mandrel projected on the hard mask layer is larger than an area of ​​the first mandrel projected on the hard mask layer.

4. The preparation method according to claim 2, wherein The first core axis and the second core axis are both amorphous semiconductor strip structures.

5. The preparation method according to claim 1, wherein The semiconductor structure further includes a dielectric layer, the dielectric layer covering a side surface of the first mandrel and a side surface of the second mandrel, a first surface of the first mandrel and the second mandrel facing away from the hard mask layer, and a second surface of the hard mask layer outside the first mandrel and the second mandrel structure; The forming of sidewall deposits on the sidewalls of the first mandrel and the second mandrel comprises: Performing anisotropic etching on the dielectric layer to form sidewall deposits on the sidewalls of the first mandrel and the second mandrel; The hard mask layer is exposed between the sidewall deposits.

6. The preparation method according to claim 5, wherein The dielectric layer has the same coverage thickness on the side surface of the first core shaft, the side surface of the second core shaft, the first surface, and the second surface.

7. The preparation method according to claim 1, wherein The semiconductor structure further includes a sacrificial material layer and a photoresist layer, wherein the sacrificial material layer is deposited on the hard mask layer, and the photoresist layer is coated on the sacrificial material layer; The step of forming a first patterned layer on the hard mask layer comprises: performing exposure and development processes on the photoresist layer to form a third patterned layer; patterning the sacrificial material layer based on the third patterned layer to form a fourth patterned layer; The third patterned layer is etched to define the fourth patterned layer as the first patterned layer formed on the hard mask layer.

8. The preparation method according to claim 1, wherein The substrate is a semiconductor material.

9. The preparation method according to claim 1, wherein The forming of a filling metal layer in the first trench includes: A Damascene process is used to fill the first trench with metal to form a filling metal layer.

10. A semiconductor structure, characterized in that The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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