Array and Contact Architecture for Four Stacked Layer 3D Cross-Point Memory

Abstract

The architecture for three-dimensional cross-point memory cells includes layers of multiple planar and parallel bit slice regions, each of the bit slice regions including bit lines extending in a bit line direction. The architecture also includes a decoder to which the bit slice regions are electrically connected through contacts. Each bit slice region layer has a slice ratio per decoder, which is defined as the ratio of the number of bit slice regions in the layer to the number of many decoders to which at least one of the slice regions in the layer is electrically connected. At least one of the bit slice region layers has a different slice ratio per decoder greater than 1:1.

Description

[0001] This application is a divisional application, and its original application is the international patent application PCT / CN2020 / 121071 that entered the Chinese national stage on November 18, 2020, with an international filing date of October 15, 2020. The Chinese national application number of this original application is 202080002803.4, and the invention title is "Array and Contact Architecture for Four Stacked Layer Three-Dimensional Cross-Point Memory". Technical Field

[0002] The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in three-dimensional cross-point memories. Background Art

[0003] By improving process technology, circuit design, programming algorithms, and manufacturing processes, planar memory cells are scaled down to smaller sizes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit. Three-dimensional (3D) storage architectures can address the density limitations in planar memory cells by stacking multiple planes of memory cells in a single device. Summary of the Invention

[0004] According to one aspect, an architecture for three-dimensional cross-point memory cells includes multiple, mutually parallel bit tile layers, each bit tile including bit lines extending in the bit line direction. The architecture further includes a decoder to which the bit tiles are electrically connected via contacts. Each bit tile layer has a tile per decoder ratio, which is defined as the ratio of the number of bit tiles in the layer to the number of many decoders to which at least one tile in the layer is electrically connected. At least one bit tile layer has a different tile per decoder ratio greater than 1:1.

[0005] In some arrangements, at least one bit tile layer has a tile per decoder ratio different from that of another bit tile layer.

[0006] In some arrangements, at least one bit tile layer has a tile per decoder ratio of 2:1.

[0007] In some arrangements, at least one bit tile layer having a tile per decoder ratio of 2:1 includes a bit tile that is electrically connected to the same decoder as another bit tile in the same layer.

[0008] In some arrangements, at least one bit tile layer has a tile per decoder ratio of 4:1.

[0009] In some arrangements, at least one bit slice layer having a slice ratio per decoder of 4:1 includes bit slices that are electrically connected to the same decoder as three other bit slices in the same layer.

[0010] In some arrangements, multiple bit slice layers include: a first layer; an intermediate layer that is closer to the decoder than the first layer and has a slice ratio per decoder greater than that of the first layer; and an outer layer that is closer to the decoder than the intermediate layer and has a slice ratio per decoder greater than that of the intermediate layer.

[0011] In some arrangements, the multiple bit slice layers further include a second layer that is farther from the decoder than the intermediate layer and the outer layer and has the same slice ratio per decoder as the first layer.

[0012] In some arrangements, the bit slices in the intermediate layer are shorter than the slices in the first layer in the bit line direction, and the bit slices in the outer layer are shorter than the slices in the intermediate layer in the bit line direction.

[0013] According to another aspect, an array and contact architecture for three-dimensional cross-point memory cells includes multiple planar and parallel bit slice layers, each bit slice including bit lines extending in the bit line direction. The bit slices in at least one bit slice layer are shorter than the bit slices in another bit slice layer in the bit line direction.

[0014] In some arrangements, the architecture includes a decoder, and the multiple bit slices include: a first layer; an intermediate layer that is closer to the decoder and includes bit slices that are shorter than the bit slices in the first layer in the bit line direction; and an outer layer that is closer to the decoder than the intermediate layer and includes bit slices that are shorter than the bit slices in the intermediate layer in the bit line direction.

[0015] In some arrangements, each bit slice layer has a slice ratio per decoder, which is defined as the ratio of the bit slices in the layer to the number of decoders to which at least one slice in the layer is electrically connected, and the intermediate layer has a slice ratio per decoder greater than that of the first layer.

[0016] In some arrangements, the outer layer has a slice ratio per decoder greater than that of the intermediate layer.

[0017] In some arrangements, the multiple bit slice layers further include a second layer that is farther from the decoder than the intermediate layer and the outer layer and has bit slices having the same length as the bit slices in the first layer in the bit line direction.

[0018] In some arrangements, each bit-slice layer has a per-decoder slice ratio, which is defined as the ratio of the bit-slices in the layer to the number of decoders to which at least one slice in the layer is electrically connected. The second layer has the same per-decoder slice ratio as the first layer, the middle layer has a per-decoder slice ratio greater than the first layer, and the outer layer has a per-decoder slice ratio greater than the middle layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The foregoing aspects, features, and advantages of the present disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals represent like elements. Specific terms may be used when describing the exemplary embodiments of the present disclosure shown in the drawings for clarity. However, aspects of the present disclosure are not intended to be limited to the specific terms used.

[0020] Figure 1 is an isometric view of a portion of an existing three-dimensional cross-point memory.

[0021] Figure 2 is Figure 1 a plan view of a portion of the existing three-dimensional cross-point memory shown in

[0022] Figure 3 is Figure 1 and Figure 2 a cross-sectional side view of a portion of the existing three-dimensional cross-point memory shown in

[0023] Figure 4 is a cross-sectional side view of a portion of a three-dimensional cross-point memory according to an embodiment. DETAILED DESCRIPTION

[0024] The present technology is applied to the field of three-dimensional cross-point memories. General examples of three-dimensional (3D) memories are shown in Figure 1 In particular, Figure 1 is an isometric view of a portion of a three-dimensional cross-point memory 10. This portion includes a first bit-slice 14 and a second bit-slice 18 extending below the first bit-slice 14. Both the first bit-slice 14 and the second bit-slice 18 are planar and parallel to each other, and both include a plurality of bit lines 22 extending therethrough. The lines 22 are also parallel to each other and extend in the bit-line direction.

[0025] Interleaved with bit regions 14, 18 are first word regions 26 extending between the first bit region 14 and the second bit region 18, and second word regions 30 extending below the second bit region 18. The interleaving shown is merely exemplary, and in other examples, the first word region 26 may extend above the first bit region 14 while the second word region 30 extends between the first bit region 14 and the second bit region 18. The word regions 26, 30 are also planar and parallel to the bit regions 14, 18. Each of the word regions 26, 30 includes a plurality of word lines 34 extending therethrough in a word direction Z perpendicular to the bit direction X.

[0026] The portion of the memory 10 shown includes three layers of memory cells 40. The memory cells 40 may be present between the bit regions 14, 18 and the word regions 26, 30, and from the perspective of the height direction Y, the memory cells 40 are where the bit lines 22 and the word lines 34 intersect. Thus, the storage density per unit area in the XY plane is a function of the many bit regions and word regions that can be alternately interleaved at a given location.

[0027] To selectively activate the word lines 34 and the bit lines 22, the memory includes a bit line decoder 42 and a word line decoder 46 at the bottom layer of the memory architecture. The bit line decoder 42 and the word line decoder 46 are coupled to the bit lines 22 and the word lines 34 respectively through contacts 38 and are used to decode the bit line and word line addresses such that a specific bit line 22 or word line 34 is activated upon addressing. The bit regions 14, 18 and the word regions 26, 30 are all shown in dashed lines to indicate that the contacts 38 are located at or near the midpoints of the bit regions 14, 18 in the bit direction X and at or near the midpoints of the word regions 34 in the word direction Z. It should also be understood that the number of bit lines 22 for each bit region 14, 18 and the number of word lines 34 for each word region 26, 30 shown are exemplary, and more or fewer lines may be used for each region. In connection with Figure 2 The arrangement of the decoders 42, 46 and the contacts 38 is further discussed.

[0028] Figure 2 A cross-section of the memory 10 is schematically shown from the perspective of the height direction Y, showing only the bit lines 22 and the word lines 34 corresponding to the first and second bit regions 14, 18 and the first word region 26. Since the contacts 38 extend vertically to the bottom layer of the memory architecture, the contacts 38 associated with each region define areas that the other regions represented by the dashed lines cannot pass through below. This is also shown in Figure 3 shown in Figure 3A cross-section of a first bit slice region 14 and a second bit slice region 18 in the X-Y plane is schematically shown. Thus, such contact regions impede the interleaving of the bit slices. When present in a repeating pattern, the contact regions limit the number of bit slice layers that can be achieved across the memory device. For example, in the case of using bit slice regions 14, 18 having substantially equal lengths in the in-bit direction X and a centered contact 38, only two bit slice layers can be used at a given location along the in-bit direction X in a given X-Y plane.

[0029] Figure 4 A cross-section of a memory according to an embodiment is schematically shown along the X-Y plane. As shown, the memory includes a third bit slice region 50 extending beneath the second bit slice region 18 and a fourth bit slice region 54 extending beneath the third bit slice region 50. The third bit slice region 50 is shorter than the first and second bit slice regions 14, 18 in the in-bit direction X such that the third bit slice region 50 can be fitted between the contacts 38 associated with the first and second bit slice regions 14, 18. Similarly, the fourth bit slice region 54 is shorter than the third bit slice region 50 in the in-bit direction X such that the fourth bit slice region 54 can be fitted between the contacts 38 associated with the first, second, and third bit slice regions 14, 18, 50. Thus, Figure 4 the architecture is capable of using up to four bit slice layers at a given location along the in-bit direction X in the shown X-Y plane. A greater number of bit slice layers can correspondingly increase the number of bit cell 40 layers, thereby increasing the possible storage density per unit area in the X-Z plane. Although the third bit slice region 50 and the fourth bit slice region 54 have different sizes, in the example shown, the contacts 38 are connected to the respective third bit slice region 50 and fourth bit slice region 54 along the X direction at the center of the bit slice.

[0030] The bridge 56 joins the contacts 38 associated with the third bit slices 50 and the fourth bit slices 54 at the bottom of the memory architecture such that multiple third bit slices 50 contact a single bit line decoder 42 and multiple fourth bit slices 54 contact a single bit line decoder 42. In the example shown, the bridge 56 joins the contacts 38 associated with two adjacent third bit slices 50 such that each third bit slice 50 shares the bit line decoder 42 with the other third bit slice 50. Similarly, the bridge 56 joins the contacts 38 associated with four adjacent fourth bit slices 54 such that each fourth bit slice 54 shares the decoder with the other three fourth bit slices 54. In this way, each slice layer has a slice-to-decoder ratio, which is defined as the ratio of the total number of bit slices in the layer to the total number of decoders electrically connected to the bit slices in the layer. Thus, in a layer with a 1:1 slice-to-decoder ratio and assuming no bit slice is electrically connected to more than one decoder, each bit slice is electrically connected to a different decoder. Similarly, in a layer with a 2:1 slice-to-decoder ratio and assuming no bit slice is electrically connected to more than one decoder and the size of the decoder-sharing groups of slices in the layer is uniform across the layer, the bit slices are electrically connected in pairs that share the same decoder and each pair of bit slices is electrically connected to a different decoder. Here, a decoder-sharing group refers to a group of bit slices all electrically connected to the same decoder.

[0031] A layer can be assigned a layer wide group size. In an example where the slice layout is uniform across the layer, the layer wide group size refers to the number of slices in each decoder-sharing group of slices in the layer. In an example where the decoder-sharing group size varies within the layer (e.g., due to differences at the architecture edges or manufacturing defects), the layer wide group size instead refers to the statistical mode number of bit slices in the layer that are electrically connected to any one decoder in the group of all decoders electrically connected to the bit slices in the layer. In other words, in a layer where the decoder-sharing group size is non-uniform, the layer wide group size refers to the statistical mode size of the decoder-sharing groups of bit slices in the layer, where each decoder-sharing group of bit slices is one or more bit slices that share a decoder.

[0032] In the example shown, the layer including the third bit slice 50 has a per-decoder slice ratio greater than that of the layer including the first bit slice 14 and the second bit slice 18, and the layer including the fourth bit slice 54 has a per-decoder slice ratio greater than that of the layer including the third bit slice 50, while the layer including the first bit slice 14 has a per-decoder slice ratio equal to that of the layer including the second bit slice 18. In particular, the per-decoder slice ratio of the layer including the third bit slice 50 is twice that of the layer including the first bit slice 14 and the second bit slice 18, and the per-decoder slice ratio of the layer including the fourth bit slice 54 is twice that of the layer including the third bit slice 50. Thus, both the layer including the first bit slice 14 and the layer including the second bit slice 18 have a per-decoder slice ratio of 1:1. The layer including the third bit slice 50 has a per-decoder slice ratio of 2:1, and the layer including the fourth bit slice 54 has a per-decoder slice ratio of 4:1. Similarly, both the layer including the first bit slice 14 and the layer including the second bit slice 18 have a layer width group size of 1. The layer including the third bit slice 50 has a layer width group size of 2, and the layer including the fourth bit slice 54 has a layer width group size of 4. However, it should be understood that the per-decoder slice ratios and layer width group sizes shown are merely exemplary, and other per-decoder slice ratios are possible according to various applications and embodiments. Additionally, although some examples are arranged such that for layers of bit slices closer to the bit line decoder 42, the per-decoder slice ratio of the layer will generally be greater, other per-decoder slice ratio gradients are possible. Further, it should be understood that the same or similar manner of varying per-decoder slice ratios as described above for bit slices 14, 18, 50, 54 can be applied to word slices 26, 30 and the word line decoder 46 to implement the structure of a memory architecture with more word slice layers.

[0033] Although the invention herein has been described with reference to particular embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. Thus, it should be understood that several modifications may be made to the illustrative embodiments and other arrangements may be designed without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An array and contact architecture for three-dimensional memory cells, comprising: A plurality of planar and parallel bit region layers, each of the bit region layers including bit lines extending in a bit line direction; A decoder, the bit region layers being electrically connected to the decoder through contacts, Wherein, The plurality of bit region layers include: A first layer; An intermediate layer, the intermediate layer being closer to the decoder and including bit regions shorter than the bit regions in the first layer in the bit line direction, such that the bit regions of the intermediate layer can be assembled between the contacts associated with the bit regions in the first layer; and An outer layer, the outer layer being closer to the decoder than the intermediate layer and including bit regions shorter than the bit regions in the intermediate layer in the bit line direction, such that the bit regions in the outer layer can be assembled between the contacts associated with the bit regions in the first layer and the intermediate layer, Wherein each bit region layer has a per decoder region ratio, the per decoder region ratio being defined as the ratio of the total number of bit regions in the bit region layer to the total number of decoders electrically connected to the bit regions in the bit region layer, and the intermediate layer has a per decoder region ratio greater than that of the first layer.

2. The architecture according to claim 1, wherein The outer layer has a per decoder region ratio greater than that of the intermediate layer.

3. The architecture according to claim 1, wherein, The plurality of bit region layers further include a second layer, the second layer being farther from the decoder than the intermediate layer and the outer layer and having bit regions with the same length as the bit regions in the first layer in the bit line direction.

4. The architecture according to claim 3, wherein: The second layer has the same per decoder region ratio as the first layer; The intermediate layer has a per decoder region ratio greater than that of the first layer; And The outer layer has a per decoder region ratio greater than that of the intermediate layer.

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