Error correction for a stepwise signal modification circuit

Abstract

Circuits and methods for correcting errors in a multi-step signal modification circuit. Embodiments of the invention also provide flexibility in correcting accuracy errors over a range of conditions, such as differences in signal frequency and / or temperature. A first embodiment includes ordering actual values of a multi-step signal modification circuit to generate a monotonic list of actual values, mapping input codes to new sequential codes corresponding to the ordered actual values, and providing a mapping function to convert each input code to a mapped output code. A second embodiment includes searching, for each ideal value corresponding to an input code, the actual values of a multi-step signal modification circuit for an actual value closest to the ideal value, mapping input codes to new sequential codes corresponding to the closest actual values, and providing a mapping function to convert each input code to a mapped output code.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 448,930, filed June 21, 2019, entitled “Error Correction for Stepwise Signal Modification Circuits,” the contents of which are incorporated herein by reference in their entirety.

[0003] This invention may relate to the following patents and / or patent applications, all of which are assigned to the assignee of this invention, the entire contents of which are incorporated herein by reference:

[0004] • U.S. Patent Application Serial No. 16 / 013,844, entitled “High Resolution Attenuator or PhaseShifter with Weighted Bits”, filed on June 20, 2018, is now U.S. Patent No. 10,505,511, published on December 10, 2019.

[0005] • U.S. Patent No. 9,397,635, entitled “Segmented Attenuator with Glitch Reduction”, issued on July 19, 2016;

[0006] • U.S. Patent No. 9,634,650, entitled "State Change Stabilization in a PhaseShifter / Attenuator Circuit," issued on April 25, 2017; and

[0007] • U.S. Patent No. 10,062,946, entitled “Reflection-Based RF Phase Shifter”, issued on August 28, 2018. Background Technology (1) Technical Field

[0009] The present invention relates generally to electronic circuits, and more specifically to electronic error correction circuits and methods for step-type signal modification circuits (e.g., attenuators and / or phase-shifting circuits). (2) Background Technology

[0011] Many electronic circuits—especially those designed to transmit radio frequency signals—include multiple coupling stages that together provide a step-by-step modification or transformation of the applied input signal.

[0012] As an example of a stepped signal modification circuit, a digital step attenuator (DSA) is an electronic device that reduces the power of an applied signal in discrete steps without significantly distorting its waveform. DSAs are often used with radio frequency (RF) systems such as transceivers for broadcast radios, cellular phones, and RF-based digital networks (e.g., Wi-Fi, Bluetooth).

[0013] A typical DSA consists of cascaded switchable dual-state attenuator stages. For example, Figure 1 is a schematic diagram of a prior art binary weighted DSA 100. Four attenuator stages 102a to 102d connected in series are shown. Under the control of a selector 104 that decodes the provided input control code into the respective control lines 106, each attenuator stage 102a to 102d can be switched to a valid “attenuation” state or a “bypass” state (also called a “reference state”). Each attenuator stage 102a to 102d can be considered to have a “bit position” associated with a single control line 106. In this example, the 4-bit input control code applied to the selector 104 can set 16 attenuation combinations from no attenuation (i.e., all stages are in the bypass state) to 15dB attenuation (i.e., all stages are in the attenuation state) in a minimum step size of 1dB. Additional background on DSAs can be found in the patent application entitled “High Resolution Attenuator or Phase Shifter with Weighted Bits” cited above.

[0014] Digital phase shifter (DPS) circuits are another example of stepped signal modification circuits. DPS circuits are used to change the transmission phase angle of a signal and are commonly used to phase-shift RF signals. RF phase shifter circuits can be used in applications such as in-phase discriminators, beamforming networks, power dividers, power amplifier linearization, and phased array antennas.

[0015] A typical DPS circuit is a collection of digitally controlled, cascaded phase shifter stages that provide a set of discrete phase states selectable directly or after decoding via control words or control codes, similar to a DSA 100. For example, Figure 2 is a schematic diagram of a prior art binary-weighted DPS 200. Four cascaded phase shifter stages 202a to 202d are shown. Under the control of selectors 204 that decode the provided input control codes into individual control lines 206, each phase shifter stage 202a to 202d can be switched to a valid “phase-shifted” state or a “bypass” state (also called a “reference state”). Therefore, each phase shifter stage 202a to 202d can be considered to have a “bit position” associated with a single control line 206. In this example, the 4-bit input control code applied to selector 204 can set 16 phase shift combinations from no phase shift (i.e., all stages are in bypass state) to 168.75° phase shift (i.e., all stages are in phase shift state) with a minimum step size of 11.25°. Additional background on DPS can be found in the patent application entitled "High Resolution Attenuator or Phase Shifter with Weighted Bits" cited above.

[0016] In DSAs and DPSs such as those described above, each attenuator stage or phase shifter stage is typically described as having a bit position assigned from the associated selectors 104, 204 corresponding to one of the control lines 106, 206. For example, in Figure 1, attenuator stage 102d can be considered as associated with the most significant bit (MSB) of a 4-bit binary weighted control word or control code, while attenuator stage 102a can be considered as associated with the least significant bit (LSB) of a 4-bit binary weighted control word or control code. The binary weighted control code “1001” sets attenuator stages 102d and 102a to an effective attenuation state (a total of 9 dB in the example shown), while attenuator stages 102b and 102c are set to a bypass (reference) state. A similar mapping of control code bits to phase shifter stages can be applied to the DPS 200 shown in Figure 2.

[0017] While the examples of DSA and DPS above use binary weighted control words or control codes, other commonly used bit position weighting schemes are thermometer weighting (i.e., the decay or phase shift value increases or decreases with each unit change in state) and hybrid thermometer / binary weighting. Further descriptions of such conventional weightings can be found in the patent application titled "Segmented Attenuator with Glitch Reduction" cited above.

[0018] In practice, DSA, DPS, and other multi-stage step signal modification circuits (e.g., digital-to-analog converters or DACs) typically exhibit errors in one or more stages. This results in distortion of the signal modification (e.g., attenuation, phase shift, etc.) relative to the control code value, which adversely affects accuracy, differential nonlinearity, and integral nonlinearity.

[0019] For example, Figure 3A This is a diagram 300 showing the ideal and actual level attenuations based on the nominal level attenuation for a modeled 6-level binary weighted DSA with 0.25 dB resolution. The DSA can be implemented as a six-level version of the four-level DSA 100 example shown in Figure 1. Assume the modeled DSA is designed with six binary weighted levels, where the nominal attenuation per level is 8 dB, 4 dB, 2 dB, 1 dB, 0.5 dB, and 0.25 dB, respectively. Therefore, in this example, ideally, each level should have exactly twice the attenuation of the previous level (the bar on the left-hand side of the code position for each attenuation level). However, due to component defects or other variations, such as attenuation based on frequency variations, the actual attenuations per level in this example are 8.75 dB, 3.5 dB, 2.27 dB, 1.20 dB, 0.4 dB, and 0.3 dB, respectively. Figure 3B It is based on the nominal attenuation code. Figure 3A The error (difference) between the ideal attenuation value and the actual attenuation value is shown in Figure 310.

[0020] Figure 3C It is aimed at Figure 3A The figure in Figure 320 shows the ideal attenuation of DSA based on binary control code and the modeled actual multi-stage attenuation.

[0021] For a level 6 DSA, there are 2 6(64) Control Codes. Ideally, each input code (in this example, ranging from decimal 0 to 63) should result in a combined attenuation value for the selected stage of the DSA that would fall precisely on the ideal line 320. Since the stages are not ideal attenuators, the actual output attenuation value alternatively falls on curve 322. Note that when the next most significant bit (MSB) stage is activated, such as near decimal code values ​​15, 31, and 47, a large jump in attenuation typically occurs. For example, as shown within dashed circle 326, when the next MSB stage is activated, the attenuation at code value 32 (binary 100000) jumps significantly from the attenuation at code value 31 (binary 011111). However, in some cases, the next higher code results in a lower attenuation level rather than a higher attenuation level; this is the case within dashed circle 324, where when the next MSB stage is activated, the attenuation at code value 16 (binary 010000) is lower than the attenuation at code value 15 (binary 001111).

[0022] Figure 3D It is aimed at Figure 3A The figure 330 shows the differential nonlinearity (DNL) 332 and integral nonlinearity (INL) 334 of the DSA according to the binary control code. Given an example level error, the DNL plot shown, particularly the deviation from 0 dB, demonstrates a significant error in the attenuation characteristics.

[0023] High accuracy is required in multi-stage step signal modification circuits. If such errors are systematic, they can often be corrected by redesigning the circuit; however, such redesign can be costly for some processing or applications. Therefore, it is necessary to correct accuracy errors in multi-stage step signal modification circuits without redesigning the circuit. It would also be useful if such correction provided the flexibility to correct accuracy errors under a range of conditions, such as differences in signal frequency and / or temperature. This invention provides a solution that meets these or more of these needs. Summary of the Invention

[0024] This invention includes circuitry and methods for correcting accuracy errors in multi-stage stepped signal modification circuits without requiring circuit redesign. Embodiments of the invention also provide flexibility in correcting accuracy errors under a range of conditions, such as differences in signal frequency and / or temperature.

[0025] The first implementation includes: sorting the actual values ​​of the multi-stage step signal modification circuit to generate a monotonic list of the actual values; mapping input codes to codes in a new order corresponding to the sorted actual values; and providing a mapping function to convert each input code input to the multi-stage step signal modification circuit into a mapped output code.

[0026] The second implementation includes: for each ideal value corresponding to an input code, searching for the actual value closest to the ideal value among all actual values ​​of the multi-stage step signal modification circuit; mapping the input code to a new order of codes corresponding to the closest actual value; and providing a mapping function to convert each input code input to the multi-stage step signal modification circuit into a mapped output code.

[0027] Details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will become apparent from the description, the drawings, and the claims. Attached Figure Description

[0028] Figure 1 is a schematic diagram of the prior art binary weighted DSA.

[0029] Figure 2 is a schematic diagram of the binary weighted DPS of the prior art.

[0030] Figure 3A It is a graph of ideal and actual level attenuation based on nominal level attenuation for a modeled 6-level binary weighted DSA with 0.25dB resolution.

[0031] Figure 3B It is based on the nominal attenuation code. Figure 3A The graph shows the error (delta) between the ideal attenuation value and the actual attenuation value.

[0032] Figure 3C It is aimed at Figure 3A The graph shows the ideal attenuation of DSA based on binary control code and the modeled actual multi-stage attenuation.

[0033] Figure 3D It is aimed at Figure 3A The graph shows the differential nonlinearity (DNL) and integral nonlinearity (INL) of the DSA based on the binary control code.

[0034] Figure 4A It shows the sorting from lowest to highest. Figure 3C A graph showing the decay values.

[0035] Figure 4B It is aimed at Figure 4A The graph shows the differential nonlinearity (DNL) and integral nonlinearity (INL) of the calibrated DSA based on the binary control code.

[0036] Figure 5 This is a flowchart summarizing a first method for correcting accuracy errors in multi-stage step signal modification circuits using sorted and mapped input codes.

[0037] Figure 6A It is a chart of ideal attenuation and modeled actual multi-stage attenuation based on binary control code for DSA with a certain degree of accuracy error.

[0038] Figure 6B It is aimed at Figure 6A The example shown is a diagram mapping input control codes to output control codes.

[0039] Figure 6C It is aimed at Figure 6A The graphs of ideal attenuation and modeled actual multi-stage attenuation based on binary control codes are generated using the corrected and mapped input codes of the DSA.

[0040] Figure 6D It is aimed at Figure 6C The graph shows the differential nonlinearity (DNL) and integral nonlinearity (INL) measurements of the calibrated DSA based on the binary control code.

[0041] Figure 7 This is a flowchart summarizing a second method for correcting accuracy errors in multi-stage step signal modification circuits using adapted and mapped input codes.

[0042] Figure 8 This is a block diagram of an example circuit that can be used to convert each input control code input to a multi-stage step signal modification circuit into a mapped output control code.

[0043] Figure 9 This is a block diagram of an example circuit that can be used to convert each input control code input to a multi-stage step signal modification circuit into a mapped output control code using a reduced lookup table.

[0044] Figure 10A It is a graph of ideal attenuation and modeled actual multi-stage attenuation based on binary control codes for a 5-bit DSA using calibrated and mapped input codes.

[0045] Figure 10B It uses additional resolution bits to map the output code. Figure 10A A graph showing the ideal attenuation of a 5-bit DSA based on binary control code and the modeled actual multi-stage attenuation.

[0046] Figure 11A It is a chart of ideal attenuation, original multi-level attenuation, and reordered multi-level attenuation for all 6-bit DSAs based on binary control codes.

[0047] Figure 11BIt is a graph of ideal attenuation based entirely on binary control codes for 6-bit DSAs, raw multi-level attenuation using smaller MSB values, and reordered multi-level attenuation.

[0048] Figure 11C It is aimed at Figure 11A A graph showing the characteristics of the error vector [X,1,0,0,0,0] of a 6-bit DSA.

[0049] Figure 11D It is aimed at Figure 11A A graph showing the characteristics of the 6-bit DSA, but using the error vector [X,1,0,0,0,0] of the next most significant bit level (i.e., the N-1th level) with negative bias.

[0050] Figure 11E It is shown Figure 11B and Figure 11D A graph showing the combined negative bias and the resulting reordering error correction curve of the embodiment illustrated.

[0051] Figure 12A This is a chart of ideal attenuation, original multi-stage attenuation, and reordered multi-stage attenuation for an example 6-bit DSA where the amount of error cannot be corrected by simply using bit reordering.

[0052] Figure 12B It is a graph of the ideal attenuation of the entire 7-bit DSA based on the binary control code, the original multi-level attenuation with added fractional levels, and the reordered multi-level attenuation.

[0053] Similar reference numerals in the various figures indicate similar elements. Detailed Implementation

[0054] This invention includes circuitry and methods for correcting accuracy errors in multi-stage stepped signal modification circuits without requiring circuit redesign. Embodiments of the invention also provide flexibility in correcting accuracy errors under a range of conditions, such as differences in signal frequency and / or temperature.

[0055] For ease of explanation, the invention will be described in reference to a digital step attenuator (DSA). However, the concept of the invention is also applicable to other multi-stage step signal modification circuits, such as digital phase shifters (DPS) and digital-to-analog converters (DACs).

[0056] Sorting and Reordering Implementation Methods

[0057] As mentioned above, Figure 3C It is aimed at Figure 3AThe graph 320 shows the ideal attenuation of the DSA based on the binary control code and the modeled actual multi-stage attenuation. In the first embodiment, to at least partially correct for the deviation or error between the actual curve 322 and the ideal straight line 320, the attenuation values ​​are sorted to generate a monotonic list of attenuation values. For example, Figure 4A It shows the sorting from lowest to highest. Figure 3C The graph 400 shows the attenuation values. The result is an improved curve 402, which forces the code-to-code transition to be monotonic (i.e., without, for example, in...). Figure 3C The attenuation jump that occurs in the opposite direction in the dashed coil 324 provides a significant improvement.

[0058] Because the attenuation values ​​are sorted, the corresponding codes can no longer be sequentially ordered. For example, after sorting, code value 15 might correspond to the attenuation level generated by code value 17 before sorting. Therefore, it is necessary to map the input codes to a new order of codes corresponding to the sorted attenuation values ​​in order to convert each input code into a mapped code. For example, the mapping function can be implemented in a hardware or software-implemented lookup table (LUT), implemented as a software-implemented conditional statement, or implemented in combinational logic circuitry. The mapping circuitry can be implemented on the same integrated circuit (IC) device as a multi-stage step signal modification circuit, or externally to such an IC device. Details of one implementation of the mapping function are described below.

[0059] Figure 4B It is aimed at Figure 4A Chart 420 shows the differential nonlinearity (DNL) 422 and integral nonlinearity (INL) 424 of the corrected DSA according to the binary control code. (Compared to...) Figure 3D Compared to DNL 332, DNL 422 shows a significantly reduced deviation from 0 dB. In this specific example, the RMS error improved from approximately 0.23 dB to approximately 0.18 dB. Additionally, compared to... Figure 3D Compared to INL 334, Figure 4B The INL 424 in the model has been improved.

[0060] As described above, the sorting process illustrated by the DSA example is applicable to any multi-stage step signal modification circuit, such as a DPS or DAC, that exhibits the aforementioned type of accuracy error.

[0061] Figure 5This is a flowchart 500 summarizing a first method for correcting accuracy errors in a multi-stage step signal modification circuit using sorted and mapped input codes. The process includes sorting the actual values ​​of the multi-stage step signal modification circuit to generate a monotonic list of actual values ​​(box 502); mapping the input codes to codes in a new order corresponding to the sorted actual values ​​to generate corresponding mapped output codes (box 504); and providing a mapping function to convert each input code input to the multi-stage step signal modification circuit into a mapped output code (box 506).

[0062] Code Transformation Implementation Methods

[0063] The second implementation method can achieve even greater improvements in accuracy error. For each control code corresponding to the ideal attenuation value, the value whose attenuation is closest to that ideal attenuation value is searched in a list of all actual attenuation values—essentially, the "best fit" actual attenuation value is found for each ideal attenuation value, thereby enabling the input code to be transformed by mapping to a new code set.

[0064] For example, Figure 6A This is a diagram 600 showing the ideal attenuation 602 and the modeled actual multi-stage attenuation 604 based on binary control codes for a DSA with a certain degree of accuracy error. Each code value corresponds to an ideal attenuation level. In the example shown, control code value 40 ideally results in a 10 dB attenuation level for the DSA. However, due to per-stage accuracy error, code value 40 actually results in an attenuation level of approximately 11 dB for the example DSA. A search of all actual attenuation values ​​shows that an actual attenuation level very close to 10 dB corresponds to code value 36. Therefore, input code value 40 should be mapped to code value 36. Thus, when input control code value 40 is applied to the DSA, the mapping function is replaced with code value 36, and the stage in the DSA corresponding to code value 36 is activated.

[0065] exist Figure 6AThe process of this implementation is graphically illustrated by connecting the straight line representing the ideal attenuation 602 to the short line 606 representing the actual multi-level attenuation 604 of the model. Each short line 606 connects an ideal attenuation value corresponding to an input code to the available best-fitting actual attenuation value. In this example, control code value 30 is mapped to an actual attenuation value that corresponds exactly to the ideal attenuation value assigned to code value 30. As described above, control code value 40 is mapped to an actual attenuation value that would typically be generated by code value 36. In some cases, two or more input control codes are mapped to the same best-fitting actual attenuation value. For example, in the example shown, input control code values ​​33, 34, and 35 best correspond to the actual attenuation value (approximately 9 dB) that would typically be generated by input control code value 32 (see ellipse 608).

[0066] Figure 6B It is aimed at Figure 6A The example shown is graph 620, which maps input control codes to output control codes. Graph 622 shows the input control codes mapped to unordered control codes (i.e., input control code = output control code), while graph 624 shows the input control codes mapped to reordered output control codes. The difference (differential) between the unordered and reordered output control codes is shown in graph 626. As this example demonstrates, in most cases, input control codes can be mapped to nearby (e.g., ±3 or ±4) output control code values.

[0067] Figure 6C It is aimed at Figure 6A The graph 630 shows the ideal attenuation 602 and the modeled actual multi-level attenuation 634 of the DSA using the corrected and mapped input code based on the binary control code. As shown in the graphical curve for the modeled actual multi-level attenuation 634, as a result of the above code transformation, the actual attenuation value is closer to the ideal attenuation value 602.

[0068] Figure 6D It is aimed at Figure 6C Figure 640 shows the differential nonlinearity (DNL) measurement results 642 and integral nonlinearity (INL) measurement results 644 of the calibrated DSA based on the binary control code. In this particular example, the INL RMS error improved from approximately 0.59 dB to approximately 0.13 dB. The DNL RMS error improved from approximately 0.23 dB to approximately 0.20 dB.

[0069] The transformation from the M input control codes described above to a new set of M output control codes can be mathematically represented as follows: Definition:

[0070] a k≡The ideal response to input control code k, k∈{0,1,...,M}

[0071] b k ≡ The actual response to input control code k, k∈{0,1,...,M}

[0072] c k ≡Optimized (“bit-reordered”) output control code response to input control code k, k∈{0,1,...,M}

[0073] Then:

[0074] c k =b m m = arg min{|b m -a k |}, k∈{0,1,...,M}.

[0075] Similar to the sorting implementation described above, the code corresponding to the actual set of attenuation values ​​for "best fit" is unlikely to be ordered sequentially. Therefore, as... Figure 6B As shown, it is necessary to map the input codes to a new order of codes corresponding to the sorted decay values, so that each input code is converted into a mapped code. The mapping function can be implemented, for example, in a hardware or software-implemented lookup table (LUT), implemented as a software-implemented conditional statement, or implemented in combinational logic circuitry. The mapping circuitry can be implemented on the same integrated circuit (IC) device as a multi-stage step-by-step signal modification circuit, or implemented externally to such an IC device. Details of one implementation of the mapping function are described below.

[0076] Furthermore, the code transformation process described in the DSA example is applicable to any multi-stage step signal modification circuit exhibiting the accuracy errors described above. In the example illustrated above, the error was described only for a "signal modification circuit" with binary weighted stages. Another common way to construct such a circuit is to use "thermometer-encoded" stages, where each stage adds an equal increment to the total number of stages, instead of a binary-weighted increment. In some applications, a combination of binary and thermometer stages is used. Note that the bit reordering method described above applies to all of these implementations.

[0077] Figure 7This is a flowchart 700 summarizing a second method for correcting accuracy errors in a multi-stage step signal modification circuit using adapted and mapped input codes. The process includes: searching for the closest actual value to the ideal value among all actual values ​​of the multi-stage step signal modification circuit for each ideal value corresponding to the input code (box 702); mapping the input code to a new order of codes corresponding to the closest actual value to generate a corresponding mapped output code (box 704); and providing a mapping function to convert each input code input to the multi-stage step signal modification circuit into a mapped output code (box 706).

[0078] Mapping function

[0079] Figure 8 This is a block diagram of an example circuit that can be used to convert each input control code input to a multi-stage step signal modification circuit into a mapped output control code. The generalized multi-stage step signal modification circuit 800 includes n series-connected signal modification stages 802a to 802n, where n is an integer ≥ 2. Under the control of selectors 804 that decode the provided control code into individual control lines 806, each signal modification stage 802a to 802n can be switched to an active state (e.g., attenuation or phase shift state) or to an inactive state (e.g., bypass or reference state). Each signal modification stage 802a to 802n can be considered to have a “bit position” associated with its corresponding control line 806.

[0080] Compared to the examples in Figures 1 and 2, the input control codes are not applied directly to selector 804, but instead are applied to mapping function 810. Mapping function 810 maps each input control code to an output control code, which is then applied to selector 804.

[0081] The mapping function 810 can be implemented in hardware or software (e.g., hardware addressable memory devices or lookup tables (e.g., RAM, ROM, PROM, etc.)), or as a software-implemented lookup table or conditional statement (e.g., as part of device driver code), or in combinational logic circuitry. The circuitry implementing the mapping function 810 can be implemented on the same integrated circuit (IC) device as the multi-stage step-by-step signal modification circuitry 800, or externally to such an IC device.

[0082] If the mapping function 810 is implemented as a simple lookup table, then in the most general case, the table size will be 2. N ×N bits (2 N The output is an address × N-bit wide, where N is an integer ≥ 1. However, as mentioned above, in the case of code transformation implementation, the input control code can typically be mapped to a nearby (e.g., ±3 or ±4) value (e.g., see...). Figure 6B (See graph 626 in the figure). Since the output of the transformation is usually very close to the input, the transformation can be implemented using a lookup table that stores only the difference between the input control code and the output control code. This difference can be added to the input control code to achieve the transformation or bit reordering. Although this method requires adder circuitry, such circuitry is typically smaller than the additional storage circuitry required.

[0083] For example, Figure 9 This is a block diagram of an example alternative mapping function circuit 810', which can be used to convert each input control code input to a multi-stage step-by-step signal modification circuit into a mapped output control code using a reduced lookup table with a smaller output word or output code (e.g., 4 bits instead of 6 bits). In the example shown, a 6-bit input control code is applied to a 4-bit reduced lookup table 900 and an adder 902. The 4-bit output of the example reduced lookup table 900 is also applied to the adder 902. The 6-bit output of the adder 902 is the sum of the 6-bit input control code and the corresponding 4-bit output of the example reduced lookup table 900. The output of the adder 902 is then applied as the output control code to the multi-stage step-by-step signal modification circuit 800, as... Figure 8 As shown.

[0084] use Figure 6B In the example of graph 626, the error (i.e., the difference between the input control code and the output control code) falls between -6 and +1. This range can be represented by a 4-bit signed number (i.e., -8 to +7). When a 6-bit input control code is applied to the shrink lookup table 900, the corresponding 4-bit difference value is output from the shrink lookup table 900, and this 4-bit difference value is added to the 6-bit input control code in adder 902. As a result, for a 6-bit input control code, the shrink lookup table 900 is only 4 / 6 (i.e., 2 / 3) larger than when adder 902 is not used. Of course, the input control word and output control word can have fewer or more than 6 bits, and the size of the shrink lookup table 900 will be adjusted accordingly.

[0085] Note that in this example, when adding a 4-bit signed number to a 6-bit unsigned number (such as an input control code), the result could be 7 bits due to underflow or overflow. However, this can be prevented by intentionally limiting the values ​​of the input control code in lookup table 900 to near zero or full-scale values, effectively limiting the corresponding output control codes to zero or full-scale values ​​respectively. The same principle applies to control codes with fewer or more than 6 bits.

[0086] As described above, accuracy errors can be reduced by redesigning the multi-stage step signal modification circuit. However, for radio frequency circuits, some stages may behave differently at different frequencies. If so, redesign may also be incorrect within the frequency range. In contrast, embodiments of the present invention can utilize multiple mapping functions 810, one mapping function for each frequency range (e.g., VHF, UHF, etc.) and / or frequency band (e.g., cellular radio bands B1, B2, B3, etc.). For example, the lookup table can have multiple pages, each page loaded with mapping transformations for different frequency ranges and / or frequency bands. The selection of a specific page will be made by one or more control signals associated with the frequency range and / or frequency band. A similar approach can be used to provide temperature-dependent mapping transformations for multi-stage step signal modification circuits with temperature-varying stages.

[0087] The mapping required for the sequencing or code transformation implementation of the present invention can be determined based on characterization data or calibration data. Characterization data can be obtained for a specific design of the multi-stage step signal modification circuit by sampling the test circuit, determining a suitable mapping according to the above description, and applying the mapping to all manufacturing units of the circuit. Calibration data can be obtained by testing each unit of the multi-stage step signal modification circuit, determining a suitable mapping according to the above description, and applying the mapping to the unit under test of the circuit.

[0088] Somewhat surprisingly, using imprecise attenuation levels in multi-stage stepped signal modification circuits often provides additional design flexibility. For example, in DSA, the IC layout for specific imprecise attenuation level values ​​can scale better than for precise values.

[0089] Extended accuracy

[0090] It is known that at the design level of a multi-stage stepped signal modification circuit planning bit reordering code transformation, there are some design changes that will further improve accuracy results. This section describes three methods for extending the accuracy of multi-stage stepped signal modification circuits to which bit reordering code transformation is applied: fine bit resolution over-provisioning, negative bias of one or more stages, and adding fractional MSB.

[0091] Fine-grained resolution over-provisioning: An additional M bits of resolution (where M is an integer ≥ 1) can be added to reduce resolution noise by selecting the best-fitting (N+M)-bit output control code through mapping N-bit input control codes (where N is an integer ≥ 2) to (N+M) signal modification levels. One or more “over-provisioning” bits of resolution can be provided by one or more relatively small added LSB levels (“adjustment bits”), such that the smaller added LSB level is, for example, half the value of the “normal” LSB level, which would otherwise exist without over-provisioning.

[0092] For example, Figure 10A This is a graph 1000 showing the ideal attenuation 1002 and the modeled actual multi-stage attenuation 1004 based on the binary control code for a 5-bit DSA using a corrected and mapped input code. Figure 10B Is the value less than Figure 10A The configuration allocates additional resolution bits to the LSB to map the output code. Figure 10A The graph 1020 shows the ideal attenuation 1002 and the modeled actual multi-stage attenuation 1024 of the 5-bit DSA based on the binary control code. It can be seen that... Figure 10B The graph curve 1024 is higher than Figure 10A The graph curve 1004 is closer to the ideal attenuation line 1002, which indicates a smaller error. Numerically, Figure 10A The system's RMS INL is approximately 0.22 dB, while Figure 10B The RMS INL of the system is approximately 0.13 dB.

[0093] Therefore, embodiments of the present invention can use overconfiguration to provide a larger number of possible states than the required number of output states (e.g., 2^(N+1), 2^(N+2), etc.) to increase the likelihood of optimal fit between the N-bit input control code and the (N+M)-bit output control code. Further discussion of overconfiguration can be found in the patent application entitled "Reflection-Based RF Phase Shifter" cited above.

[0094] Negative bias of one or more levels: If the designer knows where the problem bits or errors might occur, and knows that bit reordering code transformations are available, the designer can adjust the design to compensate. For example, if the MSB level typically causes the maximum error, the MSB level can be designed with values ​​intentionally smaller than some ideal value (e.g., 7dB instead of 8dB). Achieving the target original MSB value might require a combination of smaller MSB levels plus some combination of levels with lower values, but by design there will at least be a solution, and therefore the target original MSB value will not be skipped in the reordering (although the trade-off is a reduction in the overall range).

[0095] For example, Figure 11A This is a diagram 1100 showing the ideal attenuation 1102, the original multi-stage attenuation 1104, and the reordered multi-stage attenuation 1106 for a 6-bit DSA, all based on the binary control code. Due to the relatively large error in the MSB stage, there is a large jump in the output attenuation when the MSB stage is activated (see ellipse 1108), resulting in a substantially constant error across all higher output values. Reordering the control code as described above provides a significant reduction in overall error, but a noticeable error still exists where the MSB stage error cannot be fully compensated (see again ellipse 1108).

[0096] Replacing with an MSB level whose value is smaller than the original MSB level typically allows for a reordering closer to the ideal. For example, Figure 11B This is a diagram 1120 showing the ideal attenuation 1102 based entirely on binary control codes for a 6-bit DSA, the original multi-stage attenuation 1124 using smaller MSB levels, and the reordered multi-stage attenuation 1126. When the MSB level is activated (see ellipse 1128), a certain degree of MSB error is introduced for all higher output values. However, compared to... Figure 11A Compared to the MSB level in the original configuration, by intentionally designing the MSB level to have a smaller attenuation when activated, the MSB error drops below the ideal attenuation level of 1102 (i.e., negative bias), and can therefore be compensated for by reordering. Essentially, reordering shifts the upper bound of the MSB error range (the combination of MSB and LSB) downwards to overlap with the lower bound of the reordered values. As mentioned above, the trade-off is a reduced overall range, as shown by the flattened output attenuation within ellipse 1129 (i.e., control code values ​​exceeding approximately 59 do not generate a different output attenuation).

[0097] Figure 11A The binary error shown is common to both DSA and DPS. Clearly, the sudden step change in value when each level is activated or deactivated causes most of the uncorrectable error. To understand such errors more generally, consider how these steps occur. Taking DSA as an example, the actual response to the k-th control word is given by the following equation:

[0098]

[0099] Where, γ i It is the i-th coefficient in the binary extension of k, and α i This is the actual attenuation at level i. We can determine the ideal attenuation at level 2. i Δ and level attenuation error e i The actual attenuation of the level: α i =2 iΔ+e i Therefore, the total attenuation error is given by the following formula:

[0100]

[0101] Larger attenuation stages tend to have larger errors. Consider a 6-bit attenuator with the following error vectors: [1,0,0,0,0,0] and [X,1,0,0,0,0], where X is either 0 or 1 (i.e., "irrelevant" value). Figure 11A Including a graphical curve of the characteristics obtained for the error vector [1,0,0,0,0,0] (i.e., the “MSB error” portion of the original multi-level decay 1104 plot). Figure 11C It is aimed at Figure 11A Figure 1130 shows the characteristics of the error vector [X,1,0,0,0,0] of the 6-bit DSA.

[0102] like Figure 11A As shown in ellipse 1108, when the MSB level (i.e., the Nth level) is activated, the maximum error is associated with the change from [0,1,0,0,0,0] to [1,0,0,0,0,0]; see also Figure 11A The sudden step in ellipse 1108. When the next highest effective level (i.e., level N-1) is activated, the second largest error occurs between [X,0,1,1,1,1] and [X,1,0,0,0,0]; for the original multi-stage attenuation shown by graphs 1134a and 1134b, see Figure 11C The sudden steps in ellipses 1138a and 1138b can be plotted as a similar (but typically smaller) error corresponding to the activation of each lower effective bit level. As shown in graph 1136 of the reordered multi-level decay configuration, the sudden steps in ellipses 1138a and 1138b cannot be corrected by the reordering process.

[0103] Note that if the error is negatively biased relative to the ideal attenuation 1102 plotting line, the plotting error can be minimized because, using the reordering method described above, only positive jumps in the error produce uncorrectable gaps. For example, assume the attenuation stage error is at -2... i Δ / 8dB and +2 iThe error is uniformly distributed between Δ / 8dB. Therefore, the 8dB level will have an error between ±1dB, the 4dB level will have an error between ±0.5dB, and so on. One aspect of some embodiments of the invention is to partially negatively bias the error. For example, a reasonable trade-off would be to target level attenuation values ​​of 7dB, 3.5dB, 2dB, 1dB, 0.5dB, and 0.25dB, rather than the conventional values ​​of 8dB, 4dB, 2dB, 1dB, 0.5dB, and 0.25dB. Therefore, the first two most significant bits will be weighted at 7dB and 3.5dB instead of 8dB and 4dB.

[0104] As mentioned above, Figure 11B The effect of a negative bias MSB level is shown (in this example, by using an MSB level value of 7dB; note that the error from other levels is...). Figure 11B (Ignored in the middle). Similarly, Figure 11D It is aimed at Figure 11A Figure 1140 shows the characteristics of the 6-bit DSA, but with the error vector [X,1,0,0,0,0] of the next most significant bit level (i.e., the N-1th level) using a negative bias. Figure 11D Graphs 1144a and 1144b show the resulting negative bias error from the original (unordered) output attenuation according to the control code. Graph 1146 shows the attenuation configuration for the reordered multi-stage attenuation. Figure 11C The original abrupt step in ellipses 1138a and 1138b can be corrected by a reordering process that substantially shifts the upper bound of the reordered values ​​downward to overlap with the lower bound of the reordered values.

[0105] Another way to observe this process is: negatively biasing some stages relative to the ideal attenuation level will place the error at the point where it begins (e.g., at...). Figure 11A Ellipse 1108 and Figure 11C Within ellipses 1138a and 1138b, the error is moved to the top of the range of each such level. Importantly, by applying the above reordering process, the moved error can usually be corrected together with the reordering correction of the next larger level (wherein, the total residual error is moved to the top of the range of the combined level). Thus, for example, in Figure 11D In this process, all uncorrectable errors at level N-1 are moved to the vicinity of control code values ​​30 and 60. When level N is corrected by applying the above reordering process, errors near control code value 30 can typically be corrected.

[0106] Figure 11B Showing with Figure 11A Compared to the negative bias of the original multi-stage attenuation of 1124 for the MSB stage (i.e., the Nth stage) using a smaller value, similarly, Figure 11D It shows the relationship with Figure 11C The negative bias of the next most significant bit level (i.e., the N-1th level) compared to the original multi-level attenuation of 1124 with a smaller value. Figure 11E It is shown Figure 11B and Figure 11D The diagram 1150 shows a plot of the combined negative bias and the resulting reordering error correction of the embodiment illustrated. Line 1154 is essentially... Figure 11B The graph of line 1124 and Figure 11D The vector sum of curves 1144a and 1144b. Curve 1156 is shown for the reordered multi-stage attenuation configuration: Figure 11A Ellipse 1108 and Figure 11C The sudden step in ellipses 1138a and 1138b can be corrected by the reordering process by substantially shifting the upper limit of the reordered values ​​downward to overlap with the lower limit of the reordered values, with some slight loss of the overall range.

[0107] Added Score MSB: A third design modification to improve accuracy utilizes the aforementioned bit reordering technique by adding a score MSB level. For example, Figure 12A This is a diagram 1200 for an example 6-bit DSA where the amount of error cannot be corrected by simply using bit reordering, showing the ideal attenuation 1102, the original multi-stage attenuation 1204, and the reordered multi-stage attenuation 1206, all based on binary control codes.

[0108] The accuracy of DSA can be improved by adding intermediate levels that have fractional values ​​relative to the MSB level. For example, in Figure 12A In the example, the jump in error is due to the control code changing from [0,1,0,0,0,0] to [1,0,0,0,0,0] and from [X,0,1,1,1,1] to [X,1,0,0,0,0]. This jump can be corrected by applying the reordering transformation as described above, by adding an additional attenuation level less than half the MSB level attenuation (e.g., 3 dB in this example). Figure 12B This is a diagram 1220 showing an example 6-bit DSA with 6 input control bits mapped to a 7-bit DSA core, all based on the ideal attenuation 1102 according to binary control codes, the original multi-level attenuation 1224 with added fractional levels, and the reordered multi-level attenuation 1226. As can be seen, the jumps seen in Figure 12 are corrected by being able to include added fractional levels during the reordering process. Furthermore, although the full 7-bit attenuation range is reduced, it is still comparable to... Figure 12A Compared to DSA, the actual attenuation range is increased.

[0109] Combination of Accuracy Improvement Techniques: In embodiments of the present invention, two or more of the three accuracy improvement techniques described above—fine bit resolution over-provisioning, one or more stages of negative bias, and added fractional MSB—can be combined. Adding attenuator stages may increase insertion loss, which is acceptable for systems where accuracy is paramount. On the other hand, one or more stages of negative bias do not introduce additional insertion loss, where the trade-off is a slight reduction in range. Therefore, this aspect of the present invention provides designers with great flexibility in combining the aforementioned reordering techniques to improve the accuracy of multi-stage stepped signal modification circuits.

[0110] Two-dimensional remapping

[0111] Some RF applications utilize both a series-connected phase-shifting multi-stage stepped signal modulator circuit and a series-attenuation multi-stage stepped signal modulator circuit. Many implementations of the phase-shifting circuit affect the attenuation level of the input RF signal based on the selected phase shift, and many implementations of the attenuator circuit affect the phase of the input RF signal based on the selected attenuation level. Therefore, the series coupling of the phase-shifting and attenuation circuits (in any order) presents complexity, where selecting the desired final phase shift and attenuation levels is the function of two interdependent circuits.

[0112] This complexity can be overcome by essentially viewing the cascaded circuit as a single "two-dimensional" (or "2-D") multi-stage stepped signal modification circuit that modifies both phase and amplitude. Therefore, the reordering technique described above can be applied to 2-D circuits, for example, by mapping each combination of phase and attenuation input control codes to corresponding output control codes representing a list of the closest actual values ​​(phase and amplitude) generated by the 2-D circuit. Further discussion of 2-D mapping using different correction methods can be found in the patent application entitled "State Change Stabilization in a PhaseShifter / Attenuator Circuit" cited above.

[0113] Additional methods

[0114] The above is about Figure 5 and Figure 7The described method can be extended by including one or more of the following aspects: wherein the multi-stage step signal modification circuit includes at least one of a digital phase shifter (DPS) circuit and / or a digital step attenuator (DSA) circuit; wherein the multi-stage step signal modification circuit modifies a signal having a frequency of at least 100 MHz; wherein the multi-stage step signal modification circuit is fabricated as a MOSFET circuit; wherein the multi-stage step signal modification circuit is fabricated using a silicon-on-insulator (SOI) fabrication process; wherein the mapping function circuit is configured to map N input control codes to N+M output control codes, wherein N is an integer ≥2 and M is an integer ≥1; and / or wherein the multi-stage step signal modification circuit modifies both the signal phase and the signal amplitude according to the phase and attenuation input control codes, and wherein the mapping function circuit is further configured to map each combination of the phase and attenuation input control codes to an output control code representing a list of the closest actual phase and amplitude values ​​generated by the multi-stage step signal modification circuit.

[0115] Manufacturing technology and options

[0116] As will be apparent to those skilled in the art, various embodiments of the invention can be implemented to meet a wide range of specifications. In particular, selecting suitable components and component values ​​for multi-stage step-by-step signal modification circuitry and / or mapping function circuitry is a matter of design choice, and various embodiments of the invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process (including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS)). The invention can be implemented using other transistor technologies, such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the above-described inventive concepts are particularly useful for SOI-based fabrication processes (including SOS) and for fabrication processes with similar characteristics. CMOS fabrication according to SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (particularly at least 100 MHz and including radio frequencies up to and exceeding 50 GHz). Monolithic IC implementations are particularly useful because parasitic capacitance can typically be kept low (or minimized, kept consistent across all cells, allowing for compensation of parasitic capacitance) through careful design.

[0117] As used in this disclosure, the term "MOSFET" means any field-effect transistor (FET) having an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms "metal" or "metal-like" include at least one conductive material (e.g., aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0118] As used in this specification, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. This term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0119] Depending on specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels and / or the polarity of voltage and / or logic signals can be adjusted. The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to handle higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering the function of the disclosed circuit.

[0120] Summarize

[0121] Many embodiments of the invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order-independent and therefore may be performed in a different order than that described. Furthermore, some of the steps described above may be optional. The various actions described with respect to the methods identified above may be performed in a repetitive, serial, or parallel manner.

[0122] It should be understood that the foregoing description is intended to illustrate, rather than limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all possible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracketed designations of claim elements are for easy reference to such elements and do not in themselves indicate a particular order of claims or an enumeration of elements; furthermore, such designations may be repeated in dependent claims where references to additional elements are not considered to be the beginning of a conflicting sequence of designations.)

Claims

1. A circuit for correcting accuracy errors in a multi-stage step-based signal modification circuit, the multi-stage step-based signal modification circuit being configured to receive a plurality of control codes, each control code determining the level of signal modification performed by one or more stages of the signal modification circuit, the circuit including a mapping function circuit coupled between the multi-stage step-based signal modification circuit and a source of input control codes, the mapping function circuit being configured to map the input control codes to output control codes representing a monotonically ordered list of actual values ​​generated by the multi-stage step-based signal modification circuit, wherein... The mapping function circuit includes: (a) a reduced lookup table for the mapped value, the reduced lookup table being configured to convert an n-bit wide input control code into a smaller-width mapped code; and (b) an adder circuit configured to receive the n-bit wide input control code and the smaller-width mapped code and sum the n-bit wide input control code and the smaller-width mapped code to generate an n-bit wide output control code, wherein the output control code from the mapping function circuit is provided as the plurality of control codes to the multi-stage step signal modification circuit.

2. The circuit according to claim 1, wherein, The reduced lookup table has multi-page mapping values.

3. The circuit according to claim 1, wherein, The reduced lookup table has multiple pages of mapped values, each page corresponding to the selected radio frequency range and / or frequency band.

4. The circuit according to claim 1, wherein, The multi-stage step signal modification circuit includes at least one of a digital phase shifter circuit and / or a digital step attenuator circuit.

5. The circuit according to claim 1, wherein, The multi-stage step signal modification circuit modifies signals with a frequency of at least 100MHz.

6. The circuit according to claim 1, wherein, The multi-stage step signal modification circuit is manufactured as a MOSFET circuit.

7. The circuit according to claim 1, wherein, The multi-stage step signal modification circuit is fabricated using silicon-on-insulator (SiI) fabrication technology.

8. A circuit for correcting accuracy errors in a multi-stage step-signal modification circuit, the multi-stage step-signal modification circuit being configured to receive a plurality of control codes, each control code determining a level of signal modification performed by one or more stages of the signal modification circuit, the circuit including a mapping function circuit coupled between the multi-stage step-signal modification circuit and a source of input control codes, the mapping function circuit being configured to map the input control codes to output control codes representing a list of closest actual values ​​generated by the multi-stage step-signal modification circuit, wherein... The output control code from the mapping function circuit is provided as one of the plurality of control codes to the multi-level step signal modification circuit.

9. The circuit according to claim 8, wherein, The mapping function circuit includes a lookup table for mapping values, which is configured to convert n-bit wide input control codes into n-bit wide control output codes.

10. The circuit according to claim 9, wherein, The lookup table has multiple pages of mapping values.

11. The circuit according to claim 9, wherein, The lookup table has multiple pages of mapping values, each page corresponding to the selected radio frequency range and / or frequency band.

12. The circuit according to claim 8, wherein, The mapping function circuit includes: (a) A reduced lookup table for mapped values, configured to convert n-bit wide input control codes into mapped codes of smaller width; and (b) An adder circuit configured to receive the n-bit wide input control code and the smaller-width mapped code and sum the n-bit wide input control code and the smaller-width mapped code to generate an n-bit wide output control code.

13. The circuit according to claim 12, wherein, The lookup table has multiple pages of mapping values.

14. The circuit according to claim 12, wherein, The lookup table has multiple pages of mapping values, each page corresponding to the selected radio frequency range and / or frequency band.

15. The circuit according to claim 8, wherein, The multi-stage step signal modification circuit includes at least one of a digital phase shifter circuit and / or a digital step attenuator circuit.

16. The circuit according to claim 8, wherein, The multi-stage step signal modification circuit modifies signals with a frequency of at least 100MHz.

17. The circuit according to claim 8, wherein, The multi-stage step signal modification circuit is manufactured as a MOSFET circuit.

18. The circuit according to claim 8, wherein, The multi-stage step signal modification circuit is fabricated using silicon-on-insulator (SiI) fabrication technology.

19. The circuit according to claim 8, wherein, The mapping function circuit is configured to map N input control codes to N+M output control codes, where N is an integer ≥ 2 and M is an integer ≥ 1.

20. The circuit according to claim 8, wherein, The multi-stage step signal modification circuit modifies both the signal phase and signal amplitude according to the phase and attenuation input control codes, and the mapping function circuit is further configured to map each combination of the phase and attenuation input control codes to an output control code representing a list of the closest actual phase and amplitude values ​​generated by the multi-stage step signal modification circuit.

21. A method for correcting accuracy errors in a multi-stage step signal modification circuit, comprising: (a) Sort the actual values ​​of the multi-stage step signal modification circuit to generate a monotonic list of the actual values; (b) Map the input code to the new order of the code corresponding to the sorted actual values ​​to generate the corresponding mapped output code; as well as (c) Provide a mapping function to convert each input code input to the multi-stage step signal modification circuit into a mapped output code.

22. The method according to claim 21, wherein, Providing mapping functionality includes providing a lookup table for mapping values, the lookup table being configured to convert n-bit wide input control codes into n-bit wide control output codes.

23. The method according to claim 21, wherein, The mapping functionality includes providing: (a) A reduced lookup table for mapped values, configured to convert n-bit wide input control codes into mapped codes of smaller width; as well as (b) An adder circuit configured to receive the n-bit wide input control code and the smaller-width mapped code and sum the n-bit wide input control code and the smaller-width mapped code to generate an n-bit wide output control code.

24. The method according to claim 21, wherein, The multi-stage step signal modification circuit includes at least one of a digital phase shifter circuit and / or a digital step attenuator circuit.

25. The method according to claim 21, wherein, The multi-stage step signal modification circuit modifies signals with a frequency of at least 100MHz.

26. The method of claim 21, further comprising manufacturing the multi-stage step signal modification circuit as a MOSFET circuit.

27. The method of claim 21, further comprising using silicon-on-insulator (SiI) fabrication process to fabricate the multi-stage step signal modification circuit.

28. A method for correcting accuracy errors in a multi-stage step signal modification circuit, comprising: (a) For each ideal value corresponding to the input code, search for the actual value that is closest to the ideal value among all the actual values ​​of the multi-stage step signal modification circuit; (b) Map the input code to a new order of code corresponding to the closest actual value to generate the corresponding mapped output code; as well as (c) Provide a mapping function to convert each input code input to the multi-stage step signal modification circuit into a mapped output code.

29. The method according to claim 28, wherein, Providing mapping functionality includes providing a lookup table for mapping values, the lookup table being configured to convert n-bit wide input control codes into n-bit wide control output codes.

30. The method according to claim 28, wherein, The mapping functionality includes providing: (a) A reduced lookup table for mapped values, configured to convert n-bit wide input control codes into mapped codes of smaller width; as well as (b) An adder circuit configured to receive the n-bit wide input control code and the smaller-width mapped code and sum the n-bit wide input control code and the smaller-width mapped code to generate an n-bit wide output control code.

31. The method according to claim 28, wherein, The multi-stage step signal modification circuit includes at least one of a digital phase shifter circuit and / or a digital step attenuator circuit.

32. The method according to claim 28, wherein, The multi-stage step signal modification circuit modifies signals with a frequency of at least 100MHz.

33. The method of claim 28 further comprises manufacturing the multi-stage step signal modification circuit as a MOSFET circuit.

34. The method of claim 28 further comprises using silicon-on-insulator (SiI) fabrication to manufacture the multi-stage step signal modification circuit.

35. The method according to claim 28, wherein, Providing the mapping function includes mapping N input control codes to N+M output control codes, where N is an integer ≥ 2 and M is an integer ≥ 1.

36. The method according to claim 28, wherein, The multi-stage step signal modification circuit modifies both the signal phase and the signal amplitude according to phase and attenuation input control codes. The method further includes mapping each combination of phase and attenuation input control codes to output control codes representing a list of the closest actual phase and amplitude values ​​generated by the multi-stage step signal modification circuit.

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