Device and method for implementing time-domain convolution calculation across clock domains based on FPGA
By building a cross-clock domain time domain convolution calculation device on FPGA and using a pipeline structure to realize the reuse of multipliers and adders, the high latency and resource consumption problems of FPGA convolution calculation are solved, and the real-time performance and resource utilization efficiency are improved.
Patent Information
- Application Number
- CN202111304060.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-05
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2041-11-05
AI Technical Summary
Existing convolution calculation methods on FPGAs have problems of high latency and low real-time performance, which are difficult to meet, especially in applications with high real-time requirements, and consume a lot of resources.
An FPGA-based cross-clock domain time domain convolution calculation device is adopted, and RAM_coef, FIFO_coef and FIFO_conv are used to form a pipeline structure to realize the reuse of multipliers and adders. RAM_coef is used to store convolution coefficients, and FIFO_coef and FIFO_conv are used to store intermediate results, thereby optimizing the multiplication and addition operation processes.
It reduces delay, improves real-time performance, saves multiplier and adder resources, and is suitable for high real-time applications with limited resources.
Smart Images
Figure CN114020240B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of programmable device applications, and in particular relates to a device and method for implementing cross-clock domain time domain convolution calculation based on FPGA. Background Art
[0002] Convolution is widely used in engineering and mathematics. In statistics, a weighted moving average is a type of convolution. In probability theory, the probability density function of the sum of two independent statistical variables, X and Y, is the convolution of the probability density functions of X and Y. In electronic engineering and signal processing, the output of any linear system can be obtained by convolving the input signal with the system function (the system's impulse response).
[0003] The convolution operation can be viewed as a multiplication-addition operation. If the convolution coefficient is long, the FPGA will occupy a large number of multiplier and adder resources when performing multiplication-addition operations in the time domain, affecting resource allocation and optimization of the entire system. When performing time-domain convolution calculations on an FPGA, there is a high probability of encountering cross-clock domain issues, i.e., a mismatch between the input signal clock domain and the signal processing (convolution) clock domain. In this case, the two clock domains must be unified into one before performing the convolution calculation.
[0004] Currently, the mainstream method for implementing convolution calculations on FPGAs is time-domain convolution. Specifically, this involves first performing an FFT on the signal and the convolution coefficients, then performing multiplication in the frequency domain, and finally returning to the time domain through an ITTF calculation. This method offers the advantage of being unaffected by the clock domain and conserving multiplier resources. However, implementation requires back-and-forth conversions between the frequency and time domains, which consumes a significant amount of time. This ultimately results in high latency and poor real-time performance. In applications where real-time performance is crucial, frequency-domain convolution methods often struggle to meet practical requirements.
[0005] In addition, FPGA time domain convolution calculation has the problem of occupying more multiplier and adder resources. Summary of the Invention
[0006] To address the high latency and low real-time performance issues of existing methods for implementing convolution calculations on FPGAs, this paper provides an FPGA-based time-domain convolution calculation device for cross-clock domains. This device can meet application requirements for high real-time performance and minimal output latency, while also consuming minimal resources.
[0007] The present invention is achieved through the following technical solutions:
[0008] A time domain convolution calculation device for implementing cross-clock domains based on FPGA, including RAM_coef, FIFO_coef and FIFO_conv implemented based on FPGA;
[0009] RAM_coef is the RAM that stores the convolution coefficients in advance;
[0010] FIFO_coef is the cache FIFO for storing convolution coefficients, with a total of (M-1);
[0011] FIFO_conv is a cache FIFO for storing the intermediate results of multiplication and addition operations, with a total of M;
[0012] RAM_coef and (M-1) FIFO_coefs constitute a pipeline structure that is transmitted sequentially according to the signal timing, and RAM_coef and (M-1) FIFO_coefs correspond one-to-one to M multipliers, respectively, and are used to provide corresponding convolution coefficients for the timing signals of the M multipliers;
[0013] There are M adders corresponding to M multipliers one by one. The M multipliers and their corresponding adders work in parallel. Before the next signal arrives, (M-1) intermediate results of multiplication and addition operations will be generated. M FIFO_convs are used to store the intermediate results of the multiplication and addition operations of the M signals respectively.
[0014] Preferably, the device of the present invention further comprises an input signal interface Sig_din;
[0015] The input signal interface Sig_din is used to receive a timing signal and distribute it to a corresponding multiplier.
[0016] Preferably, in the present invention, when the Xth signal is input and 1≤X≤M, the Xth signal is input into the Xth multiplier for operation;
[0017] When the X-th signal is input and M<X≤2M, all multiplication operations of the (XM)-th signal are just completed. At this time, the (XM)-th multiplier is just in an idle state and can be used to calculate the multiplication of the X-th signal;
[0018] This cycle repeats to achieve the reuse of M multipliers.
[0019] Preferably, the multiplication operation result output by the X-th multiplier of the present invention is added to the intermediate result of the multiplication and addition operation stored in the (X-1)-th FIFO_conv to obtain the intermediate result of the multiplication and addition operation of the X-th adder, and the first signal of the intermediate result of the multiplication and addition operation of the X-th adder is output as the convolution calculation result, and the remaining signals are stored in the X-th FIFO_conv(X), where 1≤X≤M.
[0020] Preferably, in the present invention, when the Xth signal is input and 1≤X≤M, the Xth signal is multiplied and added using the Xth multiplier and the Xth adder to obtain a multiplication and addition result of the Xth signal, and the first signal of the multiplication and addition result of the Xth signal is output as the convolution calculation result, and the remaining signals are stored in the Xth FIFO_conv(X);
[0021] When the X-th signal is input and M<X≤2M, the multiplication and addition operation of the (XM)-th signal is just completed. At this time, the data in the (XM)-th FIFO_conv(X) is read out and used to store the multiplication and addition operation result of the X-th signal;
[0022] This cycle repeats to achieve the multiplexing of M adders and FIFO_conv.
[0023] Preferably, the length of (M-1) FIFO_coef of the present invention is greater than N;
[0024] N is the ratio of the signal processing clock frequency to the input signal clock frequency.
[0025] Preferably, the method of the present invention comprises:
[0026] When a signal is input, the convolution coefficients are read out from RAM_coef in a cyclic manner, and the read convolution coefficients are multiplied with the 1st, M+1, 2M+1, ... signals to obtain the intermediate result mult1, and the coefficients are written into FIFO_coef(1).
[0027] After N clocks, the 2nd, M+2, 2M+2, ... signals are input, and the coefficients are read from FIFO_coef(1). The coefficients are multiplied by the 2nd, M+2, 2M+2, ... signals to obtain the intermediate result mult2, and the coefficients are written to FIFO_coef(2).
[0028] The process is repeated recursively until the coefficient is read out from the last level FIFO_coef(M-1), and the coefficient is multiplied with the Mth, 2Mth, 3Mth, ... signals to obtain the intermediate result multM.
[0029] Preferably, the method of the present invention further comprises:
[0030] The multiplication result of the first signal is added to the output of the M-th FIFO_conv(M) to obtain the intermediate result of the multiplication and addition operation of the first signal conv_tmp(1). The first signal in conv_tmp(1) is output as the convolution calculation result, and the remaining signals are stored in the first FIFO_conv(1).
[0031] The multiplication result of the second signal is added to the output of the first FIFO_conv(1) to obtain the intermediate result of the multiplication and addition operation of the second signal, conv_tmp(2). The first signal in conv_tmp(2) is output as the convolution calculation result, and the remaining signals are stored in the second FIFO_conv(2).
[0032] Recursively backward, the multiplication result of the Mth signal is added to the output of the (M-1)th FIFO_conv(1), and the intermediate result conv_tmp(M) of the multiplication and addition operation of the Mth signal is obtained. The first signal in conv_tmp(M) is output as the convolution calculation result, and the remaining signals are stored in the Mth FIFO_conv(M);
[0033] When the (M+1)th signal is input, M*N clocks have passed, and the multiplication and addition operation of the first signal has just been completed. The data in FIFO_conv(1) is read out and used. At this time, the addition calculation of this signal reuses the adder used by the first signal, and the intermediate result is stored in the first FIFO_conv(1);
[0034] This cycle repeats to achieve the multiplexing of M adders and M FIFO_conv.
[0035] In a third aspect, the present invention proposes a real-time data processing system, which uses the FPGA-based time domain convolution calculation device for implementing cross-clock domains as described in the present invention to perform convolution calculations on time series signals.
[0036] In a fourth aspect, the present invention proposes a radar data processing system, which uses the FPGA-based time domain convolution calculation device for implementing cross-clock domains as described in the present invention to perform convolution calculation on radar signals.
[0037] The present invention has the following advantages and beneficial effects:
[0038] 1. Compared with convolution calculation in the frequency domain, the present invention can reduce delay and improve real-time performance.
[0039] 2. Compared with convolution calculation implemented in the time domain, the present invention can reduce resource consumption of multipliers, adders, etc.
[0040] 3. The present invention can be widely promoted and used in applications with high real-time processing requirements and limited resources, and is particularly suitable for scenarios such as radar system data processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:
[0042] Figure 1 This is a block diagram of the device principle of the present invention.
[0043] Figure 2 This is a timing diagram of the relationship between the input signal, convolution coefficient and clock of the present invention. DETAILED DESCRIPTION
[0044] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.
[0045] Example
[0046] This embodiment proposes a time-domain convolution computing device that implements cross-clock domains based on FPGA.
[0047] The convolution calculation principle is:
[0048]
[0049] In the formula, h[n] is the convolution coefficient and x[n] is the signal to be convolved. It can be seen from the formula:
[0050] 1) The convolution calculation process is mainly multiplication and addition calculations.
[0051] 2) Each signal to be convolved will be multiplied by all the coefficients.
[0052] 3) The current output value is related to the historical input value.
[0053] To maximize the reuse of multipliers and adders, the multiplication and addition operations for a single signal must be completed as quickly as possible. Once the multiplier or adder has completed calculations for one signal, it can be used to calculate other signals. To minimize the accumulation of intermediate calculation results, this embodiment employs a pipeline approach to design the entire calculation process, ensuring that the intermediate calculation results of the multipliers and adders remain in an "optimal state." (The so-called "optimal state" means that the current input signal only needs to complete a single multiplication calculation and an addition calculation with the current most recent result to obtain the current convolution result, without having to recalculate historical input multiplication and addition results.)
[0054] In this embodiment, if the signal processing (convolution) clock frequency is N times faster (N is a positive integer) than the input signal clock frequency, the number of convolution coefficients is M times N (M is a positive integer). If there are insufficient coefficients, zeros are added to the end. Because the signal processing clock is N times faster than the input signal clock, N coefficients can be read from a single input signal for multiplication and addition. The clock difference can be exploited to reuse multipliers and adders, thereby saving N times the number of multipliers and adders.
[0055] like Figure 1 As shown, the device of this embodiment includes RAM_coef, FIFO_coef and FIFO_conv implemented based on FPGA;
[0056] Among them, RAM_coef is the RAM that stores the convolution coefficient.
[0057] FIFO_coef is the cache FIFO for storing convolution coefficients, with a total of (M-1), that is, Figure 1 FIFO_coef(1), FIFO_coef(2), ..., FIFO_coef(M-1) shown in .
[0058] FIFO_conv is a cache FIFO for storing the multiplication and addition calculation results, with a total of M, namely Figure 1 FIFO_conv(1), FIFO_coef(2), ..., FIFO_coef(M) shown in FIG.
[0059] Figure 1 In the figure, Sig_din is the input signal interface for receiving timing signals; 1, 2, ...M, M+1, M+2... are the input signal numbers; mult1 to multM are the multiplication calculation results; conv_tmp is the intermediate multiplication and addition calculation result; FIFO_conv is the cache FIFO for storing the multiplication and addition calculation results.
[0060] RAM_coef and (M-1) FIFO_coefs constitute a structure (pipeline structure) that is transmitted sequentially according to the signal timing, and RAM_coef and (M-1) FIFO_coefs correspond one-to-one to M multipliers, respectively, and are used to provide corresponding convolution coefficients for the timing signals of the M multipliers;
[0061] M-way timing signals correspond one-to-one to M-way multipliers. The M-way multipliers and their corresponding adders work in parallel. Before the next signal arrives, (M-1) intermediate results will be generated. M FIFO_convs are used to store the intermediate results of the multiplication and addition operations of the M-way signals respectively.
[0062] The convolution coefficients are stored in a RAM, and (M-1) FIFOs are used to buffer the coefficients, allowing for simultaneous multiplication of M signals. When the Xth (M < X ≤ 2M)th signal is input, all multiplication operations for the (XM)th signal are complete. At this point, the (XM)th multiplier is idle and can be used to calculate the multiplication for the Xth signal. This repetitive cycle ensures continuous convolution calculations while maximizing multiplication reuse.
[0063] like Figure 2As shown, 1, 2, ...M, M+1, M+2... are the input signal numbers, and each signal needs to be multiplied and added M*N times. Figure 2 As can be seen in the figure, when the M+1th signal is input, the multiplication and addition operation of the first signal has just completed after M*N clocks. At this point, the multiplier and adder used by the first signal are idle and can be reused by the M+1th signal. Similarly, M multipliers and adders can be reused, saving N times the multiplier and adder resources.
[0064] This embodiment is based on Figure 1 The device architecture shown performs convolution calculations, and the specific process includes:
[0065] Before the signal arrives, the convolution coefficient is first stored in RAM_coef, and (M-1) FIFO_coefs with a length greater than N are defined to cache the convolution coefficient.
[0066] When a signal is input, the convolution coefficients pre-stored in RAM_coef will be read out from RAM_coef in sequence, and the read coefficients will be multiplied with the 1st, M+1, 2M+1... signals to obtain the intermediate result mult1, and the coefficients will be written into FIFO_coef(1) at the same time.
[0067] After N clocks, the 2nd, M+2, 2M+2, ... signals are input, and the coefficients are read from FIFO_coef(1). The read coefficients are multiplied with the 2nd, M+2, 2M+2, ... signals to obtain the intermediate result mult2, and the coefficients are written to FIFO_coef(2).
[0068] The process is repeated recursively until the coefficient is read out from the last level FIFO_coef(M-1), and the coefficient is multiplied with the Mth, 2Mth, 3Mth, ... signals to obtain the intermediate result multM.
[0069] During the convolution calculation, the output of the current signal is the multiplication result of the current signal plus the multiplication results of the previous N_coef-1 signals (N_coef is the number of convolution coefficients). Because the signal processing clock is faster than the signal input clock and there are M multipliers operating at the same time, (M-1) intermediate results will be generated before the next signal arrives. Therefore, M FIFOs are required to store the intermediate results of the multiplication and addition operations.
[0070] The multiplication result multX of the Xth signal is added to the multiplication and addition result of the (X-1)th signal to obtain the intermediate result conv_tmp(X). The first signal in conv_tmp(X) is output as the convolution calculation result, and the remaining signals are stored in FIFO_conv(X).
[0071] Specifically:
[0072] When X=1, the multiplication result mult1 of the first signal is added to the output of FIFO_conv(M) (all zeros), and the intermediate result conv_tmp(1) is obtained. The first signal in conv_tmp(1) is output as the convolution calculation result, and the remaining signals are stored in FIFO_conv(1).
[0073] When X=2, the multiplication result mult2 of the second signal is added to the multiplication and addition result of the first signal (i.e., the output of FIFO_conv(1)) to obtain the intermediate result conv_tmp(2). The first signal in conv_tmp(2) is output as the convolution calculation result, and the remaining signals are written to FIFO_conv(2).
[0074] Recursively backward, when X=M, the multiplication result multM of the Mth signal is added to the multiplication and addition result of the (M-1)th signal (that is, the output of FIFO_conv(M-1)) to obtain the intermediate result conv_tmp(M). The first signal in conv_tmp(M) is output as the convolution calculation result, and the remaining signals are written to FIFO_conv(M).
[0075] When X = M + 1, M*N clocks have passed, and the multiplication and addition operation of the first signal has just completed. The data in FIFO_conv(1) (the intermediate result of the first signal) has also been read out and used. At this time, the addition calculation of this signal can reuse the adder used for the first signal, and the result can also be stored in FIFO_conv(1). This cycle repeats, realizing the reuse of both the adder and the FIFO, greatly improving the utilization efficiency of the internal resources of the FPGA.
[0076] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A time-domain convolution computing device for implementing cross-clock domains based on FPGA, characterized in that: Including RAM_coef, FIFO_coef and FIFO_conv based on FPGA implementation; RAM_coef is the RAM that stores the convolution coefficients in advance; FIFO_coef is the cache FIFO for storing convolution coefficients, with a total of M-1; FIFO_conv is a cache FIFO that stores the multiplication and addition calculation results; RAM_coef and M-1 FIFO_coefs form a pipeline structure that is transmitted in sequence according to the signal timing, and RAM_coef and M-1 FIFO_coefs correspond one-to-one to M multipliers, respectively, and are used to provide corresponding convolution coefficients for the timing signals of the M multipliers; The M adders correspond to the M multipliers one by one. The M multipliers and their corresponding adders work in parallel. Before the next signal arrives, M-1 intermediate results of multiplication and addition operations will be generated. M FIFO_conv are used to store the intermediate results of the multiplication and addition operations of the M signals respectively. The length of M-1 FIFO_coef is greater than N; N is the ratio of the signal processing clock frequency to the input signal clock frequency; The calculation process of the time domain convolution calculation device includes: When a signal is input, the convolution coefficients are read out from RAM_coef in a cyclic manner, and the read convolution coefficients are multiplied with the 1st, M+1, 2M+1, ... signals to obtain the intermediate result mult1, and the coefficients are written into FIFO_coef(1). After N clocks, the 2nd, M+2, 2M+2, ... signals are input, and the coefficients are read from FIFO_coef(1). The coefficients are multiplied by the 2nd, M+2, 2M+2, ... signals to obtain the intermediate result mult2, and the coefficients are written to FIFO_coef(2). Recursively proceed backward until the coefficient is read from the last level FIFO_coef(M-1), and the read coefficient is multiplied with the Mth, 2Mth, 3Mth... signals to obtain the intermediate result multM; The multiplication result of the first signal is added to the output of the M-th FIFO_conv(M) to obtain the intermediate result of the multiplication and addition operation of the first signal conv_tmp(1). The first signal in conv_tmp(1) is output as the convolution calculation result, and the remaining signals are stored in the first FIFO_conv(1). The multiplication result of the second signal is added to the output of the first FIFO_conv(1) to obtain the intermediate result of the multiplication and addition operation of the second signal, conv_tmp(2). The first signal in conv_tmp(2) is output as the convolution calculation result, and the remaining signals are stored in the second FIFO_conv(2). Recursively backward, the multiplication result of the Mth signal is added to the output of the M-1th FIFO_conv(1) to obtain the intermediate result conv_tmp(M) of the multiplication and addition operation of the Mth signal. The first signal in conv_tmp(M) is output as the convolution calculation result, and the remaining signals are stored in the Mth FIFO_conv(M). When the M+1th signal is input, M*N clocks have passed, and the multiplication and addition operation of the first signal has just been completed. The data in FIFO_conv(1) is read out and used. At this time, the addition calculation of this signal reuses the adder used by the first signal, and the intermediate result is stored in the first FIFO_conv(1); This cycle repeats to achieve the multiplexing of M adders and M FIFO_conv.
2. The device for implementing cross-clock domain time domain convolution calculation based on FPGA according to claim 1, characterized in that: It also includes an input signal interface Sig_din; The input signal interface Sig_din is used to receive a timing signal and distribute it to a corresponding multiplier.
3. The device for implementing cross-clock domain time domain convolution calculation based on FPGA according to claim 1, characterized in that: When the Xth signal is input and 1≤X≤M, the Xth signal is input to the Xth multiplier for operation; When the X-th signal is input and M<X≤2M, all multiplication operations of the XM-th signal are just completed. At this time, the XM-th multiplier is just in an idle state and can be used to calculate the multiplication of the X-th signal; This cycle repeats to achieve the reuse of M multipliers.
4. The device for implementing cross-clock domain time domain convolution calculation based on FPGA according to claim 1, characterized in that: The multiplication result output by the X-th multiplier is added to the intermediate result of the multiplication-addition operation stored in the X-1-th FIFO_conv to obtain the intermediate result of the multiplication-addition operation of the X-th adder. The first signal of the intermediate result of the multiplication-addition operation of the X-th adder is output as the convolution calculation result, and the remaining signals are stored in the X-th FIFO_conv(X), where 1≤X≤M.
5. The device for implementing cross-clock domain time domain convolution calculation based on FPGA according to claim 1, characterized in that: When the Xth signal is input and 1≤X≤M, the Xth signal is multiplied and added using the Xth multiplier and the Xth adder to obtain the multiplication and addition result of the Xth signal. The first signal of the multiplication and addition result of the Xth signal is output as the convolution calculation result, and the remaining signals are stored in the Xth FIFO_conv(X); When the X-th signal is input and M<X≤2M, the multiplication and addition operation of the XM-th signal is just completed. At this time, the data in the XM-th FIFO_conv(X) is read out and used to store the multiplication and addition operation result of the X-th signal; This cycle repeats to achieve the multiplexing of M adders and FIFO_conv.
6. A real-time data processing system, characterized in that: The time domain convolution calculation device for implementing cross-clock domain based on FPGA as described in any one of claims 1 to 5 is used to perform convolution calculation on the timing signal.
7. A radar data processing system, characterized in that: The radar signal is convolutionally calculated using the FPGA-based time domain convolution calculation device for implementing cross-clock domains as described in any one of claims 1 to 5.