Split-Gate Memory Array Structure and Operating Method

Abstract

The present invention discloses a split-gate memory array structure. The split-gate memory array structure forms a memory array by multiple storage units with the same structure in the X direction and the Y direction; the memory array is placed in a well; each of the storage units is a split-gate structure to form a selection transistor and a storage transistor; in the memory array, in the Y direction, every two adjacent storage units are connected in common source, that is, the selection transistors of every two adjacent storage units are connected in common source; after the two selection gates of two storage units adjacent in common source are short-circuited, they are connected to the selection transistor word line WL in the X direction; the storage gates of every two storage units adjacent in common source are respectively connected to the storage gate word lines WLSa and WLSb; the drains of all the storage transistors in the same column in the memory array are all connected to the bit line BL in the Y direction corresponding to this column. The present invention uses a split-gate structure memory array structure adjacent in common source, and the structure of the storage unit is more compact, effectively reducing the area of the storage unit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing processes, and particularly to a split-gate memory array structure. Background Art

[0002] With the rapid popularization of electronic products, flash memory has been rapidly promoted and popularized as the mainstream storage medium today, and its technology has also developed rapidly. Non-volatile memory (NVM) technology mainly includes floating gate technology and SONOS

[0003] (Silicon-Oxide-Nitride-Oxide-Silicon) technology in terms of storage media, and mainly includes single-gate (1-Transistor), split-gate, double-gate (2-Transistor) and other technologies in terms of structure. Flash has been increasingly widely used in various embedded electronic products such as financial IC cards and automotive electronics due to its advantages of long life, non-volatility, low price, and easy programming and erasing. Improving the storage integration density is beneficial to saving chip area and reducing manufacturing costs. With the development of mainstream process technologies and the urgent requirements for Flash devices, split-gate Flash based on the split-gate structure has received extensive attention. Compared with traditional Flash, split-gate flash memory, as a type of flash memory, has received more attention both in terms of single units and embedded products due to its high programming speed and the ability to completely avoid over-erasing. At present, split-gate flash memory has been widely used in products such as personal computers, digital devices, mobile terminals, and smart cards. This novel split-gate Flash performs excellently in terms of reliability and no over-erasing, and due to its compact structure, more storage units can be integrated in the same chip area, thus having a better optimization effect on capacity improvement. However, due to the huge increase in data volume in the current information age, further optimizing the memory structure to achieve higher capacity has always been the pursuit of the industry. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a split-gate memory array structure and its operation method, which adopts a split-gate structure, is more compact in structure, and simpler in operation.

[0005] To solve the above problems, a split-gate memory array structure described in the present invention

[0006] The split-gate memory array structure is composed of multiple storage units with the same structure, and is distributed in the X direction and the Y direction to form a storage array; the storage array is placed in a well; each of the storage units is a split-gate structure to form a selection transistor and a storage transistor, and includes a selection gate and a storage gate;

[0007] In the storage array, in the Y direction, every two adjacent memory cells are connected in common source, that is, the selection transistors of every two adjacent memory cells share a source region; after the two selection gates of two adjacent memory cells connected in common source are short-circuited, they are connected to the selection gate word line WL in the X direction; the storage gates of every two adjacent memory cells connected in common source are respectively connected to the storage gate word lines WLSa and WLSb.

[0008] The drains of all the memory transistors in the same column in the storage array are all connected to the bit line BL in the Y direction corresponding to that column.

[0009] Optionally, the split-gate structure in the memory cell forms a selection transistor and a memory transistor, and the selection transistor and the memory transistor share a channel, omitting the intermediate source / drain region; in two adjacent memory cells connected in common source, the two selection transistors share a source region, reducing two contact holes led outwards; only one bit line BL is needed in the Y direction.

[0010] Optionally, the memory transistor is a SONOS memory transistor.

[0011] Optionally, when erasing, programming or reading data in the storage array, corresponding different voltage values are applied to the wells respectively.

[0012] For the operation method of the split-gate memory array structure, when erasing and programming data in the storage array, the page operation mode is adopted. When reading, a voltage is applied to the selection gate word line of the selected target memory cell, and the memory transistors of the memory cells adjacent to the selected target memory cell in common source are turned off. At this time, the current in the bit line of the target memory cell is read to obtain the state of the target memory cell.

[0013] Optionally, when erasing data, the voltage of the well is Vpos, the selection gate word line of the target memory cell that needs to be erased is connected to the voltage Vpos, the storage gate word line of the target memory cell is connected to the voltage Vneg, the storage gate word lines and the selection gate word lines of all the other memory cells in the storage array are connected to the voltage Vpos, the storage transistor word line of the selected erased memory cells in the same row is connected to the voltage Vneg, and the storage transistor word lines of other memory cells are connected to the voltage Vpos.

[0014] Optionally, when reading data, the voltage of the well is Vgnd, the voltage Vpwr is applied to the select gate word line of the selected target memory cell, and the storage gate word line of the selected target memory cell is grounded to Vgnd. At the same time, the storage tube of the memory cell sharing the same source with the selected memory cell is turned off, and the current in the bit line of the selected target memory cell is read to obtain the state of the selected target memory cell. When reading, the select gate voltage of the row where the selected memory cell is located in the memory array is Vpwr, the select gate word line voltage and the storage gate word line voltage of the memory cells in the unselected rows are both Vgnd, the storage gate voltage of the selected target memory cell is Vgnd, the storage gate word line voltage of the memory cell sharing the same source with the selected memory cell is Vnegr, the bit line voltage of the column where the selected memory cell is located is Vgnd, and the bit lines of the other columns are in a floating state. At this time, the bit line current of the selected memory cell is read to obtain the state of the target memory cell.

[0015] Optionally, when programming the memory array, it is in the page operation mode. At this time, the well voltage is Vneg, the select gate word line voltages in the memory array are all Vneg, the word line voltage of the storage gate of the target memory cell is Vpos, and the word line voltage of the storage gate of the memory cells on the non-target rows is Vneg. The bit line voltages in the memory array are divided into two states: programming "1" and programming "0". When programming "1", the bit line voltage is Vneg, and when programming "0", the bit line voltage is Vbl.

[0016] Optionally, the voltage Vpos>Vbl>Vgnd=0>Vnegr>Vneg, and Vpwr>Vgnd.

[0017] Optionally, Vpos is 7V, Vneg is -4V, Vbl is 1.2V, Vpwr is 1.5V, Vnegr is -1.5V, and Vgnd=0V.

[0018] In the split-gate memory array structure of the present invention, the memory cell uses a split-gate structure. The select tubes of every two adjacent memory cells are connected in common source, and the select gates of the two memory cells adjacent in common source share one word line. Only one bit line is required in the Y direction of the memory cell, making the structure of the memory cell more compact, simplifying the entire memory array, and effectively reducing the area of the memory cell. The operation of the memory cell is also more simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of the split-gate memory array structure provided by the present invention.

[0020] Figure 2 is a schematic diagram of page erasure of the split-gate memory array of the present invention.

[0021] Figure 3 isFigure 2 Schematic diagram of the potential of each structure in the device cross-section during erasure of the shown memory cell.

[0022] Figure 4 It is a schematic diagram of programming the split-gate memory array of the present invention.

[0023] Figure 5 is Figure 4 Schematic diagram of the potential of each structure in the device cross-section during programming of the shown memory cell.

[0024] Figure 6 It is a schematic diagram of reading data from the split-gate memory array of the present invention.

[0025] Figure 7 is Figure 6 Schematic diagram of the potential of each structure in the device cross-section during reading of the shown memory cell.

[0026] Figure 8 It is an operation table of the split-gate memory array of the present invention. Detailed implementation manners

[0027] The following gives the detailed implementation manners of the present invention in conjunction with the accompanying drawings, and clearly and completely describes the technical solutions in the present invention. However, the present invention is not limited to the following implementation manners. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. According to the following description and the claims, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0028] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals throughout the drawings denote the same elements. It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0029] The split-gate memory array structure described in the present invention is as Figure 1 shown. In the figure, the memory cells in the array form a memory cell array in the X direction and the Y direction, that is, horizontally and vertically. For the sake of simplicity of illustration, only the memory cells A1, A2, B1, B2, C1, C2, D1, and D2 are shown in this figure. The other cells in the memory array are simple repetitive arrangements of the structures of these memory cells in the X direction and the Y direction. In the memory cell of the present invention, the storage tube and the selection tube adopt a split-gate structure, and the channels of the storage tube and the selection tube in one memory cell are directly connected, saving a source / drain region compared with traditional devices. As Figure 1In the array structure shown, there are storage units such as A1, A2, B1, B2, C1, C2... Taking the A1 storage unit and the B1 storage unit as an example, these two storage units are in the same column in the Y direction and belong to the structure of common-source adjacent. The so-called common-source means that the selection transistors of the A1 unit and the B1 unit share a source region, so that the A1 storage unit and the B1 storage unit are connected in series. The storage transistors of each common-source adjacent storage unit are connected to the same bit line BL1. Among them, the selection transistor of the A1 storage unit and the selection gate of the B1 storage unit are commonly connected to the same select word line WL1. The storage gate terminal of the A1 storage unit is the storage transistor control word line WLS1a, and the gate terminal of the storage transistor of the B1 unit is connected to the control word line WLS1b. Among all the storage units in the same row in the storage array, horizontally, for the two storage units A1 and A2, the storage gate of the A2 unit is connected to the storage gate of the A1 unit and is connected to the storage word line WLS1a. The selection gate of the A2 unit and the selection gate of the A1 unit, as well as the selection gates of the B1 and B2 units, are connected to the word line WL1. The A2 and B2 storage units are in another column, and the storage gates of the A2 and B2 storage units are connected to the bit line BL2. The connection methods of the C1, D1, C2, D2 storage units and other storage units not shown in the figure are the same as those of the A1, B1, A2, B2 units, and the entire memory is thus extended to form an array.

[0030] In every two common-source adjacent memory units, the two storage transistors are located on the outside, and the selection transistors are located at the center of the two adjacent storage units, which is beneficial to connecting the gates of the two selection transistors in parallel and leading them out. The entire structure has 2 fewer external contact holes in terms of leading out than the traditional structure. At the same time, only one BL line is required in the Y direction. The above structure is more compact than the traditional memory cell array, can significantly reduce the area of the memory, and has a higher capacity under the same area.

[0031] The operation method of the above memory array structure is as described later. Generally speaking, when reading, a voltage is applied to the WL of the selected cell, and the storage transistor adjacent to the selected cell in common-source is turned off. By reading the current in the BL, the state of the selected cell can be obtained.

[0032] Figure 8The table shown in illustrates the operation of such a memory array. 1) Erasing and writing are performed in page mode. The bits in the same row are erased and written simultaneously. Erasing results in a value of 0. Writing can be either writing a "1" or writing a "0". When writing a "1", Vneg is applied to the BL; when writing a "0", Vbl is applied to the BL. 2) During reading, the voltage of the select gate word line for the selected row is Vpwr, the voltage of the select gate word line for the non-selected rows is Vgnd, the voltage of the storage gate word line for the selected row is Vgnd, the voltage of the storage transistor symmetric to the selected row is Vnegr, the voltages of the storage transistors in the remaining non-selected rows and all BL voltages are Vgnd. The state stored in the target cell is obtained by reading the current of the selected column. Vpos > Vbl > Vgnd = 0 > Vnegr > Vneg, Vpwr > Vgnd. Vpwr is the voltage of the select gate word line during reading of the memory cell, and it only needs to be greater than the threshold voltage Vt of the select transistor. Specifically, Figure 2 The figure shows the operation state diagram of the page erase operation of the memory array of the present invention. The page operation mode is a very common operation mode in the memory. The paged storage management method divides the address space of the user program into several fixed-size regions, called "pages" or "page frames". A typical page size is 1KB. When performing a page erase on the memory array, refer to Figure 8 the erase parameters in and Figure 2 . The voltages adopted in the embodiments of this specification are as follows. However, due to different manufacturing processes, there will be differences in specific voltages. At this time, the potential of the P-well is Vpos = 7V. At the same time, except that the voltage of the word line WLS1a of the rows where the storage cells A1 and A2 are located is -4V, the voltages of the word lines WL1, WLSb, WLS2a, WL2, and WLS2b corresponding to the select gates and storage gates of the remaining storage cells B1, B2, C1, C2, D1, and D2 are all Vpos = 7V. The page erase mode is achieved by applying corresponding voltages to these word lines and bit lines. Figure 3 This is a schematic diagram of the potentials of the cross-sectional structure of the storage cell, including the potentials of the select gate, storage gate, well region, and source-drain region. Since the voltage of the storage gate word line of the A1 cell is -4V and the voltage of the substrate well is 7V, there is a voltage difference of -11V between them, achieving erasure. For other cells, since the voltage between the gate and the substrate well is Vpos = 7V, the transistor state remains unchanged. That is, during erasure, there is a voltage difference of -11V between the gate and the substrate of the storage transistor, and the storage transistor channel will not be opened. It is only necessary to determine the voltage difference between the gate and the substrate.

[0033] As shown in Figure 4As shown, it is the operation state diagram of the programming mode of the memory array of the present invention. In the same page mode, the potential of the P-well is switched to Vneg = -4V, and a voltage Vpos = 7V is applied to the word line WLS1a of the storage gates of A1 and A2. The word line voltages of the selection transistors and storage transistors of the remaining memory cells are all switched to Vneg = -4V. The voltages on the bit lines BL1 and BL2 of the target memory cell are divided into two states according to whether it is programmed as "1" or programmed as "0". Combining Figure 5 with the cross-sectional structure potential diagram shown Figure 5 In the left side is the state of being programmed as "1". In the upper left is the state of the target memory cell and adjacent cells. In the lower left is the state of non-target memory cells (C1, D1). On the right side is the state of being programmed as "0". In the upper right is the state of the target memory cell and adjacent cells. In the lower right is the state of non-target memory cells (C1, D1). When programmed as "1", a voltage Vneg = -4V is connected to the bit lines BL1 and BL2. When programmed as "0", a voltage Vbl = 1.2V is connected to the bit lines BL1 and BL2. During programming, there is a positive pressure difference of 11V between the storage gate and the substrate well of the target memory cell, which is much larger than the threshold voltage of the storage transistor. Therefore, the channel of the storage gate is opened, and the voltage at the BL end will be transmitted to the channel. Therefore, P1 and P0 can be achieved by applying -4V or 1.2V at the BL end. Therefore, when programmed as "1", the word line voltage of the storage gate of the target cell is 7V, and the voltage of the bit line BL1 of the storage transistor of the A1 memory cell -4V will be transmitted to the channel. The pressure difference between the gate and the channel is +11V, which is a high-level state, and the programming state of the storage transistor is "1". When the bit line voltage BL1 is 1.2V, 1.2V will be transmitted to the channel, and the pressure difference between the gate and the channel is 5.8V, which is a low-level state, and the programming state of the storage transistor is "0".

[0034] When reading data, as Figure 6 shown, assume that it is necessary to read the storage state of the storage transistor of the A1 target memory cell. Figure 6 Combining Figure 7The cross-sectional structure potential diagram shown. At this time, the operation mode is that the well potential is zero. The storage unit adjacent to the A1 unit in common source is B1. The voltage of the storage gate word line WLS1a of the A1 unit is 0V, the voltage of the storage tube WLS1b of the B1 unit is the negative power supply -1.5V, the voltage of the select tube word line WL1 connected to the two units in common source is 1.5V, the bit line voltage BL1 of the column where the A1 unit is located is 0V, and the unit bit lines BL2 of other columns are in a floating state, and the select tube word lines and storage tube word lines of the storage units on other rows are all connected to 0V. At this time, the select tube word line voltages of the A1 and B1 units are 1.5V, the select tubes of the A1 and B1 units are turned on, and the storage tube of the B1 unit is in the off state due to the storage gate word line voltage of -1.5V. Therefore, the current can only flow from the source end through the select tube and the storage tube of A1 and flow out from BL1. When the storage tube of A1 is in the 0 state, the zero voltage can turn on the storage tube, and there is current flowing out in the path, and the state of the storage tube of the A1 unit can be read. When the storage tube of A1 is in the 1 state, the zero voltage cannot turn on the storage tube, and there is no current flowing out in the path. Thus, the storage state of the target unit A1 can be read out. If the storage state of the B1 unit is to be read out, it only needs to turn off the storage tube of the A1 unit and connect the storage tube of the B1 unit to zero voltage.

[0035] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A split-gate memory array structure device, characterized in that: The split-gate memory array structure is composed of a plurality of memory cells with the same structure, which are distributed in the X direction and the Y direction to form a memory array; The memory array is placed in a well; each memory cell is a split-gate structure forming a selection tube and a storage tube, including a selection gate and a storage gate; In the memory array, in the Y direction, every two adjacent memory cells are connected with a common source, that is, the select transistors of every two adjacent memory cells share a source region; the two select gates of the two adjacent memory cells with a common source are short-circuited and then connected to the select gate word line WL in the X direction; and the storage gates of every two adjacent memory cells with a common source are connected to storage gate word lines WLSa and WLSb respectively; The drains of all storage transistors in the same column of the storage array are connected to the bit line BL in the Y direction corresponding to the column; The split-gate structure in the memory cell forms a selection tube and a storage tube, which share a channel, eliminating the source / drain region in the middle. In two adjacent memory cells connected with a common source, the source region of the two selection tubes is shared, reducing the number of contact holes leading outward. Only one bit line BL is required in the Y direction.

2. The split-gate memory array structure device according to claim 1, wherein: The storage tube is a SONOS storage tube.

3. The split-gate memory array structure device according to claim 1, wherein: When erasing, programming or reading data from the memory array, corresponding different voltage values are applied to the wells.

4. The split-gate memory array structure device according to claim 1, wherein: The memory array adopts a page operation mode during data erasing and programming. During reading, the select gate word line of the selected target memory cell is pressurized, and the storage transistors of the memory cells adjacent to the selected target memory cell with a common source are turned off. At this time, the current in the bit line of the target memory cell is read to obtain the state of the target memory cell. When data is erased, the select gate word line of the target memory cell to be erased is connected to voltage Vpos, the storage gate word line of the target memory cell is connected to voltage Vneg, the storage gate word lines and select gate word lines of all other memory cells in the memory array are connected to voltage Vpos, the storage tube word line of the memory cell selected for erasure on the same row is connected to voltage Vneg, and the storage tube word lines of other memory cells are connected to voltage Vpos.

5. The split-gate memory array structure device according to claim 4, wherein: When reading data, the voltage of the well is Vgnd, and a voltage Vpwr is applied to the select gate word line of the selected target memory cell, and the storage gate word line of the selected target memory cell is grounded to Vgnd. At the same time, the storage transistors of the memory cells adjacent to the common source of the selected memory cell are turned off, and the current in the bit line of the selected target memory cell can be read to obtain the state of the selected target memory cell; when reading, the select gate voltage of the row where the selected memory cell in the memory array is located is Vpwr, and the select gate word line voltage and storage gate word line voltage of the memory cells in the non-selected rows are both Vgnd, the storage gate voltage of the selected target memory cell is Vgnd, and the storage gate word line voltage adjacent to the common source of the selected memory cell is Vgnd. The line voltage is Vnegr, the column bit line voltage of the selected memory cell is Vgnd, and the bit lines of the other columns are in a floating state. At this time, the state of the target memory cell can be obtained by reading the bit line current of the selected memory cell; when programming the memory array, it is a page operation mode, at this time the well voltage is Vneg, the selected gate word line voltages in the memory array are all Vneg, the word line voltage of the memory gate of the target memory cell is Vpos, and the word line voltage of the memory gate of the memory cell on the non-target row is Vneg; the bit line voltage in the memory array is divided into two states: programming "1" and programming "0": the bit line voltage is Vneg when programming "1", and the bit line voltage is Vbl when programming "0".

6. The split-gate memory array structure device according to claim 5, wherein: The voltages Vpos>Vbl>Vgnd=0>Vnegr>Vneg, Vpwr>Vgnd.

7. The split-gate memory array structure device according to claim 6, wherein: The Vpos is 7V, Vneg is -4V, Vbl is 1.2V, Vnegr is -1.5V, and Vpwr is 1.5V.

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