An ultra-low capacitance ESD protection device and preparation method thereof

Abstract

The embodiment of the present application provides an ultra-low capacitance ESD protection device and a preparation method thereof, the method comprising: forming an epitaxial layer of a first doping type on a substrate; forming a blocking oxide layer at a preset temperature on a surface of the epitaxial layer away from the substrate; the preset temperature is 1000°C to 1500°C; forming a well region of a second doping type on a side of the epitaxial layer away from the substrate; forming an injection region of a first doping type and a second doping type in the well region; isolating the oxide layer by low-pressure chemical vapor deposition on the surface of the blocking oxide layer away from the epitaxial layer; forming a contact hole at a position of the isolation oxide layer corresponding to the injection region, and depositing metal in the contact hole to lead out the anode or cathode of the protection device. The technical solution provided in the embodiment of the present application achieves the goal of ultra-low capacitance of the protection device.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically to an ultra-low capacitance ESD protection device and a method for preparing the same. Background Art

[0002] With the development of high-speed transmission interfaces, data transmission rates are getting higher and higher. In order to achieve faster transmission speeds, the control chip of the data transmission port must be designed and manufactured using more advanced processes, but this also causes the control chip's ability to withstand ESD (electrostatic discharge) attacks to decline rapidly. In addition, the popular data transmission port is a plug-and-play type, and the static electricity caused by this hot plug action is often the culprit for abnormal operation of electronic systems and even damage to port components. Therefore, additional ESD protection components must be used to protect the chip from static electricity to prevent ESD damage to the chip.

[0003] High-speed ports are widely used to transmit video and audio data. The stricter the data transmission fault tolerance, the lower the capacitance of the ESD protection device must be to ensure the integrity of the transmission signal. In the process of manufacturing ultra-low capacitance ESD protection semiconductor devices, one of the methods is to reduce the epitaxial layer concentration as much as possible, so that the PN junction depletion layer can be expanded more fully to reduce the junction capacitance. However, as the epitaxial concentration decreases, the positive charge defects in the oxide layer can easily attract negative charges on the silicon surface to form an N-type accumulation layer, which inhibits the decrease in surface concentration and limits the decrease in capacitance. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide an ultra-low capacitance ESD protection device and a method for preparing the same. The present application reduces the positive charge defects in the oxide layer, reduces the negative charge on the silicon surface, and reduces the silicon surface concentration through process adjustment and improvement, thereby achieving the goal of ultra-low capacitance.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing an ultra-low capacitance ESD protection device, comprising:

[0006] forming an epitaxial layer of a first doping type on the substrate;

[0007] Forming a blocking oxide layer on a surface of the epitaxial layer away from the substrate at a preset temperature; the preset temperature is 1000° C. to 1500° C.;

[0008] forming a well region of a second doping type on a side of the epitaxial layer facing away from the substrate;

[0009] forming an implantation region of a first doping type and a second doping type in the well region;

[0010] Depositing an isolation oxide layer on a surface of the barrier oxide layer away from the epitaxial layer by low pressure chemical vapor deposition;

[0011] A contact hole is formed at a position of the isolation oxide layer corresponding to the implantation region, and metal is deposited in the contact hole to lead out the anode or cathode of the protection device.

[0012] As a preferred embodiment of the present application, the preset temperature is 1200°C.

[0013] As a preferred embodiment of the present application, after forming the barrier oxide layer, the method further includes annealing the formed barrier oxide layer in a N2 or Ar atmosphere.

[0014] As a preferred embodiment of the present application, the injection region of each well region includes two first injection regions and one second injection region, the second injection region is arranged between the two first injection regions, and the injection regions of the first doping type and the second doping type are formed in the well region, including:

[0015] First, two second implantation regions are formed in the well region of the second doping type, and then a second implantation region is formed between the two implantation regions, wherein the implantation types of the first implantation region and the second implantation region are different.

[0016] As a preferred embodiment of the present application, the first implantation region and the second implantation region are heavy concentration implantation regions.

[0017] As a preferred embodiment of the present application, the first injection region is an N-type injection region, and the second injection region is a P-type injection region.

[0018] As a preferred embodiment of the present application, the first doping type is N-type, and the first doping type is P-type.

[0019] Compared with the prior art, the embodiment of the present application provides a method for preparing an ultra-low capacitance ESD protection device. In the general ESD device manufacturing process, there are two levels of oxide layers, first a relatively thin barrier oxide layer with a thickness of less than 100 nanometers, and then a thicker isolation oxide layer formed by a plasma enhanced chemical vapor deposition method of 1000 nanometers to 2000 nanometers. The thermal oxidation temperature of the ordinary barrier oxide layer is 800°C to 1000°C, and there are relatively high positive charge defects. The present application increases the oxidation temperature to about 1200°C, and after oxidation, the N 2 Or annealing in Ar atmosphere, effectively inhibiting the formation of oxygen vacancies, reducing the positive charge in the oxide layer, and isolating the oxide layer. Conventional process is plasma enhanced chemical vapor deposition. The C and H components in the reaction process are the cause of charge formation. Sufficient thermal processes will diffuse them to SiO 2 / Si interface, the present application replaces the isolation oxide layer process with a low-pressure chemical vapor deposition oxide layer, in which the C and H components are relatively less and the fixed charge is less during the reaction process. In this way, the oxide layer on the lightly doped silicon epitaxy is reduced to the minimum as much as possible, the negative charge attracted by the positive charge on the silicon surface becomes less, and the concentration on the N-type epitaxial surface is lower, so that the device can obtain a lower capacitance.

[0020] In a second aspect, an embodiment of the present application provides an ultra-low capacitance ESD protection device, and the protection device is prepared by the ultra-low capacitance ESD protection device preparation method described in any one of the first aspects.

[0021] The protection device includes a substrate, an epitaxial layer and a well region;

[0022] A blocking oxide layer is arranged on the surface of the epitaxial layer away from the substrate, and the well region is arranged on the side of the epitaxial layer away from the substrate; the well region is provided with an injection region of a first doping type and a second doping type, and an isolation oxide layer is arranged on the surface of the blocking oxide layer away from the epitaxial layer; an anode or cathode of the protection device is led out through a metal at the position of the injection region.

[0023] Compared with the prior art, the ultra-low capacitance ESD protection device provided in the second aspect has the same technical solution as that provided in the first aspect, and will not be described in detail herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Non-limiting and non-exhaustive embodiments of the present invention are described by way of example with reference to the following drawings, in which:

[0025] Figure 1 A schematic diagram of a process of an ultra-low capacitance ESD protection device and a preparation method thereof provided in an embodiment of the present application is shown;

[0026] Figures 2 to 7 A schematic diagram of the product structure formed in each process step of the embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and non-restrictive.

[0028] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] After research, the applicant found that the existing technology usually reduces the concentration of the epitaxial layer as much as possible to allow the PN junction depletion layer to expand more fully to reduce the junction capacitance. However, as the epitaxial concentration decreases, the positive charge defects in the oxide layer can easily attract negative charges on the silicon surface to form an N-type accumulation layer, which inhibits the decrease in surface concentration and limits the decrease in capacitance.

[0031] Therefore, the present application prepares a low-capacitance ESD protection device through the following scheme to solve the problems in the prior art.

[0032] like Figure 1 The present invention provides a method for preparing an ultra-low capacitance ESD protection device, comprising the following steps:

[0033] Step S01, forming an epitaxial layer of a first doping type on a substrate;

[0034] Step S02, forming a blocking oxide layer at a preset temperature on a surface of the epitaxial layer away from the substrate; the preset temperature is 1000° C. to 1500° C.;

[0035] Step S03, forming a well region of a second doping type on a side of the epitaxial layer facing away from the substrate;

[0036] Step S04, forming an implantation region of a first doping type and a second doping type in the well region;

[0037] Step S05, isolating an oxide layer by low pressure chemical vapor deposition on a surface of the barrier oxide layer away from the epitaxial layer;

[0038] Step S06, forming a contact hole at a position of the isolation oxide layer corresponding to the implantation region, and depositing metal in the contact hole to lead out the anode or cathode of the protection device.

[0039] refer to Figures 2 to 6 As shown, Figures 2 to 6 This is a schematic diagram of the structure during the preparation of the protection device;

[0040] refer to Figure 2 , execute step S01, first provide a substrate 01, the substrate 01 is a silicon substrate or a silicon germanium substrate, a silicon carbide substrate, etc., then the entire substrate 01 is formed into an epitaxial layer 02, in the embodiment of the present application, the epitaxial layer 02 is an N-type epitaxial layer, and finally obtain the following Figure 2 Schematic diagram of the structure shown.

[0041] refer to Figure 3 , executing step S02, forming a blocking oxide layer 03 on the surface of the epitaxial layer 02 away from the substrate 01, wherein the temperature for forming the blocking oxide layer is 1000°C to 1500°C, preferably 1200°C, but the prior art generally forms the blocking oxide layer at 800°C to 1000°C, and there are relatively high positive charge defects in the blocking oxide layer 03. The embodiment of the present application increases the oxidation temperature to about 1200°C, and after oxidation, the N 2 Or annealing in Ar atmosphere, effectively inhibiting the formation of oxygen vacancies and reducing the positive charge in the oxide layer. In the present application, the blocking oxide layer 03 is silicon oxide. The formation of the blocking oxide layer 03 is used to form a well region to play a blocking role. If the protection device of the present application is a bidirectional protection device, two symmetrical and identical well regions need to be formed.

[0042] refer to Figure 4 , execute step S03, form a well region 04 of a second doping type on the side of the epitaxial layer 02 away from the substrate 01. In the embodiment of the present application, the well region 04 is a P-type well region, so that a PN junction is formed between the well region 04 and the epitaxial layer 02. In the present application, there are two well regions 04, and the well region 04 is formed by ion implantation. The P-type semiconductor is also called a hole-type semiconductor. The P-type semiconductor is an impurity semiconductor with a hole concentration much greater than the free electron concentration. A trivalent element (such as boron) is doped into a pure silicon crystal to replace the position of silicon atoms in the lattice to form a P-type semiconductor. In a P-type semiconductor, holes are majority carriers and free electrons are minority carriers, and the main conduction is through holes. Holes are mainly provided by impurity atoms, and free electrons are formed by thermal excitation. The more impurities are doped, the higher the concentration of majority carriers (holes) and the stronger the conductivity.

[0043] refer to Figure 5, execute step S04, form a first injection region 05 and a second injection region 06 of the first doping type and the second doping type in the well region 04, the injection region of each well region 04 includes two first injection regions 05 and one second injection region 06, the second injection region 06 is arranged between the two first injection regions 05, in the embodiment of the present application, first form two first injection regions 05 in the well region 04 of the second doping type, and then form a second injection region 06 in the middle of the two first injection regions 05, wherein the injection types of the first injection region 05 and the second injection region 06 are different, wherein the first injection region 05 and the second injection region 06 are heavy concentration injection regions, in the embodiment of the present application, the first injection region 05 is an N-type injection region, the second injection region 06 is a P-type injection region, the first doping type is N-type, the second doping type is P-type, and the first injection region 05 and the second injection region 06 of each well region 04 form the anode or cathode of the device.

[0044] refer to Figure 6 , execute step S05, on the surface of the blocking oxide 03 away from the epitaxial layer 02, an isolation oxide layer 07 is deposited by low-pressure chemical vapor deposition; the isolation oxide layer is conventionally formed by plasma enhanced chemical vapor deposition. The C and H components in the reaction process are the cause of charge formation, and sufficient thermal processes will cause them to diffuse to SiO 2 / Si interface, the present application replaces the isolation oxide layer process with a low-pressure chemical vapor deposition isolation oxide layer, in which the C and H components are relatively less and the fixed charge is less during the reaction process, so that the oxide layer on the lightly doped silicon epitaxy is reduced to the minimum as much as possible, the positive charge attracts less negative charge on the silicon surface, and the N-type epitaxial surface concentration is lower, so that the device can obtain a lower capacitance.

[0045] refer to Figure 7 , executing step S06, etching a contact hole at a position corresponding to the implantation region of the isolation oxide layer 07, and depositing metal 08 in the contact hole to lead out the anode or cathode of the protection device.

[0046] The embodiment of the present application provides a method for preparing an ultra-low capacitance ESD protection device. In the general ESD device manufacturing process, there are two levels of oxide layers, first a relatively thin barrier oxide layer with a thickness of less than 100 nanometers, and then a thicker isolation oxide layer formed by a plasma enhanced chemical vapor deposition method of 1000 nanometers to 2000 nanometers. The thermal oxidation temperature of the ordinary barrier oxide layer is 800°C to 1000°C, and there are relatively high positive charge defects. The present application increases the oxidation temperature to about 1200°C, and after oxidation, the N 2Or annealing in Ar atmosphere, effectively inhibiting the formation of oxygen vacancies, reducing the positive charge in the oxide layer, and isolating the oxide layer. Conventional process is plasma enhanced chemical vapor deposition. The C and H components in the reaction process are the cause of charge formation. Sufficient thermal processes will diffuse them to SiO 2 / Si interface, the present application replaces the isolation oxide layer process with a low-pressure chemical vapor deposition oxide layer, in which the C and H components are relatively less and the fixed charge is less during the reaction process. In this way, the oxide layer on the lightly doped silicon epitaxy is reduced to the minimum as much as possible, the negative charge attracted by the positive charge on the silicon surface becomes less, and the concentration on the N-type epitaxial surface is lower, so that the device can obtain a lower capacitance.

[0047] Second, as Figure 7 As shown, an embodiment of the present application provides an ultra-low capacitance ESD protection device, and the protection device is prepared by the ultra-low capacitance ESD protection device preparation method described in any one of the first aspects.

[0048] The protection device comprises a substrate 01, an epitaxial layer 02 and a well region 04;

[0049] A blocking oxide layer 03 is provided on the surface of the epitaxial layer 02 away from the substrate 01, and the well region 04 is provided on the side of the epitaxial layer 02 away from the substrate; the well region 04 is provided with injection regions 05 and 06 of a first doping type and a second doping type, and an isolation oxide layer 07 is provided on the surface of the blocking oxide layer 03 away from the epitaxial layer 02; and the anode or cathode of the protection device is led out at the position of the injection regions 05 and 06 through a metal 08.

[0050] Compared with the prior art, the ultra-low capacitance ESD protection device provided in the second aspect has the same technical solution as that provided in the first aspect, and will not be described in detail herein.

[0051] The various technical features of the above implementation schemes can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above implementation schemes are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] Although the present invention has been described in conjunction with the embodiments, it will be appreciated by those skilled in the art that the above description and the accompanying drawings are exemplary and non-restrictive, and the present invention is not limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the present invention.

Claims

1. A method for preparing an ultra-low capacitance ESD protection device, It is characterized in that include, forming an epitaxial layer of a first doping type on the substrate; Forming a blocking oxide layer at a preset temperature on a surface of the epitaxial layer away from the substrate; the thickness of the blocking oxide layer is within 100 nanometers; forming a well region of a second doping type on a side of the epitaxial layer facing away from the substrate; forming an implantation region of a first doping type and a second doping type in the well region; An isolation oxide layer is deposited on the surface of the blocking oxide layer away from the epitaxial layer by low-pressure chemical vapor deposition, wherein the thickness of the isolation oxide layer is 1000 nanometers to 2000 nanometers; Forming a contact hole at a position of the isolation oxide layer corresponding to the implantation region, and depositing metal in the contact hole to lead out the anode or cathode of the protection device; The preset temperature is 1200°C; After forming the blocking oxide layer, the step includes: 2 Or annealing the formed barrier oxide layer in an Ar atmosphere.

2. A method for preparing an ultra-low capacitance ESD protection device as claimed in claim 1, It is characterized in that The implantation region of each well region includes two first implantation regions and one second implantation region, wherein the second implantation region is arranged between the two first implantation regions, and implantation regions of a first doping type and a second doping type are formed in the well region, including: First, two second implantation regions are formed in the well region of the second doping type, and then a second implantation region is formed between the two implantation regions, wherein the implantation types of the first implantation region and the second implantation region are different.

3. A method for preparing an ultra-low capacitance ESD protection device as claimed in claim 2, It is characterized in that The first implantation region and the second implantation region are heavy concentration implantation regions.

4. A method for preparing an ultra-low capacitance ESD protection device as claimed in claim 2, It is characterized in that The first implantation region is an N-type implantation region, and the second implantation region is a P-type implantation region.

5. A method for preparing an ultra-low capacitance ESD protection device as claimed in claim 1, It is characterized in that The first doping type is N type, and the second doping type is P type.

6. An ultra-low capacitance ESD protection device, It is characterized in that The protection device is prepared by the method for preparing an ultra-low capacitance ESD protection device according to any one of claims 1 to 5; The protection device includes a substrate, an epitaxial layer and a well region; A blocking oxide layer is arranged on the surface of the epitaxial layer away from the substrate, and the well region is arranged on the side of the epitaxial layer away from the substrate; the well region is provided with an injection region of a first doping type and a second doping type, and an isolation oxide layer is arranged on the surface of the blocking oxide layer away from the epitaxial layer; an anode or cathode of the protection device is led out through a metal at the position of the injection region; the thickness of the blocking oxide layer is within 100 nanometers, and the thickness of the isolation oxide layer is 1000 nanometers to 2000 nanometers.

7. An ultra-low capacitance ESD protection device as claimed in claim 6, It is characterized in that The implantation region of each well region includes two first implantation regions and one second implantation region, wherein the second implantation region is arranged between the two first implantation regions, and implantation regions of a first doping type and a second doping type are formed in the well region.

8. A method for preparing an ultra-low capacitance ESD protection device as claimed in claim 7, It is characterized in that The first injection region is an N-type injection region, the second injection region is a P-type injection region, the first doping type is N-type, and the second doping type is P-type.

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