A method for improving step height uniformity in a process

Abstract

The present invention provides a method for improving the uniformity of step height in a process, wherein an STI groove is provided between active regions; a first SiN layer is formed on the active region; an oxide is filled in the STI groove, and the oxide covers the first SiN layer on the active region; the STI groove filled with the oxide is annealed; a first chemical mechanical polishing is performed to flatten the oxide on the STI groove; a second SiN layer is formed on the flattened oxide; a second chemical mechanical polishing is performed on the second SiN layer to flatten its surface; the second SiN layer and the oxide are etched until the upper surface of the first SiN layer is exposed; the oxide is kept at the same height as the upper surface of the first SiN layer; an etching condition is selected in which the etching ratio of the oxide to the first SiN layer is greater than 1, and the oxide is etched to make the first SiN layer on multiple active regions have the same height. The present invention improves the inconsistency of step heights between different graphic structures through two STI CMP processes, so as to increase the window of the later process and improve the performance of the device.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving step height uniformity in a process. Background Art

[0002] At present, the uniformity of step heights formed by different structures in the process is mainly adjusted through STI planarization (CMP). Due to the characteristics of the CMP process, the Step Heights between different pattern structures (Pattern loading) will be different. In the subsequent process, the polysilicon falls on the active area and STI area of ​​different pattern structures, resulting in inconsistent heights, which in turn affects the electrical properties of the device.

[0003] Therefore, a new method needs to be proposed to solve the above problems. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the uniformity of step height in a process, so as to solve the problem in the prior art that the difference in step heights of different graphic structures affects device performance.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for improving the uniformity of step height in a process, which at least comprises:

[0006] Step 1, providing a wafer, wherein a plurality of active areas are provided on the wafer, and STI trenches are provided between the active areas; a first SiN layer is formed on the active areas; an oxide is filled in the STI trenches, and the oxide covers the first SiN layer on the active areas; and then the STI trenches filled with the oxide are annealed;

[0007] Step 2: performing a first chemical mechanical polishing to planarize the oxide on the STI trench;

[0008] Step 3, forming a second SiN layer on the planarized oxide;

[0009] Step 4: performing a second chemical mechanical polishing on the second SiN layer to planarize its surface;

[0010] Step 5, etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed; and keeping the oxide and the upper surface of the first SiN layer in the same height;

[0011] Step 6: Select an etching condition in which the etching ratio of the oxide to the first SiN layer is greater than 1, and etch the oxide so that the height of the first SiN layer on the multiple active regions is consistent.

[0012] Preferably, in step 1, before filling the STI trench with the oxide, a thin oxide layer is first formed on the STI trench and the active area; the thin oxide layer on the active area is located below the first SiN layer.

[0013] Preferably, in step five, the method for etching the second SiN layer and the oxide is dry etching.

[0014] Preferably, in the dry etching in step five, an etching ratio of the second SiN layer to the oxide is close to 1:1.

[0015] Preferably, the etching in step six is ​​dry etching.

[0016] As described above, the method of improving the uniformity of step height in the process of the present invention has the following beneficial effects: the present invention improves the inconsistency of step heights between different graphic structures through two STI CMP processes, so as to increase the window of the later process and improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram showing a structure in which STI trenches are provided between multiple active regions in the present invention;

[0018] Figure 2 It is a schematic diagram showing the structure after the first chemical mechanical polishing of the oxide in the present invention;

[0019] Figure 3 It is a schematic diagram of the structure after forming a second SiN layer on the oxide in the present invention;

[0020] Figure 4 It is a schematic diagram showing the structure after the second SiN layer is subjected to a second chemical mechanical polishing in the present invention;

[0021] Figure 5 It is a schematic diagram of the structure after etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed in the present invention;

[0022] Figure 6 It is a schematic diagram showing the structure of etching the oxide and the first SiN layer to make the first SiN layer on multiple active regions have the same height in the present invention;

[0023] Figure 7 Shown is a flow chart of the method for improving step height uniformity in a process according to the present invention. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0026] The present invention provides a method for improving the uniformity of step height in a process, such as Figure 7 As shown, Figure 7 The flowchart of the method for improving the uniformity of step height in the process of the present invention is shown, and the method at least comprises the following steps:

[0027] Step 1, providing a wafer, wherein a plurality of active regions are provided on the wafer, and STI trenches are provided between the active regions; a first SiN layer is formed on the active regions; an oxide is filled in the STI trenches, and the oxide covers the first SiN layer on the active regions; and then the STI trenches filled with the oxide are annealed; Figure 1 As shown, Figure 1 It is a schematic diagram of a structure in which STI grooves are provided between multiple active areas in the present invention. In step 1, a wafer is provided with multiple active areas 01, and STI grooves 03 are provided between the active areas 01; a first SiN layer 04 is formed on the active areas 01; an oxide 02 is filled in the STI grooves, and the oxide 02 covers the first SiN layer 04 on the active areas 01; and then the STI grooves 03 filled with the oxide 02 are annealed;

[0028] The present invention further comprises that in step 1 of this embodiment, before the STI trench 03 is filled with the oxide 02 , a thin oxide layer 05 is first formed on the STI trench 03 and the active area 01 ; the thin oxide layer 05 on the active area is located below the first SiN layer 04 .

[0029] Step 2: Perform a first chemical mechanical polishing to planarize the oxide on the STI trench; Figure 2 As shown, Figure 2The structure diagram after the first chemical mechanical polishing of the oxide in the present invention is shown. In step 2, the first chemical mechanical polishing (CMP) is performed to flatten the oxide 02 on the STI trench. The flattening in step 2 refers to the maximum possible flattening.

[0030] Step 3: forming a second SiN layer on the planarized oxide; Figure 3 As shown, Figure 3 It is a schematic diagram of the structure after forming the second SiN layer on the oxide in the present invention. In step three, the second SiN layer 06 is formed on the planarized oxide 02.

[0031] Step 4: Perform a second chemical mechanical polishing on the second SiN layer to flatten its surface; Figure 4 As shown, Figure 4 It is a schematic diagram of the structure after the second SiN layer is subjected to a second chemical mechanical polishing in the present invention. In step four, the second SiN layer 06 is subjected to a second chemical mechanical polishing to flatten its surface. The flattening in step four refers to the maximum possible flattening.

[0032] Step 5: Etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed; and keeping the oxide and the upper surface of the first SiN layer in the same height; Figure 5 As shown, Figure 5 The structure diagram after etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed is shown in the present invention. In step five, the second SiN layer and the oxide 02 are etched until the upper surface of the first SiN layer 04 is exposed; and the oxide 02 is kept at the same height as the upper surface of the first SiN layer 04.

[0033] Furthermore, in the present invention, in step five of this embodiment, the method for etching the second SiN layer and the oxide is dry etching.

[0034] Furthermore, in the dry etching in step five of this embodiment, the etching ratio of the second SiN layer to the oxide is close to 1:1.

[0035] Step 6: Select an etching condition in which the etching ratio of the oxide to the first SiN layer is greater than 1, and etch the oxide so that the first SiN layer on the multiple active regions has the same height. Figure 6 As shown, Figure 6 It is a schematic structural diagram showing that the oxide and the first SiN layer are etched to make the first SiN layer on multiple active regions highly consistent in the present invention.

[0036] Furthermore, in the present invention, the etching in step six of this embodiment is dry etching.

[0037] In summary, the present invention improves the inconsistency of step heights between different graphic structures through two STI CMP processes, so as to increase the window of later processes and improve the performance of devices. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0038] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving step height uniformity in a process, characterized in that: At least: Step 1, providing a wafer, wherein a plurality of active areas are provided on the wafer, and STI trenches are provided between the active areas; a first SiN layer is formed on the active areas; an oxide is filled in the STI trenches, and the oxide covers the first SiN layer on the active areas; and then the STI trenches filled with the oxide are annealed; Step 2: performing a first chemical mechanical polishing to planarize the oxide on the STI trench; Step 3, forming a second SiN layer on the planarized oxide; Step 4: performing a second chemical mechanical polishing on the second SiN layer to planarize its surface; Step 5, etching the second SiN layer and the oxide until the upper surface of the first SiN layer is exposed; and keeping the oxide and the upper surface of the first SiN layer in the same height; Step 6: Select an etching condition in which the etching ratio of the oxide to the first SiN layer is greater than 1, and etch the oxide so that the height of the first SiN layer on the multiple active regions is consistent.

2. The method for improving step height uniformity in a process according to claim 1, characterized in that: In step 1, before the STI trench is filled with the oxide, a thin oxide layer is first formed on the STI trench and the active area; the thin oxide layer on the active area is located below the first SiN layer.

3. The method for improving step height uniformity in a process according to claim 1, characterized in that: In step five, the method for etching the second SiN layer and the oxide is dry etching.

4. The method for improving step height uniformity in a process according to claim 3, characterized in that: In the dry etching in step five, the etching ratio of the second SiN layer to the oxide is close to 1:

1.

5. The method for improving step height uniformity in a process according to claim 1, characterized in that: The etching in step six is ​​dry etching.

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