Semiconductor device and method of forming the same

Abstract

The redistribution structure is made using a non-filler insulating material with a high shrinkage. Thus, good planarity can be achieved without the need to perform planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure. Embodiments of the present application also relate to a semiconductor device and a method of forming the same.

Description

Semiconductor devices and their fabrication methods Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, improvements in integration density come from iterative reductions in the smallest component size, allowing more components to be integrated into a given area. With the growing demand for miniaturized electronics, there has been a need for smaller and more innovative semiconductor die packaging technologies. An example of such packaging systems is stacked package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology typically allows for the production of semiconductor devices with enhanced functionality and small coverage areas on printed circuit boards (PCBs). Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device including: a redistribution structure, conductive components coupled to a substrate, the redistribution structure including: a first conductive layer, a first insulating layer located above the first conductive layer, the first insulating layer including a first unfilled insulating material, a second conductive layer located above the first insulating layer and coupled to the first conductive layer, and a second insulating layer located above the second conductive layer, the second insulating layer including a second unfilled insulating material; and a conductive connector electrically coupled to the redistribution structure.

[0004] Other embodiments of this application provide a semiconductor device including: a first redistribution structure, the first redistribution structure including: a first metallization pattern having a first thickness, a first insulating layer adjacent to the first metallization pattern, and a second metallization pattern adjacent to the first insulating layer, wherein the first insulating layer has a second thickness between the first metallization pattern and the second metallization pattern, wherein the second thickness is less than the first thickness; and a sealed die disposed above the first redistribution structure.

[0005] Further embodiments of this application provide a method for forming a semiconductor device, comprising: depositing a first metallization pattern on a substrate; depositing a first insulating layer over the first metallization pattern, the first insulating layer being unfilled; curing the first insulating layer such that the first insulating layer shrinks by less than 5%; forming a first opening through the first insulating layer to expose a portion of the first metallization pattern; depositing a second metallization pattern over the first insulating layer and in the first opening without flushing the first insulating layer; and depositing a second insulating layer over the second metallization pattern, the second insulating layer being unfilled. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1 to 19 illustrate intermediate processes in the formation of redistributed structures according to some embodiments.

[0008] Figures 20 to 30 illustrate intermediate processes in the formation of redistributed structures according to some embodiments.

[0009] Figures 31 to 37 illustrate intermediate processes in the formation of device stacks according to some embodiments.

[0010] Figure 38 shows a cross-sectional view of an integrated circuit die according to some embodiments.

[0011] Figures 39 to 53 illustrate intermediate processes in the formation of device stacks according to some embodiments.

[0012] Figures 54 to 59 illustrate intermediate processes in the formation of device stacks according to some embodiments.

[0013] Figures 60 and 61 illustrate device packages according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] According to some embodiments, a redistribution structure is disclosed, which is made of an unfilled insulating layer with a shrinkage rate to achieve a wavy upper profile, but within permissible limits, to avoid the need for planarization processes, such as planarization, of the insulating layer between each successive deposition of the layers of the redistribution structure. Therefore, the redistribution structure can be fabricated more simply and the insulating layer can be advantageously made thinner. Furthermore, the first metallization pattern of the redistribution structure can be made using a relatively thick metal to provide increased signal transmission and less attenuation. Some embodiments may utilize a ceramic carrier, such as an alumina carrier, to obtain good heat dissipation and electrical insulation properties. Embedded dies can be used for further functionality of the redistribution structure.

[0017] In Figures 1 through 19, a redistribution structure 100 is formed over a substrate 102 (see Figure 19). Briefly referring to Figure 19, the redistribution structure 100 is used to electrically couple conductive components 101 in the substrate 102 to other conductive components 101 in the substrate 102 and to conductive connectors 160. The redistribution structure 100 includes insulating layers 112, 122, 132, 142, and 152 and metallization patterns comprising conductive layers 108, 118, 128, 138, and 148. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The redistribution structure 100 is shown as an example with five metallization patterns. More or fewer dielectric layers and metallization patterns can be formed in the redistribution structure 100. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0018] Figure 1 shows a cross-sectional view of a substrate 102 of a semiconductor device. In some embodiments, the semiconductor device is a device wafer including active and / or passive devices. In some embodiments, the substrate 102 and the semiconductor device can be diced to form a plurality of chips / dies, and the view shown in Figure 1 may be one of such dies. In some embodiments, the substrate 102 may correspond to an interposer wafer which has no active devices and may include passive devices. In some embodiments, the substrate 102 may correspond to a package substrate strip which includes a coreless package substrate or a cored package substrate having a core therein. In some embodiments, the substrate 102 may correspond to a device wafer diced in a subsequent process. The redistribution structure embodiments of the present invention can also be applied to interposer wafers, package substrates, packages, etc.

[0019] In some embodiments, substrate 102 may correspond to logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), application processor (AP), microcontroller, application-specific integrated circuit (ASIC) die, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, high bandwidth memory (HBM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies, etc.), front-end dies (e.g., analog front-end (AFE) dies), etc., or combinations thereof.

[0020] In some embodiments, substrate 102 may be a semiconductor substrate and may include components formed on the top surface of substrate 102. In such embodiments, substrate 102 may be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., having p-type or n-type dopants) or undoped. Substrate 102 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 102 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. Shallow trench isolation (STI) regions (not shown separately) may be formed in substrate 102 to isolate active regions in substrate 102. Vias (not shown separately) may be formed to extend into or through substrate 102 (e.g., vias) and may be used for components on opposite sides of electrically coupled substrate 102.

[0021] In some embodiments, substrate 102 includes an integrated circuit device formed on the top surface of semiconductor substrate 102 and coupled to conductive component 101 of FIG. 19. The integrated circuit device may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit device are not shown here. In some embodiments, substrate 102 is used to form an interposer (which does not contain active devices), and substrate 102 may be a semiconductor substrate or a dielectric substrate.

[0022] A seed layer 106 is formed above the substrate 102. The seed layer 106 can be formed from any suitable material using appropriate processes. In some embodiments, the seed layer may include copper, aluminum, platinum, gold, palladium, titanium, tungsten, cobalt, and combinations thereof, and can be deposited by sputtering, CVD processes, PVD processes, and combinations thereof. The seed layer 106 can be deposited to a thickness between 0.2 μm and 0.6 μm or any suitable thickness.

[0023] In Figure 2, a mask layer 107 is formed and patterned on a seed layer 106 to expose portions of the seed layer 106. The mask layer 107 may be formed of a photosensitive material and patterned using an acceptable photolithography technique. In some embodiments, the mask layer 107 may be the bottom layer of a two- or three-layer photomask, wherein the upper layer of the mask is patterned using photolithography, and the layer below the mask layer 107 is subsequently patterned using etching. In some embodiments, a dual-patterning or multi-patterning process may be used. Typically, dual-patterning or multi-patterning processes combine photolithography and self-aligned processes, thereby allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate 102. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then become the mask layer 107.

[0024] In Figure 3, a conductive layer 108 is deposited on the exposed portion of the seed layer 106. In some embodiments, the conductive layer 108 is relatively thick, for example, compared to the thickness of the dielectric layer that separates the conductive layer 108 from another conductive layer formed in a subsequent process (described below). Furthermore, the conductive layer 108 is thicker than the subsequent metalline and can be used to wire signals with minimal signal loss, for example, in radio or analog signals. In some embodiments, the combined thickness of the seed layer 106 and the conductive layer 108 can be between about 10 μm and about 60 μm, but other thicknesses are conceivable and can be used. The conductive layer 108 can be formed from any suitable conductive material, including, for example, Co, Cu, Al, Ti, Ta, W, TiN, TaN, etc., or combinations thereof. The conductive layer 108 can be formed using any suitable technique, including PVD, ALD, CVD, variants thereof, etc., or combinations thereof. The conductive layer 108 is the first metallization layer of the redistributed structure.

[0025] Referring again to Figure 3, the mask layer 107 is removed using an etch-back or ashing technique. When removing the mask layer 107, any material that may be located on top of the conductive layer 108 is removed. Next, the exposed portions of the seed layer 106 are removed using an etching technique with a suitable etchant that is selective to the material of the seed layer 106.

[0026] In Figure 4, an insulating material 111 is deposited over the conductive layer 108. Figure 4 shows the insulating material 111 immediately after deposition (i.e., before curing). The insulating material 111 can be a varnish-type insulating material rather than a dry-type insulating material. The insulating material 111 can be a resin only, i.e., the resin may not contain any filler material. For example, the insulating material 111 can be a type of polymer called an additional polymer, such as epoxy resin, bismaleimide (BMI), polyphenylene ether (PPO), cyanate ester, acrylate, etc., or combinations thereof. The molecular weight of the insulating material can be less than 50,000 g / mol, such as between about 25,000 g / mol and 50,000 g / mol. The solids content of the resin can be greater than 40%, such as between about 40% and about 60%. The shrinkage rate of the insulating material 111 can be between about 95-99%, or in other words, the thickness of the finally cured insulating material 112 (see Figure 5) is 95-99% of the thickness of the uncured insulating material 111. Or, to put it another way, the shrinkage rate is very low (between 1% and 5%). The insulating material 111 can be deposited using any technique, such as spin coating, screen printing, spraying, or combinations thereof. The SAP process can also be used, examples of which are further described below, where subsequently formed vias and conductive layers are processed simultaneously. Due to the deposition technique, the upper surface of the immediately deposited insulating material 111 can have a high degree of planarity, i.e., it can be flat, as shown in Figure 4. Therefore, the thickness of the insulating material 111 varies due to the underlying conductive layer 108, being thicker between the elements of the conductive layer 108 (e.g., thickness 111t1) and thinner above the elements of the conductive layer 108 (e.g., thickness 111t2).

[0027] The insulating material 111 can be deposited with a thickness 111t1 between about 12 μm and about 120 μm (or a thickness 111t2 between about 2 μm and about 60 μm, or less than the thickness of the combination of the seed layer 106 and the conductive layer 108, such as between 30% and 100% or between 30% and 70% of the thickness of the combination of the seed layer 106 and the conductive layer 108). Because the shrinkage rate of the insulating material 111 is only 95% to 99%, the thickness difference caused by the conductive layer 108 is minimal as the insulating material 111 shrinks. Therefore, as the insulating material 111 shrinks after application, the combination of shrinkage rate, filler-free design, molecular weight, and solids content only provides small grooves appearing in the upper surface, which corresponds to sparse areas of the pattern of the conductive layer 108. Furthermore, because the insulating material 111 has an additional type of polymerization, no additional byproducts need to be removed during curing, and almost no weight loss of the insulating material 111 is observed.

[0028] Referring to Figure 5, after the insulating material 111 shrinks to its final form as insulating layer 112, the thickness 112t1 of the insulating material between the elements on the upper surface of the conductive layer 108 from the underlying substrate 102 to the insulating layer 112 can be between about 12 μm and about 114 μm. The thickness d1 (or 112t2) of the insulating material above the conductive layer 108 can be between about 2 μm and about 57 μm. In other words, the thickness d1 of the insulating layer 112 can be between about 25% and 100% of the combined thickness of the conductive layer 108 and the seed layer 106, such as between about 30% and 60%. In some embodiments, the thickness d1 of the insulating layer 112 can be less than half the thickness of the combined conductive layer 108 and the seed layer 106. The relatively thin insulating layer 112 above the thick metallic conductive layer 108 reduces transmission loss and increases power efficiency. The process shown advantageously provides an insulating layer 112 that is thinner than the underlying metallization layers (seed layer 106 and conductive layer 108) without requiring any additional planarization process.

[0029] When the insulating layer 112 fills the gaps laterally surrounding the conductive layer 108, as the film of the insulating material 111 shrinks to its final form within the insulating layer 112, a groove r1 can be formed in the upper surface of the insulating layer 112 due to the thickness difference between the insulating layer 112 and the elements of the conductive layer 108. The groove r1 can have a depth d2 determined by the difference between thicknesses 111t1 and 111t2. This difference is attributed to the metallization pattern (conductive layer 108 and seed layer 106). Therefore, the depth d2 is approximately the thickness of the metallization pattern multiplied by the shrinkage rate. Thus, the groove r1 can have a depth d2 between 1% and 5% of the combined thickness of the conductive layer 108 and seed layer 106, such as between 0.1 μm and about 3 μm. Taking into account the thickness d1 associated with the conductive layer 108 and seed layer 106, the groove r1 is also between 1% and 5% of the thickness d1.

[0030] Because the grooves r1 are only between 1% and 5% of the thickness d1, the planarization process can be omitted, saving time and resources. This results in the upper surface of the insulating layer 112 possibly having some slight waviness due to the grooves r1. Furthermore, if planarization were performed, traces would be left due to the planarization process. However, in this embodiment, no planarization traces are present on the insulating layer 112 (and subsequent insulating layers). These grooves r1 may propagate to subsequent layers to some extent as the subsequent conductive and insulating layers are formed; however, the propagation in each successive layer is likely less than the previous layer, as typically only a small fraction of the depth d2 of the grooves r1 will propagate. For example, as noted above, the depth d2 of the groove r1 is between 1% and 5% of the thickness of the combined conductive layer 108 and seed layer 106. In subsequent insulating layers, the propagation is reduced by a similar amount, depending on the material of the next insulating layer, such that any propagation of the grooves r1 is likely only about 1% to 35% of the depth d2. Therefore, acceptable planarity of subsequent layers can be maintained without requiring a planarization step. Acceptable planarity allows for reliable implementation of subsequent lithography techniques, for example, without focusing errors that could be caused by topographic issues.

[0031] In Figure 6, after the insulating layer 112 is formed, the insulating layer 112 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 114 in the insulating layer 112 to expose a portion of the conductive layer 108. Although the opening 114 is shown as tapered, the opening 114 can be rectangular, i.e., having vertical sidewalls.

[0032] In Figure 7, a metallization pattern including conductive elements is formed, such as a seed layer 116 and a conductive layer 118 extending along the main surface of the insulating layer 112 and extending through the insulating layer 112 to be physically and electrically coupled to the conductive layer 108. As an example of forming a metallization pattern, the seed layer 116 is formed over the insulating layer 112 and in an opening 114 extending through the insulating layer 112. In some embodiments, the seed layer 116 is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer 116 includes a titanium layer and a copper layer above the titanium layer. The seed layer 116 can be formed using, for example, PVD. Then, a photoresist is formed and patterned on the seed layer 116. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern including the conductive layer 118. The patterning forms an opening through the photoresist to expose the seed layer. A conductive layer 118 is then formed in the openings of the photoresist and on the exposed portions of the seed layer 116. The conductive layer 118 can be formed by plating (such as electroplating, electroless plating, etc.). The conductive layer 118 may include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive layer 118 and the lower portion of the seed layer 116 forms a metallized pattern. The photoresist and the portions of the seed layer on which no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example by using an acceptable etching process, such as wet etching or dry etching.

[0033] The thickness d3 of the combined seed layer 116 and conductive layer 118 can be between 15% and 30% of the thickness of conductive layer 108. In other words, the thickness d3 of the subsequent metallization pattern can be much thinner than the thickness of the first metallization pattern of the redistribution structure 100. In some embodiments, conductive layer 118 can be used to route signals that are not sensitive to attenuation, such as signals routed in conductive layer 108. The reduced thickness of conductive layer 118 compared to conductive layer 108 helps to reduce the overall device thickness and control heat dissipation. The reduced thickness of conductive layer 118 also helps to maintain good planarity in the subsequently formed insulating layer without requiring a planarization process, as described below. In some embodiments, the thickness d3 of the combined seed layer 116 and conductive layer 118 can be between about 3 μm and about 8 μm. The seed layer 116 and the conductive layer 118 follow the shape of the opening 114 such that a portion of the conductive layer 118 has an upper surface in the opening 114 that is immersed downwards into the opening 114 by a distance d4 up to approximately half the thickness of the insulating layer 112 above the conductive layer 108. In some embodiments, the distance d4 may be greater than the thickness d3, for example, between 0 and (d3 + (d1) / 2). In other embodiments, the distance d4 may be less than the thickness d3.

[0034] In Figure 8, an insulating layer 122 is deposited over the conductive layer 118 and a portion of the insulating layer 112. In some embodiments, the insulating layer 122 may be an additional polymer, such as that used in the insulating layer 112, and may be formed using materials and processes similar to those discussed above with respect to the insulating layer 112, but the material composition of the insulating layer 122 may be the same as or different from that of the insulating layer 112. In other embodiments, the insulating layer 122 may be a different type of polymer, such as a condensation polymer. The insulating layer 122 may be a varnish-type insulating material rather than a dry-type insulating material. The material may be resin only, i.e., the resin may not contain any filler material. For example, the material may be a condensation polymer, such as polyimide, polybenzoxazole (PBO), nylon, or combinations thereof. The molecular weight of the material of the insulating layer 122 may be less than 25,000 g / mol, such as between about 10,000 g / mol and 25,000 g / mol. The solids content of the resin may be greater than 45%, such as between about 45% and about 60%. The shrinkage rate of the material of insulating layer 122 can be between approximately 65% ​​and 80%, such as between 68% and 75%. In other words, insulating layer 122 may lose 20% to 35% of its material thickness during the curing process from the deposited state to the cured state. Insulating layer 122 can be deposited using any technique, such as spin coating, screen printing, spraying, or combinations thereof. Due to the deposition technique, the upper surface of the insulating material of insulating layer 122 immediately after deposition can have a high degree of planarity, i.e., it can be flat. Therefore, the thickness of the insulating material varies due to the underlying conductive layer 118 and the groove r1, being thicker between the elements of conductive layer 118 and thinner above the elements of conductive layer 118.

[0035] The insulating layer 122 can be deposited to a thickness between about 7 μm and about 25 μm. Because the material shrinkage rate of the insulating layer 122 is relatively high, as the material of the insulating layer 122 shrinks after application, the combination of shrinkage rate, filler-free design, molecular weight, and solids content tends to project attenuated versions of the underlying recesses and protrusions to form the wavy upper surface of the insulating layer 122. These attenuated projections are projected at a ratio of about one to three or about one to four, or in other words, for every 3 μm to 4 μm variation, about 1 μm is projected onto the surface of the insulating layer 122 (about 50%). For example, components such as the conductive layer 118 and / or the groove r1 can project onto the upper surface of the insulating layer 122. In other words, while the insulating material of the insulating layer 122 can be planar during deposition, after curing, the insulating layer 122 can have an upper surface that is somewhat conformal to the underlying components. However, the insulating layer 122 is relatively thin, for example, compared to the thickness of the conductive layer 118. Therefore, it is difficult to reliably planarize the upper surface of the insulating layer 122, for example, by planarization. Therefore, instead of planarizing the upper surface of the insulating layer 122 as indicated in the subsequent process described below, the subsequent metallization pattern is formed directly on the wavy upper surface of the insulating layer 122.

[0036] After the insulating material of insulating layer 122 shrinks to its final form as insulating layer 122, the thickness d5 of insulating layer 122 above conductive layer 118 can be between about 5 μm and about 7 μm. The process shown advantageously provides insulating layer 122 that is 100% to 200% of the thickness of the underlying metallization (seed layer 116 and conductive layer 118) without requiring any additional planarization process. A portion of insulating layer 122 may extend into a recess in conductive layer 118 according to a distance d4 (see FIG. 7), and therefore, in some embodiments, the bottom surface of insulating layer 122 may extend below the upper surface of insulating layer 112.

[0037] When the insulating layer 122 fills the gaps laterally surrounding the conductive layer 118, a groove r2 can be formed in the upper surface of the insulating layer 122. Furthermore, when the insulating layer 122 fills the depressions in the upper surface of the conductive layer 118 (e.g., according to distance d4), a groove r3 can be formed in the upper surface of the insulating layer 122. Grooves r2 and r3 can have a depth d6 between 10% and 35% of the thickness d5, such as between 1.0 μm and 3.0 μm. Grooves r2 and r3 can also have a depth d6 between 30% and 60% of the thickness of the conductive layer 118, such as between 1.0 μm and 3.0 μm. Because grooves r2 and r3 are between 10% and 35% of the thickness d5, a planarization process can be omitted, thus saving time and resources. This results in the upper surface of the insulating layer 122 having a waviness due to the grooves r2 and r3.

[0038] In Figure 9, after the insulating layer 122 is formed, the insulating layer 122 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 124 in the insulating layer 122 to expose a portion of the conductive layer 118. Although the opening 124 is shown as tapered, the opening 124 can be rectangular, i.e., having vertical sidewalls.

[0039] In Figure 10, a seed layer 126 and a conductive layer 128 may be formed in the opening 124 and extend along the upper surface of the insulating layer 122. The seed layer 126 and the conductive layer 128 may be formed using processes and materials similar to those discussed above with respect to the seed layer 116 and the conductive layer 118, which will not be repeated here. The seed layer 126 and the conductive layer 128 follow the shape of the opening 124, which allows a portion of the conductive layer 128 to have an upper surface in the opening 124 that extends downwards into the opening 124 by up to approximately half the thickness of the insulating layer 122 above the conductive layer 128. In some embodiments, the distance d8 may be greater than the thickness d7, for example, between 0 and (d7 + (d5) / 2). In other embodiments, the distance d8 may be less than the thickness d7.

[0040] In Figure 11, insulating layer 132 may be deposited over conductive layer 128 and insulating layer 122. In some embodiments, insulating layer 132 may be an additional polymer like insulating layer 112 and may be formed using materials and processes similar to those discussed above with respect to insulating layer 112, but the material composition of insulating layer 132 may be the same as or different from that of insulating layer 112. In other embodiments, insulating layer 132 may be a condensation polymer like insulating layer 122 and may be formed using materials and processes similar to those discussed above with respect to insulating layer 122, but the material composition of insulating layer 132 may be the same as or different from that of insulating layer 122.

[0041] In Figure 12, after the insulating layer 132 is formed, the insulating layer 132 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 134 in the insulating layer 132 to expose a portion of the conductive layer 128. Although the opening 134 is shown as tapered, the opening 134 can be rectangular, i.e., having vertical sidewalls.

[0042] In Figure 13, the seed layer 136 and the conductive layer 138 can be formed in the opening 134 and extend along the upper surface of the insulating layer 132. The seed layer 136 and the conductive layer 138 can be formed using processes and materials similar to those discussed above with respect to the seed layer 116 and the conductive layer 118.

[0043] In Figure 14, insulating layer 142 may be deposited over conductive layer 138 and insulating layer 132. In some embodiments, insulating layer 142 may be an additional polymer like insulating layer 112 and may be formed using materials and processes similar to those discussed above with respect to insulating layer 112, but the material composition of insulating layer 142 may be the same as or different from that of insulating layer 112. In other embodiments, insulating layer 142 may be a condensation polymer like insulating layer 122 and may be formed using materials and processes similar to those discussed above with respect to insulating layer 122, but the material composition of insulating layer 142 may be the same as or different from that of insulating layer 122.

[0044] In Figure 15, after the insulating layer 142 is formed, the insulating layer 142 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 144 in the insulating layer 142 to expose a portion of the conductive layer 138. Although the opening 144 is shown as tapered, the opening 144 can be rectangular, i.e., having vertical sidewalls.

[0045] In Figure 16, the seed layer 146 and the conductive layer 148 can be formed in the opening 144 and extend along the upper surface of the insulating layer 142. The seed layer 146 and the conductive layer 148 can be formed using processes and materials similar to those discussed above regarding the seed layer 116 and the conductive layer 118.

[0046] In Figure 17, insulating layer 152 may be deposited over conductive layer 148 and insulating layer 142. In some embodiments, insulating layer 152 may be an additional polymer like insulating layer 112 and may be formed using materials and processes similar to those discussed above with respect to insulating layer 112, but the material composition of insulating layer 152 may be the same as or different from that of insulating layer 112. In other embodiments, insulating layer 152 may be a condensation polymer like insulating layer 122 and may be formed using materials and processes similar to those discussed above with respect to insulating layer 122, but the material composition of insulating layer 152 may be the same as or different from that of insulating layer 122.

[0047] Insulating layer 152 is shown as the topmost insulating layer of redistribution structure 100. It should be understood that more or fewer metallization patterns can be used in redistribution structure 100 by repeating or omitting the above-described processes of patterning the insulating layer and depositing the seed layer and conductive layer. Redistribution structure 100 may be further processed as described below and as described in other embodiments to form connectors or other conductive components. The upper surface of insulating layer 152 may include grooves r4 corresponding to recesses in the upper surface, which are represented by the thickness of the conductive layer (e.g., a combination of seed layer 146 and conductive layer 148). Grooves r4 may also include recesses propagating from the recesses in the upper surface of the underlying insulating layer (e.g., insulating layer 142). The upper surface of insulating layer 152 may also include grooves r5 corresponding to areas of the underlying conductive layer (e.g., conductive layer 148) that extend through the underlying insulating layer (e.g., insulating layer 142) and contact another underlying conductive layer (e.g., conductive layer 138). These grooves are similar to grooves r2 and r3 discussed above. Therefore, the upper surface of the insulating layer 152 can be wavy due to the grooves r4 and r5.

[0048] In Figure 17, one measure of the waviness of the topmost insulating layer 152 is the distance d9 between the average peak 152u1 and the average valley 152u2 on the upper surface of insulating layer 152, which can be between approximately 3 μm and approximately 5 μm. The waviness of each layer of the redistribution structure is similar to that of the topmost insulating layer 152. Waviness in a redistribution structure is generally undesirable because it increases the likelihood of delamination, metallization short circuits and breaks, and pattern focusing errors. However, in the embodiments described herein, waviness is controlled by the choice of insulating layer material, the thickness of the underlying metallization pattern, and the deposition technique employed. Therefore, a different planarization process is not required after forming each insulating layer (e.g., insulating layers 112, 122, 132, 142, and 152). And because the planarization process is omitted, no additional material needs to be deposited for the insulating layers, which would require a margin for the planarization process. Therefore, it is advantageous that the thickness of the redistribution structure can be smaller and the additional step of the planarization process can be omitted.

[0049] In Figure 18, after the insulating layer 152 is formed, the insulating layer 152 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 154 in the insulating layer 152 to expose a portion of the conductive layer 148. Although the opening 154 is shown as tapered, the opening 154 can be rectangular, i.e., having vertical sidewalls.

[0050] In FIG. 19, a conductive connector 160 is formed in opening 154. In some embodiments, the conductive connector 160 may be formed on a bump under-metallization structure (UBM) (see, for example, UBM 394 in FIG. 51) first formed in opening 154. In such embodiments, the UBM may be formed for external connection to the front side of redistribution structure 100. The UBM may have a bump portion located on and extending along the main surface of insulating layer 152, and a via portion extending through insulating layer 152 to physically and electrically couple conductive layer 148. Thus, the UBM is electrically coupled to conductive component 101 in substrate 102 through various conductive layers 148, which conductive component 101 may be coupled to devices in substrate 102. The UBM may be formed of the same material as seed layer 146 and / or conductive layer 148. In some embodiments, the UBM has different dimensions (e.g., thickness) than the metallization patterns corresponding to conductive layers 108, 118, 128, 138, 148, etc.

[0051] The conductive connector 160 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. The conductive connector 160 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connector 160 is initially formed by evaporation, electroplating, printing, solder transfer, ball placement, solder paste, etc., to form a solder layer. Once the solder layer has been structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 160 includes metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal overlay is formed on the top of the metal pillar. The metallic coating may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by an electroplating process.

[0052] The resulting redistributed structure 100 can be used and combined in various packages and devices, as described below with respect to subsequent embodiments. The redistributed structure 100 advantageously uses an insulating material with extremely high shrinkage rates over a thick metallic conductive layer without requiring a planarization process to achieve a final insulating layer only 25% to 50% thicker than the thick metallic conductive layer, providing excellent signal transmission capabilities, reliability, and heat dissipation using a simplified process. The additional insulating layer of the redistributed structure 100 also exhibits good planarity due to its high shrinkage and low filler content.

[0053] Figures 20 through 29 illustrate intermediate stages in the formation of the redistribution structure 200 according to some embodiments. Figures 20 through 29 use reference numerals similar to those used in Figures 1 through 19, except that the leading '1' in the numerals '1xx' is replaced by the '2' in the corresponding numerals '2xx'. The same reference numerals indicate the same elements in Figures 20 through 29 unless otherwise stated. Briefly referring to Figure 29, the redistribution structure 200 is used to electrically couple conductive components 201 in substrate 202 to other conductive components 201 in substrate 202, and to electrically couple conductive components 201 in substrate 202 to conductive connectors 260. The redistribution structure 200 includes insulating layers 212, 222, and 232 and a metallization pattern comprising conductive layers 208, 218, and 228. The metallization pattern may also be referred to as a redistribution layer or redistribution line. The redistribution structure 200 is shown as an example with three layers of metallization pattern. More or fewer dielectric layers and metallization patterns can be formed in the redistribution structure 200. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0054] Figure 20 illustrates substrate 202, seed layer 206, and conductive layer 208, which can be formed using processes and materials similar to those discussed above regarding substrate 102, seed layer 106, and conductive layer 108, as shown in Figure 3. However, in Figure 20, insulating material 211 is formed from a different material than the insulating material 111 of insulating layer 112 shown in Figures 4 and 5. Specifically, insulating layer 212 can be formed using the condensation polymer described above for insulating layer 122. Insulating material 211 can be a varnish-type insulating material instead of a dry-type insulating material. Insulating material 211 can be a resin only, i.e., the resin may not contain any filler material. For example, insulating material 211 can be a condensation polymer, such as polyimide (PI), polybenzoxazine (PBO), nylon, or combinations thereof. The molecular weight of insulating material 211 can be less than 25,000 g / mol, such as between about 15,000 g / mol and 25,000 g / mol. The solids content of the resin can be greater than 40%, such as between about 40% and about 60%. The shrinkage rate of the insulating material 211 can be between about 65% and 80%, such as between about 68% and 75%. In other words, the insulating layer 122 may lose 20% to 35% of its material thickness during the curing process from the deposited state to the cured state. The insulating material 211 can be deposited using any technique, such as spin coating, screen printing, spraying, or combinations thereof. Due to the deposition technique, the upper surface of the immediately deposited insulating material 211 can have a high degree of planarity, i.e., it can be flat. Therefore, the thickness of the immediately deposited insulating material 211 varies due to the underlying conductive layer 208. The insulating material 211 can be deposited to a thickness between about 7 μm and about 25 μm greater than the thickness of the underlying conductive layer 208.

[0055] In Figure 21, insulating material 211 cures and shrinks into insulating layer 212. Because insulating material 211 will shrink by 20% to 35%, the combination of shrinkage rate, filler-free design, molecular weight, and solids content tends to project a decaying version of conductive layer 208 onto the upper surface of insulating layer 212 to form a wavy upper surface of insulating layer 212 as insulating material 211 shrinks after application to insulating layer 212. These decay projections are projected at a ratio of approximately one to three, or in other words, for every 3 μm change, approximately 1 μm is projected onto the surface of insulating layer 212 (approximately 50%). While the insulating material 211 can be flat during deposition, after curing, insulating layer 212 can have an upper surface that is somewhat conformal to the underlying component. Conductive layer 208 can be relatively thick, for example, approximately twice the thickness of insulating layer 212 above conductive layer 208. Therefore, shrinkage between portions of conductive layer 208 can be significant, including shrinkage to have an upper surface that descends below the level of the upper surface of conductive layer 208. Even if the upper surface of the insulating layer 212 does not descend to the level of the upper surface of the conductive layer, it will be difficult to reliably planarize the upper surface of the insulating layer 212 due to the lack of thickness margin of the insulating layer 212. Therefore, instead of planarizing the upper surface of the insulating layer 212 as indicated in the subsequent process described below, the subsequent metallization pattern is formed directly on the wavy upper surface of the insulating layer 212.

[0056] The thickness d11 of the insulating material above the conductive layer 208 can be between about 5 μm and about 10 μm. In other words, the thickness d11 of the insulating layer 212 can be between about 25% and 50% of the combined thickness of the conductive layer 208 and the seed layer 206. The relatively thin insulating layer 212 above the thick metallic conductive layer 208 reduces transmission loss and increases power efficiency. The illustrated process advantageously provides an insulating layer 212 that is 25% to 50% of the thickness of the underlying metallization (seed layer 106 and conductive layer 108) without requiring any additional planarization process. Furthermore, where planarization is performed, traces are left due to the planarization process. However, in this embodiment, no planarization traces are present on the insulating layer 212 (and subsequent insulating layers).

[0057] When the insulating layer 212 fills the spacer laterally surrounding the conductive layer 208, a groove r11 can be formed in the upper surface of the insulating layer 212. The groove r11 can have a depth d12 between 75% and 125% of the thickness d11, such as between 5 μm and about 12.5 μm. The groove r11 can also have a depth d12 between 25% and 65% of the thickness of the conductive layer 108, such as between 5 μm and about 13 μm.

[0058] Due to the thick metallization of the conductive layer 208 and the shrinkage rate of the insulating layer 212, the groove r11 results in a wavy top surface of the insulating layer 212. As noted above, the insulating material 211 of the insulating layer 212 can have a shrinkage rate between 65% and 80%, such as between 68% and 75%. Therefore, the amount of insulating material 211 surrounding the conductive layer 208 undergoes a greater difference in shrinkage than the insulating material 211 directly above the conductive layer 208. Ideally, the distance d11 should be kept thin to reduce transmission loss and increase power and heat dissipation efficiency.

[0059] Even though the top surface of insulating layer 212 is wavy, it is not planarized but allowed to remain wavy. Because subsequent conductive layers are deposited thinner, the waviness of insulating layer 212 can be preserved. The waviness of insulating layer 212 will propagate to subsequent layers of the redistribution structure; however, the distance between the high and low points of the subsequently formed insulating layers will attenuate, and the propagation will decrease with each subsequent layer.

[0060] In Figure 22, after the insulating layer 212 is formed, the insulating layer 212 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 214 in the insulating layer 212 to expose a portion of the conductive layer 208. Although the opening 214 is shown as tapered, the opening 214 can be rectangular, i.e., having vertical sidewalls.

[0061] In Figure 23, a metallization pattern including conductive elements is formed, such as a seed layer 216 and a conductive layer 218 extending along the main surface of the insulating layer 212 and extending through the insulating layer 212 to be physically and electrically coupled to the conductive layer 208. The seed layer 216 and the conductive layer 218 can be formed using processes and materials similar to those discussed above with respect to the seed layer 116 and the conductive layer 118 in Figure 7.

[0062] The thickness d13 of the combined seed layer 216 and conductive layer 218 can be between about 15% and 35% of the thickness of conductive layer 208. In other words, the thickness of the metallization pattern used for conductive layer 208 can be between 3 and 5 times thicker than the thickness d13. In some embodiments, conductive layer 218 can be used to route signals that are not sensitive to attenuation, such as signals routed in conductive layer 208. The reduced thickness compared to conductive layer 208 helps to reduce the overall device thickness and control heat dissipation. The reduced thickness of conductive layer 218 also helps to improve the planarity of the top layer of the redistributed structure without requiring planarization processes, as described below. In some embodiments, the thickness d13 of the combined seed layer 216 and conductive layer 218 can be between about 3 μm and about 8 μm. The seed layer 216 and the conductive layer 218 follow the shape of the opening 214 such that a portion of the conductive layer 218 has an upper surface in the opening 214 that extends downward into the opening 214 by a distance d14 up to approximately half the thickness of the insulating layer 212 above the conductive layer 218. In some embodiments, the distance d14 may be greater than the thickness d13, for example, between 0 and (d13 + (d11) / 12). In other embodiments, the distance d14 may be less than the thickness d13.

[0063] The metallization pattern also follows the contour of the wavy upper surface of the insulating layer 212. Each metallization pattern corresponding to the conductive layer 218 is thinner than distance d12 and has sufficient lateral spacing to prevent the conductive layers 218 from merging.

[0064] In Figure 24, an insulating layer 222 is deposited over the conductive layer 218 and a portion of the insulating layer 212. In some embodiments, the insulating layer 222 may be a condensation polymer such as the insulating layer 212 and may be formed using materials and processes discussed above with respect to the insulating layer 212, as shown in Figure 24; however, the material composition of the insulating layer 222 may differ from that of the insulating layer 212. In other embodiments, the insulating layer 222 may be an additional polymer similar to the insulating layer 112 and may be formed using materials and processes discussed above with respect to the insulating layer 112. Due to the deposition technique, the upper surface of the insulating material of the immediately deposited insulating layer 222 may have a high degree of planarity, i.e., it may be flat. Therefore, the thickness of the insulating material of the insulating layer 222 varies due to the wavy surfaces of the underlying conductive layer 218 and the insulating layer 212.

[0065] Insulating layer 222 can be deposited to a thickness between approximately 15 μm and approximately 70 μm. As the material of insulating layer 222 cures and shrinks, the underlying morphology will begin to be projected onto the surface of insulating layer 222. However, because the shrinkage rate of the material of insulating layer 222 is between 65% and 80%, such as between approximately 68% and 75%, the combination of shrinkage rate, filler-free design, molecular weight, and solids content will weaken the projection of the underlying layer as the material of insulating layer 222 shrinks after application (losing between 20% and 35% of the thickness during deposition). In other words, the morphology of the upper surface of the cured insulating layer 222 will be flatter than the corresponding morphology of the upper surface of insulating layer 212. Examples of this weakening effect are discussed below.

[0066] After the insulating material of insulating layer 222 shrinks to its final form as insulating layer 222, the thickness d15 of insulating layer 222 above conductive layer 218 can be between about 5 μm and about 20 μm. The process shown advantageously provides insulating layer 222 that is 50% to 200% of the thickness of the underlying metallization (seed layer 216 and conductive layer 218) without requiring any additional planarization process.

[0067] With the insulating layer 222 filling the gaps laterally surrounding the conductive layer 218, various grooves can be formed in the upper surface of the insulating layer 222. Groove r12 corresponds to a metallized region that corresponds to a conductive layer 218 serving as a via, extending through the insulating layer 222 and contacting the conductive layer 208. The depth d16 of groove r12 can correspond to the morphology of the underlying conductive layer 218, but can be reduced. For example, depth d16 can be about 20% to 40% of depth d14, such as between 1 μm and 4 μm. Groove r13 corresponds to a region of the insulating layer 222 having a waviness corresponding to the morphology below the insulating layer 212, without any conductive layer 218 between the top of the insulating layer 212 and the top of the insulating layer 222. Therefore, the depth d17 of groove r13 corresponds to the depth d12 of groove r11 in FIG. 21. However, due to the material of the insulating layer 222, the projection of groove r11 is reduced within the insulating layer 222. For example, depth d17 can be about 20% to 40% of depth d12, such as between 1 μm and 3 μm. Groove r14 corresponds to a region of insulating layer 222 having a waviness corresponding to the transition between the morphology below insulating layer 212 and the morphology below conductive layer 218. Therefore, depth d18 of groove r14 corresponds to the metallization thickness d13 of conductive layer 218. However, due to the material of insulating layer 222, the projection of the thickness of conductive layer 218 is reduced within insulating layer 222. For example, depth d18 can be about 20% to 40% of thickness d13, such as between 0.5 μm and 1.5 μm.

[0068] Even though the upper surface of insulation layer 222 is wavy, its waviness is less than that of insulation layer 212. Therefore, a different planarization process is not performed before depositing additional conductors, saving time and resources. This results in an upper surface of insulation layer 222 with waviness.

[0069] In Figure 25, after the insulating layer 222 is formed, the insulating layer 222 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 224 in the insulating layer 222 to expose a portion of the conductive layer 218. Although the opening 224 is shown as tapered, the opening 224 can be rectangular, i.e., having vertical sidewalls.

[0070] In Figure 26, the seed layer 226 and the conductive layer 228 can be formed in the opening 224 and extend along the upper surface of the insulating layer 222. The seed layer 226 and the conductive layer 228 can be formed using processes and materials similar to those discussed above with respect to the seed layer 216 and the conductive layer 218, which will not be repeated here. The seed layer 226 and the conductive layer 228 follow the shape of the opening 224, which allows a portion of the conductive layer 228 to have an upper surface in the opening 224 that is immersed downward into the opening 224 by a distance up to about half the thickness of the insulating layer 222 above the conductive layer 228, with dimensions similar to those discussed above with respect to Figure 23.

[0071] In Figure 27, insulating layer 232 is deposited over conductive layer 228 and a portion of insulating layer 222. In some embodiments, insulating layer 232 may be a condensation polymer such as insulating layer 212 and may be formed using materials and processes discussed above with respect to insulating layer 212, as shown in Figure 27; however, the material composition of insulating layer 232 may differ from that of insulating layer 212. In other embodiments, insulating layer 232 may be an additional polymer similar to insulating layer 112 and may be formed using those materials and processes discussed above with respect to insulating layer 112.

[0072] For reasons similar to those discussed above with respect to Figure 24, the projection of the morphology from the underlying insulating layer 222 and the metallization corresponding to the conductive layer 228 will be further attenuated in the upper surface of the insulating layer 232. Therefore, each successive layer of the redistribution structure 200 typically has a flatter upper surface than the preceding layer. For example, in some embodiments, the difference between the peak height and the valley of the insulating layer 212 is between about 1 μm and 16 μm, while in some embodiments, the difference between the peak height and the valley of the insulating layer 222 is between about 1 μm and 8 μm, and in some embodiments, the difference between the peak height and the valley of the insulating layer 232 is between about 0.5 μm and 4 μm, but other values ​​may also be considered.

[0073] Insulating layer 232 is shown as the topmost insulating layer of the redistribution structure 200. It should be understood that by repeating or omitting the above-described processes of patterning the insulating layer and depositing the seed layer and conductive layer, more or fewer metallization patterns can be used in the redistribution structure 200. The redistribution structure 200 may be further processed as described below and as described in other embodiments to form connectors or other conductive components. The upper surface of insulating layer 232 may include a groove r15 corresponding to a groove propagating from the underlying component. The groove r15 may include a groove formed due to the propagation of the thickness of the conductive layer (e.g., a combination of seed layer 226 and conductive layer 228; see, for example, groove r14 in FIG. 24); a groove formed due to the propagation of a groove in the upper surface of the underlying insulating layer (e.g., insulating layer 222; see, for example, groove r13 in FIG. 24); and a groove formed due to the propagation of a region of the underlying conductive layer (e.g., conductive layer 228; see, for example, groove r12 in FIG. 24) that extends through the underlying insulating layer (e.g., insulating layer 222) and contacts another underlying conductive layer (e.g., conductive layer 218). Due to the groove r15, the upper surface of the insulating layer 232 may be wavy.

[0074] In Figure 27, one measure of the waviness of the topmost insulating layer 232 is the distance d19 between the average peak 232u1 and the average valley 232u2 on the upper surface of insulating layer 232, which can be between approximately 3 μm and approximately 5 μm. The waviness of each layer of the redistribution structure is similar to that of the topmost insulating layer 232. Waviness in a redistribution structure is generally undesirable because it increases the likelihood of delamination, metallization short circuits and breaks, and pattern focusing errors. However, in the embodiments described herein, waviness is controlled by the choice of insulating layer material, the thickness of the underlying metallization pattern, and the deposition technique employed. Therefore, a different planarization process is not required after forming each insulating layer (e.g., insulating layers 212, 222, and 232). And because the planarization process is omitted, no additional material needs to be deposited for the insulating layers, which would require a margin for the planarization process. Therefore, it is advantageous that the thickness of the redistribution structure can be smaller and the additional step of the planarization process can be omitted.

[0075] In Figure 28, after the insulating layer 232 is formed, the insulating layer 232 is then photolithographically patterned using an acceptable photolithography technique, such as by exposure, development, and curing, to form an opening 234 in the insulating layer 232 to expose a portion of the conductive layer 228. Although the opening 234 is shown as tapered, the opening 234 can be rectangular, i.e., having vertical sidewalls.

[0076] In Figure 29, a conductive connector 260 is formed in opening 234. In some embodiments, the conductive connector 260 may be formed on a bump under-metallization structure (UBM) first formed in opening 254. In such an embodiment, the UBM may be formed for external connection to the front side of the redistribution structure 200. The UBM may have a bump portion located on and extending along the main surface of insulating layer 232, and a via portion extending through insulating layer 232 to physically and electrically couple conductive layer 228. Thus, the UBM is electrically coupled to conductive component 201 in substrate 202 through each conductive layer 228, which can be coupled to devices in substrate 202. The UBM may be formed of the same material as the seed layer 216 and conductive layer 218. In some embodiments, the UBM has a different dimension (e.g., thickness) than the metallization pattern corresponding to conductive layers 208, 218, and 228.

[0077] The conductive connector 260 can be formed using processes and materials similar to those discussed above with respect to the conductive connector of Figure 19.

[0078] The resulting redistributed structure 200 can be used and combined in various packages and devices, as described below with respect to subsequent embodiments. The redistributed structure 200 advantageously uses a high-shrinkage insulating material on the thick metal conductive layer to achieve a final insulating layer only 25% to 50% thicker than the thickness of the thick metal conductive layer, providing excellent signal transmission capability, reliability, and heat dissipation using a simplified process. In the various layers forming the redistributed structure, different planarization processes are omitted, allowing the upper surface to remain wavy. However, due to the choice of insulating material for the insulating layer, the waviness is reduced or attenuated in each successive layer of the redistributed structure, advantageously allowing the omission of planarization processes.

[0079] Figure 30 illustrates the redistribution structure 200 of Figure 29; however, in Figure 30, a passivation layer 265 is deposited over the insulating layer 232. The passivation layer 265 can provide a flat upper surface and eliminate residual waviness on the upper surface of the insulating layer 232. In some embodiments, the material and deposition process of the passivation layer 265 can be selected to make the upper surface flat without requiring a planarization process. In other embodiments, a planarization process, such as grinding or chemical mechanical polishing (CMP), is used on the passivation layer 265. The passivation layer 265 can be formed before or after the opening 234, and an additional opening corresponding to the opening 234 is formed through the passivation layer 265 before the formation of the conductive connector 260. Other embodiments may omit the passivation layer 265 and use a planarization process, such as grinding or CMP, before forming the opening for the conductive connector (e.g., opening 234) to make the upper surface of the final insulating layer (e.g., insulating layer 232) of the redistribution structure 200 flush.

[0080] Figures 31 through 53 show cross-sectional views of various intermediate stages in the formation of semiconductor devices, such as integrated fan-out (InFO) packages, for example, for MEMS devices. In Figure 31, package region 300A is shown. Package region 300A may be one of several package regions and represents a portion of the entire package region 300A. Also in Figure 31, a carrier 302 is provided. Carrier 302 may have openings pre-formed therein or openings may be formed in carrier 302 using any suitable process. The openings may extend entirely through carrier 302 (as shown) or may extend only through a portion of carrier 302. In some embodiments, carrier 302 may be a ceramic carrier. In some embodiments, carrier 302 is provided in wafer form. Optionally, carrier 302 may be provided in any other suitable form (e.g., panel form, chip form, or strip form, etc.), depending on process requirements. In some embodiments, the material of carrier 302 is selected to have high thermal conductivity to provide good heat dissipation. In some embodiments, the selected material of carrier 302 has a higher dielectric constant (or dielectric constant (Dk)) than conventional dielectric materials (e.g., a molding material with a Dk of about 3.3 or FR-4 with a Dk of about 4.5 to about 4.9). The selected material of carrier 302 may have a lower dissipation factor (or dielectric loss tangent, DO) than conventional dielectric materials (e.g., FR-4 with a Df of about 0.013 to about 0.020). The lower the dissipation factor of the material of carrier 302, the lower the signal transmission loss. In some embodiments, the material of carrier 302 is selected to have good handling properties to withstand the semiconductor structure formed thereon. The material of carrier 302 may be selected to have a coefficient of thermal expansion (CTE) that closely matches the CTE of the semiconductor chip (e.g., silicon material) to prevent the chip package subsequently formed on carrier 302 from cracking or separating under the influence of temperature changes.

[0081] For example, the material of the carrier 302 may include aluminum nitride (AlN), silicon carbide (SiC), aluminum oxide (Al2O3), silicon nitride (Si3N4), boron nitride (BN), zirconium oxide (ZrO2), or other suitable materials. In some embodiments using aluminum nitride wafers, the carrier 302 includes a dielectric constant (or dielectric constant; Dk) value in the range of about 7.7 to about 9.9, and a dielectric loss tangent (Df) in the range of about 0.003 at 10 GHz to about 0.00045 at 140 GHz. The carrier 302 may be customized to provide desired material properties, such as enhanced thermal conductivity, thereby facilitating heat dissipation. In some embodiments, the thermal conductivity of the carrier 302 may be in the range of about 60 W / mK to about 120 W / mK. In some embodiments, the thermal conductivity of the carrier 302 may be in the range of about 80 W / mK to about 180 W / mK or about 200 W / mK. In other embodiments, the thermal conductivity of the carrier 302 at room temperature is in the range of about 20 W / mK to about 150 W / mK. Optionally, the thermal conductivity of the carrier 302 at room temperature is in the range of about 3 W / mK to about 150 W / mK. Other suitable carrier materials with good dielectric and heat dissipation properties can be used.

[0082] In Figure 32, the back side of the carrier 302 can be attached to the strip 304 for easy handling. It should be understood that the cross-sectional views of the carrier 302 and the strip 304 shown represent only portions of the carrier 302 and the strip 304.

[0083] In Figures 33 to 35, a redistribution structure 100 is formed (Figure 35). In Figure 33, a seed layer 106 is formed. The seed layer 106 can be formed using processes and materials similar to those discussed above with respect to the seed layer of Figure 2. The seed layer 106 is nested within an opening in the carrier 302 and, in some embodiments, may extend along the strip 304. In Figure 34, a conductive layer 108 is formed on the seed layer 106, including within the opening in the carrier 302. The conductive layer 108 can be formed using processes and materials similar to those discussed above with respect to the conductive layer 108 of Figure 3. A portion of the conductive layer 108 forms a via 305 through the carrier 302. After the conductive layer is formed, the exposed portions of the seed layer 106 can be etched away using a suitable wet or dry etching process. As indicated in Figure 34, in some embodiments, the upper surface of the conductive layer 108 may have depressions formed therein, depending on the opening in the carrier 302.

[0084] In Figure 35, the remaining portion of the redistribution structure 100 can be formed using processes and materials similar to those discussed above with respect to Figures 4 through 17. In some embodiments, a portion of the insulating layer 122 may have a bottom surface that contacts the conductive layer 108, which is lower than the upper surface 112s of the insulating layer 112.

[0085] In Figure 36, the strip 304 is removed and the encapsulation region 300A is attached to the carrier 308 via a die attachment film 306 (such as a release layer). The carrier 308 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier 308 may be a wafer, thereby allowing multiple packages to be formed simultaneously on the carrier 308. The die attachment film 306 may be formed of a polymer-based material, which may be removed along with the carrier 308 from the above structure to be formed in subsequent steps. In some embodiments, the die attachment film 306 is a heat-release epoxy-based material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the die attachment film 306 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. The die attachment film 306 may be dispensed and cured as a liquid, may be a laminated film laminated onto the carrier 308, or may be the like. The top surface of the die attachment film 306 may be flush and may have a high degree of planarity.

[0086] In some embodiments, such as shown in FIG. 36, multiple encapsulation regions may be attached to a carrier 308. In some embodiments, corresponding layers of the multiple encapsulation regions may extend continuously to each other; for example, the carrier 302 of encapsulation region 300A may extend continuously to the carrier 302 of encapsulation region 300B, or in other words, the carrier 302 in encapsulation region 300A and the carrier 302 in encapsulation region 300B may be the same carrier. A similar correspondence occurs between each layer of encapsulation regions 300A and 300B. In other embodiments, encapsulation regions 300A and 300B may be spaced apart and may each be attached to a common carrier 308 via a die attachment film 306. In other words, in such an embodiment, the carrier 302 of encapsulation region 300A is a different carrier than the carrier 302 of encapsulation region 300B. Although two encapsulation regions 300A and 300B are shown, any suitable number of encapsulation regions may be used, including only one encapsulation region.

[0087] In Figure 37, the carrier 308 is flipped over, and either or a combination of both of the conductive via 312 (left side in package region 300B), the conductor 318 (right side in package region 300A), or both can be formed on the now upper side of the carrier 302. If the opening in the carrier 302 (see Figure 31) does not extend through the entire thickness of the carrier 302, a new opening can be formed in the now upper side of the carrier 302 to expose the via 305 of the conductive layer 108 and its associated seed layer 106. The illustrations in package region 300A and package region 300B show that the via portion 318v of the conductor 318 and / or the bottom via portion 312v of the conductive via 312 can extend downward through a portion of the carrier 302. In such an embodiment, as shown in the illustrations, the resulting conductor through the carrier 302 can have an hourglass shape.

[0088] The conductive via 312 can be formed by any suitable process, such as electroplating, electroless plating, etc. In some embodiments, a different seed layer (not shown) may be deposited first where the conductive via 312 will be formed, while in other embodiments, the conductive via 312 may use seed layer 106 as the seed layer, thereby reducing processing complexity. The conductive wire 318 can be formed by first depositing seed layer 316, then covering the portion of the seed layer to be depatched with a mask, and then using any suitable deposition process, such as electroplating, electroless plating, CVD, PVD, etc., or combinations thereof. The mask is then removed and the exposed portion of seed layer 316 is etched away. The formation of seed layer 316 and conductive wire 318 can use processes and materials similar to those discussed above regarding seed layer 106 and conductive layer 108.

[0089] Figure 38 shows a cross-sectional view of an integrated circuit die 350 according to some embodiments. The integrated circuit die 350 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 350 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a MEMS controller (e.g., an application-specific integrated circuit (ASIC)), a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or combinations thereof.

[0090] An integrated circuit die 350 can be formed in a wafer, which may include different device regions that can be diced in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 350 can be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit die 350 includes a semiconductor substrate 352, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 352 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 352 has an active surface (e.g., the upward-facing surface in FIG. 38), sometimes referred to as the front side, and an active surface (e.g., the downward-facing surface in FIG. 38), sometimes referred to as the back side.

[0091] A device 354 (represented by a transistor) may be formed on the front surface of the semiconductor substrate 352. The device 354 may be an active device (e.g., a transistor, diode, etc.), a capacitor, a resistor, etc. An interlayer dielectric (ILD) 356 is located above the front surface of the semiconductor substrate 352. The ILD 356 surrounds and may cover the device 354. The ILD 356 may comprise one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0092] A conductive plug 358 extends through the ILD 356 to electrically and physically couple device 354. For example, when device 354 is a transistor, the conductive plug 358 can couple the gate and source / drain regions of the transistor. The conductive plug 358 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. An interconnect structure 360 ​​is located above the ILD 356 and the conductive plug 358. The interconnect structure 360 ​​interconnects device 54 to form an integrated circuit. The interconnect structure 360 ​​can be formed, for example, by a metallization pattern in a dielectric layer on the ILD 356. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 360 ​​is electrically coupled to device 354 through the conductive plug 358.

[0093] The integrated circuit die 350 also includes pads 362, such as aluminum pads, formed for external connection. The pads 362 are located on the active side of the integrated circuit die 350, such as in and / or on the interconnect structure 360. One or more passivation films 364 are located on the integrated circuit die 350, such as on portions of the interconnect structure 360 ​​and the pads 362. Openings extend through the passivation films 364 to the pads 362. Die connectors 366, such as conductive pillars (e.g., formed of a metal such as copper), extend through the openings in the passivation films 364 and are physically and electrically coupled to the corresponding pads 362. The die connectors 366 can be formed, for example, by plating. The die connectors 366 are electrically coupled to the corresponding integrated circuit of the integrated circuit die 350.

[0094] Optionally, solder areas (e.g., solder balls or solder bumps) can be provided on pad 362. Solder balls can be used to perform chip probe (CP) testing on the integrated circuit die 350. CP testing can be performed on the integrated circuit die 350 to determine whether the integrated circuit die 350 is a known good die (KGD). Therefore, integrated circuit dies 350 that are only KGD undergo subsequent processing and are packaged, while dies that fail the CP test are not packaged. After testing, the solder areas can be removed in subsequent processing steps.

[0095] The dielectric layer 368 may (or may not) be located on the active side of the integrated circuit die 350, such as on the passivation film 364 and the die connector 366. The dielectric layer 368 laterally seals the die connector 366, and the dielectric layer 368 shares a common end with the integrated circuit die 350 laterally. Initially, the dielectric layer 368 may bury the die connector 366, such that the top surface of the dielectric layer 368 is above the top surface of the die connector 366. In some embodiments where solder regions are disposed on the die connector 366, the dielectric layer 368 may also bury the solder regions. Alternatively, the solder regions may be removed before the dielectric layer 368 is formed.

[0096] The dielectric layer 368 may be a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; or a combination thereof. The dielectric layer 368 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the die connector 366 is exposed through the dielectric layer 368 during the formation of the integrated circuit die 350. In some embodiments, the die connector 366 remains buried and is exposed during subsequent processes for packaging the integrated circuit die 350. Exposing the die connector 366 can remove any solder areas that may be present on the die connector 366.

[0097] In some embodiments, the integrated circuit die 350 is a stacked device comprising a plurality of semiconductor substrates 352. For example, the integrated circuit die 350 may be a memory device comprising a plurality of memory dies, such as a hybrid memory dataset (HMC) module, a high bandwidth memory (HBM) module, etc. In such an embodiment, the integrated circuit die 350 includes a plurality of semiconductor substrates 352 interconnected via through-substrate vias (TSVs). Each of the semiconductor substrates 352 may (or may not) have an interconnect structure 360.

[0098] In Figure 39, an integrated circuit die 350 (such as integrated circuit die 350A) is bonded to a carrier 308 by an adhesive (see, for example, adhesive 372 in Figure 45). The desired type and number of integrated circuit dies 350A are bonded in each of package regions 300A and 300B. The integrated circuit die 350A can be any of the candidate die types discussed above with respect to Figure 38, including, for example, MEMS devices or MEMS controllers, such as ASIC devices. Additional integrated circuit dies 350 / 350A can be attached to each of package regions 300A and 300B and can have the same or different functions as the illustrated integrated circuit die 350A. In the case of using multiple integrated circuit dies 350A in each package region, they can be formed in a process at the same technology node or in a process at different technology nodes. For example, the first integrated circuit die 350A can be in a process node more advanced than the second integrated circuit die 350 / 350A. When multiple integrated circuit dies 350A are used in each package region, they can have different dimensions (e.g., different heights and / or surface areas) or they can have the same dimensions (e.g., the same height and / or surface area). The spacing of conductive vias 312 and / or wires 318 that can be used in package regions 300A and 300B may be limited, especially when the integrated circuit die 350A includes devices with large coverage areas (such as SoCs). When package regions 300A and 300B have limited spacing that can be used for conductive vias 312 and / or wires 318, the use of the back-side redistribution structure 100 allows for improved interconnect arrangement.

[0099] The adhesive used for the integrated circuit die 350A is located on the back side of the integrated circuit die 350A and bonds the integrated circuit die 350A to the carrier 308. The adhesive can be any suitable adhesive, epoxy resin, die attachment film (DAF), etc. The adhesive can be applied to the back side of the integrated circuit die 350A. For example, the adhesive can be applied to the back side of the integrated circuit die 350A before dicing to separate the integrated circuit dies 350A.

[0100] In Figure 40, a sealant 320 is formed on and around the various components. After formation, the sealant 320 seals the conductive vias 312 and / or wires 318, as well as the integrated circuit die 350A. The sealant 320 can be a molding compound, epoxy resin, etc. The sealant 320 can be applied by compression molding, transfer molding, etc., and can be formed over the carrier 302, thereby burying or covering the conductive vias 312, wires 318, and / or integrated circuit die 350A. The sealant 320 is further formed in the gap regions between the integrated circuit dies 350A. The sealant 320 can be applied in liquid or semi-liquid form and then subsequently cured.

[0101] In Figure 41, a planarization process is performed on the sealant 320 to expose the conductive vias 312 and / or wires 318 of the integrated circuit die 350A, as well as the die connector 366 (see Figure 38). The planarization process may also remove material from the conductive vias 312 and / or wires 318, the dielectric layer 368 (see Figure 38), and / or the die connector 366 (see Figure 38) until the die connector 366 and the conductive vias 312 and / or wires 318 are exposed. Within the process variation, the top surfaces of the conductive vias 312 and / or wires 318, the die connector 366, the dielectric layer 368, and the sealant 320 are substantially coplanar after the planarization process. The planarization process can be, for example, chemical mechanical polishing (CMP), lamination, etc. In some embodiments, planarization may be omitted, for example, if the conductive vias 312 and / or wires 318 and / or die connector 366 have already been exposed.

[0102] In Figure 42, a redistribution structure 322 is formed over the sealant 32. The redistribution structure 322 may be a fan-out redistribution structure. In some embodiments, the redistribution structure 322 may be formed using processes and materials similar to those discussed above with respect to redistribution structures 100 and / or 200. In other embodiments, the redistribution structure 322 may be formed using other processes and materials.

[0103] For example, dielectric layer 324 can be deposited on sealant 320, conductive vias 312 and / or wires 318, and die connector 366 (see FIG. 38). In some embodiments, dielectric layer 324 is formed of a photosensitive material that can be patterned using a photomask, such as PBO, polyimide, BCB, etc. Dielectric layer 324 can be formed by spin coating, lamination, CVD, etc., or combinations thereof. Dielectric layer 324 is then patterned. Patterning forms openings that expose portions of conductive vias 312 and / or wires 318 and die connector 366. Patterning can be performed by acceptable processes, such as exposing dielectric layer 324 to light and developing when dielectric layer 324 is a photosensitive material, or by etching, for example, anisotropic etching.

[0104] Metallization pattern 326 can then be formed. Metallization pattern 326 includes conductive elements extending along the main surface of dielectric layer 324 and extending through dielectric layer 324 to be physically and electrically coupled to conductive vias 312 and / or wires 318 and integrated circuit die 350A. As an example of forming metallization pattern 326, a seed layer is formed above dielectric layer 324 and in openings extending through dielectric layer 324. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to metallization pattern 326. Patterning forms openings through the photoresist to expose the seed layer. Conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. Conductive materials can be formed by plating (such as electroplating or electroless plating). Conductive materials can include metals such as copper, titanium, tungsten, and aluminum. The combination of the conductive material and the lower portion of the seed layer forms a metallized pattern 326. The photoresist and the portion of the seed layer above which no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example by using an acceptable etching process, such as wet etching or dry etching.

[0105] Next, a dielectric layer 328 is deposited on the metallization pattern 326 and the dielectric layer 324. The dielectric layer 328 may be formed in a manner similar to that of the dielectric layer 324 and may be formed of a material similar to that of the dielectric layer 324. A metallization pattern 330 is then formed. The metallization pattern 330 includes a portion located on and extending along the main surface of the dielectric layer 328. The metallization pattern 330 also includes a portion extending through the dielectric layer 328 to physically and electrically couple the metallization pattern 326. The metallization pattern 330 may be formed in a manner similar to that of the metallization pattern 326 and may be formed of a material similar to that of the metallization pattern 326. In some embodiments, the metallization pattern 330 has different dimensions than the metallization pattern 326. For example, the conductors and / or vias of the metallization pattern 330 may be wider or thicker than the conductors and / or vias of the metallization pattern 326. Furthermore, the metallization pattern 330 may be formed with a larger pitch than the metallization pattern 326.

[0106] The processes for forming the dielectric layer and metallization pattern are repeated any desired number of times to form the remaining layers of the redistribution structure. As shown in FIG42, these include forming dielectric layers 332 and 336 and metallization pattern 334. In the illustrated embodiment, metallization pattern 334 is the topmost metallization pattern of the redistribution structure 322. Therefore, all intermediate metallization patterns of the redistribution structure 322 (e.g., metallization patterns 326 and 330) are disposed between metallization pattern 334 and integrated circuit die 350A. In some embodiments, metallization pattern 334 has different dimensions than metallization patterns 326 and 330. For example, the conductors and / or vias of metallization pattern 334 may be wider or thicker than the conductors and / or vias of metallization patterns 326 and 330. Furthermore, metallization pattern 334 may be formed with a larger spacing than metallization pattern 330. Dielectric layer 336 is the topmost dielectric layer of redistribution structure 322. Therefore, all metallization patterns (e.g., metallization patterns 326, 330, and 334) of the redistribution structure 322 are disposed between the dielectric layer 336 and the integrated circuit die 350A. Furthermore, all intermediate dielectric layers (e.g., dielectric layers 324, 328, and 332) of the redistribution structure 322 are disposed between the dielectric layer 336 and the integrated circuit die 350A.

[0107] Figure 43 illustrates an embodiment forming a conductive connector 340 attached to the redistribution structure 322. In some embodiments, an under-bump metallization (UBM) 338 is formed for external connection to the fan-out redistribution structure 322. The UBM 338 has a bump portion located on and extending along the main surface of the dielectric layer 336, and a via portion extending through the dielectric layer 336 to physically and electrically couple the metallization pattern 334. Thus, the UBM 338 is electrically coupled to the conductive via 312 and / or wire 318 and the integrated circuit die 350A. The UBM 338 may be formed of the same material as the metallization pattern 326. In some embodiments, the UBM 338 has different dimensions than the metallization patterns 326, 330, and 334.

[0108] Next, conductive connectors 340 are formed on the UBM 338. Conductive connectors 340 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connectors 340 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 340 are initially formed by evaporation, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once the solder layer has been structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, conductive connectors 340 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal overlay is formed on the top of the metal pillars. The metal coating may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process.

[0109] Figures 44 through 53 illustrate the addition of another embedded integrated circuit die above the redistribution structure 322. In some embodiments, instead of forming conductive connectors 340, vias 342 are formed that contact the topmost metallized pattern of the redistribution structure 322, such as metallized pattern 334. In Figure 44, the dielectric layer 336 is patterned to form openings that expose portions of the metallized pattern 334. The patterning can be formed by acceptable processes, such as exposing the dielectric layer 336 to light when it is a photosensitive material, or by etching, for example, anisotropic etching. If the dielectric layer 336 is a photosensitive material, it can be developed after exposure. The via 342 is formed in the opening in the dielectric layer 336 and extends away from the carrier 302. The via 342 can be formed using materials and processes similar to those used for the conductive via 312 described above.

[0110] In Figure 45, an integrated circuit die 350 (such as integrated circuit die 350B) is bonded to a redistribution structure 322 by adhesive 372. A desired type and number of integrated circuit dies 350B are bonded in each of package regions 300A and 300B. The integrated circuit die 350B can be any candidate die type discussed above with respect to the integrated circuit die 350 of Figure 38, including, for example, MEMS devices, analog devices, radio frequency (RF) devices, etc. The adhesive 372 for the integrated circuit die 350B is located on the back side of the integrated circuit die 350B and bonds the integrated circuit die 350B to the redistribution structure 322. The adhesive 372 can be similar to the adhesive discussed above with respect to Figure 39.

[0111] In Figure 46, a sealant 374 is formed on and around the various components. After formation, the sealant 374 seals the through-hole 342 and the integrated circuit die 350B. The sealant 374 can be formed using processes and materials such as those discussed above with respect to the sealant 320 in Figure 40.

[0112] In Figure 47, a planarization process is performed on the sealant 374 to expose the via 342 and die connector 366 of the integrated circuit die 350B. The planarization process may also remove material from the via 342, dielectric layer 368 (see Figure 38), and / or die connector 366 (see Figure 38) until the die connector 366 and via 342 are exposed. Within the process variation, the top surfaces of the via 342, die connector 366, dielectric layer 368, and sealant 374 are substantially coplanar after the planarization process. The planarization process can be, for example, chemical mechanical polishing (CMP), lamination, etc. In some embodiments, planarization may be omitted, for example, if the via 342 and / or die connector 366 have already been exposed.

[0113] In Figure 48, interconnects 382 are formed over sealant 374, via 342, and integrated circuit die 350B. A dielectric layer 384 of the interconnects 382 can be deposited on sealant 374, via 342, and integrated circuit die 350B. In some embodiments, the dielectric layer 384 is formed of a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, BCB, etc. The dielectric layer 384 can be formed by spin coating, lamination, CVD, or combinations thereof. The dielectric layer 384 is then patterned. Patterning forms openings that expose portions of via 342 and die connector 366. Patterning can be performed by acceptable processes, such as exposing the dielectric layer 384 to light and developing it when the dielectric layer 384 is a photosensitive material, or by etching, for example, anisotropic etching.

[0114] Next, a metallization pattern 386 is formed over the dielectric layer 384 and in the opening through the dielectric layer 384 and in contact with the via 342. The metallization pattern 386 can be formed using any suitable process and material. In some embodiments, the metallization pattern 386 can be formed in a manner similar to that discussed above with respect to the metallization pattern 326 of FIG. 42. The interconnect 382 can be formed from any number of dielectric layers and metallization patterns. An upper dielectric layer 388 is formed over the topmost metallization pattern (metallization pattern 386 as shown in FIG. 48).

[0115] In Figure 49, an opening 390 can be formed through the dielectric layer of interconnect 382 to expose the upper portion of integrated circuit die 350B. For example, if integrated circuit die 350B is a MEMS device, the sensor region of the MEMS device can be exposed. The opening 390 can be formed by depositing a mask over interconnect 382 and patterning the mask to protect reserved areas of interconnect 382, ​​thereby exposing the area of ​​interconnect 382 to be removed. Next, any suitable removal process (such as dry etching or wet etching) can be used to remove the exposed portion of interconnect 382. Each layer of dielectric layer of the interconnect, such as dielectric layer 388 and dielectric layer 384, can be removed sequentially, extending the opening 390 until integrated circuit die 350B is exposed through the opening 390.

[0116] In Figure 50, encapsulation regions 300A and 300B are attached to frame 392. In some embodiments, an adhesive may be used between frame 392 and interconnect 382. In other embodiments, frame 392 may be attached by attraction or electrostatic charge. Figure 50 also illustrates carrier substrate peeling to separate (or “peel off”) carrier 308 from redistribution structure 100. According to some embodiments, peeling involves projecting light, such as laser or UV light, onto die attachment film 306, causing die attachment film 306 to decompose under the heat of the light, and carrier 308 can be removed. In some embodiments, the structure may then be flipped.

[0117] In Figure 51, in some embodiments, conductive connectors 396 are formed to couple to the redistribution structure 100. Openings can be formed through the upper insulating layer (i.e., insulating layer 152) of the redistribution structure 100 using acceptable photolithography techniques, for example, by depositing a photo-patternable mask over the redistribution structure, patterning the photo-patternable mask by exposing, developing, and curing the photo-patternable mask, and then using the openings in the mask to etch the upper insulating layer of the redistribution structure 100 to expose the conductive layer 148.

[0118] Optionally, a UBM 394 can be formed in the opening for external connection to the front side of the redistribution structure 100. The UBM 394 may have a bump portion located on and extending along the main surface of the insulating layer 152 of the redistribution structure 100, and a via portion extending through the insulating layer 152 to physically and electrically couple the conductive layer 148. Thus, via the redistribution structure 322 and the interconnect 382, ​​the UBM is electrically coupled to the conductive vias 312 and / or wires 318, integrated circuit dies 350A and 350B through the respective conductive layers 148. The UBM 394 may be formed of the same material as the seed layer 146 and / or conductive layer 148 of the redistribution structure 100. The UBM 394 may have different dimensions (e.g., thickness) than the metallization patterns corresponding to the conductive layers 108, 118, 128, 138, 148, etc.

[0119] Conductive connector 396 is formed in the opening and on UBM 394 (if used). Conductive connector 396 can be formed using processes and materials similar to conductive connector 160 of FIG. 19 or conductive connector 340 of FIG. 43.

[0120] In Figure 52, the partitioning process 398 separates one package from another, such that one package is formed by a structure in package region 300A and the other package is formed by a structure in package region 300B. The partitioning process is carried out by sawing or laser cutting along a scribe line area, for example, between package regions 300A and 300B. The sawing separates package regions 300A and 300B.

[0121] In Figure 53, the resulting, segmented device stack 300 originates from either package region 300A or package region 300B. Because the device stack 300 includes a redistribution structure 100 comprising unfilled high-shrinkage insulating layers 112 and 122, 132, 142, and 152, the device stack 300 can be fabricated with fewer planarization processes and at a smaller thickness. It should be understood that the thickness of the redistribution structure 100 shown in Figure 53 is not proportional but exaggerated to show detail. For example, for the same number of metallization layers, the resulting redistribution structure 100 can be less than 50% of the thickness of the redistribution structure 322, such as between 20% and 50%.

[0122] Figures 54 through 59 show cross-sectional views of various intermediate stages in the formation of semiconductor devices, such as integrated fan-out (InFO) packages, for example, for MEMS devices. Package regions 400A and 400B can be compared to package regions 300A and 300B discussed above. Figure 54 shows a redistribution structure 200 (see Figure 29) formed over a carrier 402 attached to a strip 404. The carrier 402 and strip 404 can be similar to those discussed above with respect to carrier 301 and strip 304. The seed layer 206 of the redistribution structure and the conductive layer 208 of the redistribution structure 200 can be similar to those discussed above with respect to seed layer 106 and conductive layer 108 of Figure 34. In particular, with respect to seed layer 206 and conductive layer 208, each of these has a portion extending downward into the carrier 402 and, in some embodiments, through the carrier 402. The upper surface of the conductive layer 208 may have depressions aligned with the openings in the carrier 402, similar to those discussed above with respect to the conductive layer 108 of Figures 34 and 35.

[0123] In Figure 55, the strip 404 is removed and the encapsulation region 300A is attached to the carrier 408 via the die attachment film 406. The carrier 408 and the die attachment film 406 can be similar to those discussed above regarding the carrier 308 and the die attachment film 306. As discussed above, the upper surface of the redistribution structure 200 is wavy. The top surface of the die attachment film 406 can have a high degree of planarity. Therefore, the die attachment film 406 has a varying thickness across the surface of the redistribution structure 200.

[0124] Figure 56 shows an enlarged portion of the dashed box depicted in Figure 55 to better illustrate the varying thickness of the die attachment film 406. Distance d31 represents any depression in the surface of the uppermost insulating layer (e.g., insulating layer 232) of the redistribution structure 200 that the die attachment film 406 can extend into. Distance d32 represents the thinnest portion of the die attachment film 406. Distance d31 can also represent the thickest portion of the die attachment film 406. In some embodiments, for the thinnest portion of the die attachment film 405, distance d32 can be as small as 10% to 25% of the thickest portion of the die attachment film 405. The die attachment film 406 can be made thicker to minimize the difference between distances d31 and d32; however, the ability to provide a relatively smaller distance d32 with 10% to 25% of distance d31 allows for greater flexibility in the waviness of the insulating layer 232 of the redistribution structure 200.

[0125] In Figure 57, carrier 408 is flipped over and various structures are formed on carrier 402. The same reference numerals indicate the same elements as those discussed above with respect to Figures 31 to 53. Package regions 400A and 400B are attached to frame 392 and carrier 408 is removed using processes similar to those discussed above with respect to carrier 308.

[0126] In Figure 58, an optional UBM 494 and conductive connector 496 are formed through the uppermost insulating layer of the redistribution structure 200 to contact the upper conductive layer 228. The UBM 494 and conductive connector 496 can be formed using processes and materials similar to those discussed above regarding UBM 394 and conductive connector 396. The package area can then be divided using a partitioning process 398, for example, to separate package area 400A from package area 400B.

[0127] In Figure 59, the resulting, segmented device stack 400 originates from either package region 400A or package region 400B. Because the device stack 400 includes a redistribution structure 200 comprising unfilled, high-shrinkage insulating layers 212, 222, and 232 (including more or fewer insulating layers based on the design), the device stack 400 can be fabricated with fewer planarization processes and at a smaller thickness. It should be understood that the thickness of the redistribution structure 200 shown in Figure 58 is not proportional but exaggerated to show detail. For example, for the same number of metallization layers, the resulting redistribution structure 100 can be less than 50% of the thickness of the redistribution structure 322, such as between 20% and 50%.

[0128] Figures 60 and 61 illustrate additional embodiments using redistribution structures 100 and 200, respectively, in package 500 and package 600. The main difference between the embodiments in Figures 60 and 61 is that the embodiment of Figure 60 utilizes a redistribution structure formed according to redistribution structure 100 discussed above, while the embodiment of Figure 61 utilizes a redistribution structure formed according to redistribution structure 200 discussed above. The remaining elements of Figures 60 and 61 will be discussed together.

[0129] Each of the layers 525 of packages 500 and 600 may be a segmented wafer portion 505 of a wafer. In some embodiments, packages 500 and 600 may be formed by stacking wafers in a wafer-on-wafer process to create a wafer stack. Each wafer portion 505 may include a through-hole 510 and a bonding pad 515. Devices such as transistors, resistors, capacitors, etc., may be formed in the wafer. Although four wafer portions 505 are shown, it should be understood that more or fewer wafer portions may be used. Next, redistribution structures 100 or 200 are formed, respectively. The wafer stack may then be flipped and an insulating layer 530 may be formed on a first side of packages 500 and 600, and conductive connections 535 may be formed through the insulating layer 530. Conductive connections 535 may be formed using materials and processes similar to those used to form conductive connections 160 or 396 discussed above.

[0130] In other embodiments, layer 525 may represent other structures, such as a sealed die, an interposer, a semiconductor substrate, and combinations thereof.

[0131] After the conductive connector 535 is formed, packages 500 and 600 can be separated from other similar packages in the wafer stack. Each separated package 500 or 600 can then be mounted to a package substrate 550 using the conductive connector 535. The package substrate 550 includes a substrate core 555 and bonding pads 560 above the substrate core 555. The substrate core 555 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, germanium silicon carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, etc., can also be used. Furthermore, the substrate core 555 can be an SOI substrate. Typically, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 555 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide-triazine BT resin, or alternatively other PCB materials or films. A laminated film, such as ABF or other laminated materials, can be used for the substrate core 555.

[0132] The substrate core 555 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, and combinations thereof, can be used to generate the structural and functional requirements for the design of the device stack. The devices can be formed using any suitable method.

[0133] The substrate core 555 may also include a metallization layer and vias (not shown), with bonding pads 560 physically and / or electrically coupled to the metallization layer and vias. The metallization layer may be formed over active and passive devices and designed to connect the respective devices to form a functional circuit. The metallization layer may be formed of alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), with vias interconnecting the conductive material layers, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 555 is substantially devoid of active and passive devices.

[0134] In some embodiments, the conductive connector 535 is reflowed to attach the package 500 or 600 to the bonding pad 560. The conductive connector 535 electrically and / or physically couples the package substrate 550 (including the metallization layer in the substrate core 555) to the package 500 or 600. In some embodiments, solder resist 565 may be formed on the substrate core 555. The conductive connector 535 may be disposed in openings in the solder resist 565 to be electrically and mechanically coupled to the bonding pad 560. The solder resist 565 may be used to protect areas of the package substrate 550 from external damage.

[0135] An epoxy resin flux (not shown) is formed on the conductive connector 535, and at least some epoxy resin portions of the remaining epoxy resin flux are reflowed after the package 500 or 600 is attached to the package substrate 550. This remaining epoxy resin portion can serve as an underfill to reduce stress and protect the joint created by the reflow of the conductive connector 535. In some embodiments, an underfill 540 may be formed around the conductive connector 535 between the package 500 or 600 and the package substrate 550. The underfill 540 may be formed by a capillary flow process after attaching the package 500 or 600, or by a suitable deposition method before attaching the package 500 or 600.

[0136] In some embodiments, passive devices (e.g., surface mount devices (SMDs, not shown) may also be attached to package 500 or 600 (e.g., to bonding pad 515) or to package substrate 550 (e.g., to bonding pad 560). For example, passive devices may be bonded to the same surface of package 500 or 600 or package substrate 550 as conductive connection 535. Passive devices may be attached to package 500 or 600 before package 500 or 600 is mounted on package substrate 550, or may be attached to package substrate 550 before or after package 500 or 600 is mounted on package substrate 550.

[0137] Package 500 or 600 can be implemented in other device stacks. For example, a PoP structure is shown and configured to accept additional package components attached thereto (e.g., at UBMs 155 and 255), but package 500 or 600 can also be implemented in a flip-chip ball grid array (FCBGA) package. In such embodiments, package 500 or 600 is mounted to a substrate such as package substrate 550, but UBMs 155 and 255 can be omitted. Instead, a cover or heat sink can be attached to package 500 or 600.

[0138] Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D-packaged or 3DIC devices. Test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0139] The embodiments offer several advantages. They utilize a redistributed structure that does not employ a planarization process after the insulating layer of the redistributed structure is formed, thereby simplifying the manufacturing process of the redistributed structure. Furthermore, the insulating layer between the metallized patterns can be made very thin because planarization is not performed. The insulating layer of the redistributed structure can also be made of a filler-free material with a shrinkage rate, which can produce a flatter insulating layer even without a planarization process. The resulting wavy insulating layer is less wavy than when using typical insulating materials. The redistributed structure can also have a first metallized pattern that is thicker than the other metallized patterns in the other layers, providing better conductivity and limiting signal attenuation through the first metallized pattern. Because the insulating layer separating each metallized pattern is very thin, the upper metallized pattern extends along the sidewalls of the openings in the insulating layer and along the exposed portions of the lower metallized pattern.

[0140] One embodiment is a redistribution structure of conductive components coupled to a substrate. The redistribution structure may include a first conductive layer and a first insulating layer above the first conductive layer. The first insulating layer may include a first unfilled insulating material. A second conductive layer may be located above the first insulating layer, coupled to the first conductive layer, and a second insulating layer may be located above the second conductive layer, comprising a second unfilled insulating material. The device also includes conductive connectors electrically coupled to the redistribution structure. In an embodiment, the first unfilled insulating material differs from the second unfilled insulating material. In an embodiment, the upper surface of the second insulating layer is wavy. In an embodiment, the difference between the average peak and the average valley of the upper surface is between 3 μm and 5 μm. In an embodiment, the first conductive layer is three to five times thicker than the second conductive layer. In an embodiment, the surface of the second insulating layer is free of polishing marks. In an embodiment, the second conductive layer includes a seed layer and a metal layer above the seed layer, wherein the seed layer conformally coats grooves in the first insulating layer, the grooves exposing portions of the first conductive layer. In an embodiment, the substrate is a ceramic carrier and is situated between the redistribution structure and a sealed die. In an embodiment, the device may include a metallization layer disposed in the same layer as the sealed die, the thickness of the metallization layer being the same as the thickness of the sealed die.

[0141] Another embodiment includes a first redistribution structure, which may include: a first metallization pattern having a first thickness; a first insulating layer adjacent to the first metallization pattern; and a second metallization pattern adjacent to the first insulating layer. The first insulating layer has a second thickness between the first and second metallization patterns, wherein the second thickness is less than the first thickness. The device also includes a sealed die disposed above the first redistribution structure. In an embodiment, the device may include a ceramic carrier disposed between the first redistribution structure and the sealed die. In an embodiment, the sealed die includes a microelectromechanical system (MEMS) device. In an embodiment, the second metallization pattern has a third thickness, wherein the third thickness is less than the first thickness, and wherein the first metallization pattern is positioned closer to the sealed die than the second metallization pattern. In an embodiment, the second metallization pattern includes a seed layer and a conductive layer, wherein the seed layer is conformally coated on the sidewalls of an opening through the first insulating layer. In an embodiment, the upper surface of the first insulating layer is wavy.

[0142] Another embodiment is a method comprising depositing a first metallization pattern on a substrate. The method also includes depositing a first insulating layer, without filler, over the first metallization pattern. The method also includes curing the first insulating layer such that the first insulating layer shrinks by less than 5%. The method also includes forming a first opening through the first insulating layer to expose a portion of the first metallization pattern. The method also includes depositing a second metallization pattern over the first insulating layer and in the first opening without flushing the first insulating layer. The method also includes depositing a second insulating layer, without filler, over the second metallization pattern. In embodiments, the first insulating layer shrinks between 1% and 5%. In embodiments, the first insulating layer has a different shrinkage rate than the second insulating layer. In embodiments, the metallization pattern is deposited over a ceramic carrier. In embodiments, the ceramic carrier is flipped. In embodiments, an integrated circuit die is attached to the ceramic carrier; and a sealant is deposited laterally around the integrated circuit die.

[0143] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: A redistribution structure coupled to a conductive component on a substrate, the redistribution structure comprising: a first conductive layer; a first insulating layer above the first conductive layer, the first insulating layer comprising a first unfilled insulating material, the first insulating layer having a shrinkage rate between 95% and 99%; a second conductive layer above the first insulating layer, the second conductive layer coupled to the first conductive layer; and a second insulating layer above the second conductive layer, the second insulating layer comprising a second unfilled insulating material, the second insulating layer having a shrinkage rate between 65% and 80%; and the semiconductor device further comprising a conductive connector electrically coupled to the redistribution structure.

2. The semiconductor device according to claim 1, wherein, The first unfilled insulating material is different from the second unfilled insulating material.

3. The semiconductor device according to claim 1, wherein, The upper surface of the second insulating layer is wavy.

4. The semiconductor device according to claim 3, wherein, The difference between the average peak and the average valley of the upper surface is between 3 μm and 5 μm.

5. The semiconductor device according to claim 1, wherein, The first conductive layer is three to five times thicker than the second conductive layer.

6. The semiconductor device according to claim 1, wherein, The surface of the second insulating layer has no polishing marks.

7. The semiconductor device according to claim 1, wherein, The second conductive layer includes a seed layer and a metal layer above the seed layer, wherein the seed layer is conformally coated with a groove in the first insulating layer, the groove exposing a portion of the first conductive layer.

8. The semiconductor device according to claim 1, further comprising: A sealed die, wherein the substrate is a carrier and the substrate is located between the redistribution structure and the sealed die.

9. The semiconductor device according to claim 8, further comprising: A metallization layer is disposed in the same layer as the sealed die, and the thickness of the metallization layer is the same as the thickness of the sealed die.

10. A semiconductor device, comprising: A first redistribution structure, comprising: a first metallization pattern having a first thickness; a first insulating layer adjacent to the first metallization pattern having a shrinkage rate between 95% and 99%; a second metallization pattern adjacent to the first insulating layer, wherein the first insulating layer has a second thickness between the first metallization pattern and the second metallization pattern, wherein the second thickness is less than the first thickness; a second insulating layer adjacent to the second metallization pattern having a shrinkage rate between 65% and 80%; and the semiconductor device further comprising a hermetically sealed die disposed above the first redistribution structure.

11. The semiconductor device of claim 10, further comprising: The carrier is disposed between the first redistribution structure and the sealed core.

12. The semiconductor device according to claim 10, wherein, The sealed die includes microelectromechanical systems (MEMS) devices.

13. The semiconductor device according to claim 10, wherein, The second metallization pattern has a third thickness, wherein the third thickness is less than the first thickness, and wherein the first metallization pattern is positioned closer to the sealed die than the second metallization pattern.

14. The semiconductor device according to claim 10, wherein, The second metallization pattern includes a seed layer and a conductive layer, wherein the seed layer is conformally coated on the sidewall of an opening through the first insulating layer.

15. The semiconductor device according to claim 10, wherein, The upper surface of the first insulating layer is wavy.

16. A method of forming a semiconductor device, comprising: A first metallization pattern is deposited on the substrate; A first insulating layer is deposited over the first metallized pattern, the first insulating layer being unfilled; The first insulating layer is cured such that the first insulating layer shrinks by less than 5%; a first opening is formed through the first insulating layer to expose a portion of the first metallized pattern; Without flushing the first insulating layer, a second metallization pattern is deposited over the first insulating layer and in the first opening; A second insulating layer is deposited over the second metallization pattern, the second insulating layer being unfilled; And cure the second insulating layer, causing the second insulating layer to shrink by 20% to 35%.

17. The method according to claim 16: wherein, The first insulating layer shrinks between 1% and 5%.

18. The method according to claim 16, wherein, The morphology of the upper surface of the cured second insulating layer is flatter than the corresponding morphology of the upper surface of the first insulating layer.

19. The method of claim 16, wherein, The first metallization pattern is deposited on the carrier.

20. The method of claim 19, further comprising: Flip the carrier; Attach the integrated circuit die to the carrier; And a sealant deposited laterally around the integrated circuit die.

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