Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and its formation method are disclosed. The structure includes: a first substrate, comprising a first surface and a second surface; a first dielectric structure having a first groove and a second groove on the first surface; a first interconnect layer located within the first groove; a first electrode layer located within the second groove; a second substrate bonded to the first surface of the first substrate, comprising a third surface and a fourth surface, wherein the third surface of the second substrate is bonded to the first surface of the first substrate; a second dielectric structure having a third groove and a fourth groove on the third surface; a second interconnect layer located within the third groove, wherein the second interconnect layer is connected to the first interconnect layer in a one-to-one correspondence; and a second electrode layer located within the fourth groove, wherein the surface of the second electrode layer has a dielectric layer, and the first electrode layer and the dielectric layer are connected in a one-to-one correspondence, wherein the first electrode layer, the second electrode layer, and the dielectric layer constitute a capacitor structure; or the surface of the second electrode layer does not have a dielectric layer, and the first electrode layer and the second electrode layer are connected in a one-to-one correspondence. The performance of the structure is optimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] In the semiconductor device manufacturing process, in order to achieve a high degree of integration of device functions and save silicon wafer area, 3D stacking is usually used to form semiconductor devices, that is, two functional wafers are bonded together to form a new device structure.

[0003] However, the existing 3D stacking method for forming semiconductor devices still needs improvement. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the existing 3D stacking method for forming semiconductor devices.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a first substrate, the first substrate including a first surface and a second surface opposite to each other; a first dielectric structure located on the first surface, the first dielectric structure having a first groove and a second groove arranged in parallel; a first interconnect layer located in the first groove, and a first electrode layer located in the second groove; a second substrate bonded to the first surface of the first substrate, the second substrate including a third surface and a fourth surface opposite to each other, the third surface of the second substrate being bonded to the first surface of the first substrate facing each other; a second dielectric structure located on the third surface, the second dielectric structure having a third groove and a fourth groove arranged in parallel; a second interconnect layer located in the third groove, the second interconnect layer being connected to the first interconnect layer in a one-to-one correspondence; a second electrode layer located in the fourth groove, the surface of the second electrode layer having a dielectric layer, the first electrode layer and the dielectric layer being connected in a one-to-one correspondence, the first electrode layer, the second electrode layer and the dielectric layer constituting a capacitor structure; or, the surface of the second electrode layer does not have a dielectric layer, the first electrode layer and the second electrode layer being connected in a one-to-one correspondence.

[0006] Optionally, the surface of the second electrode layer has a dielectric layer; the top surface of the dielectric layer is flush with the surface of the second dielectric structure, and the top surface of the dielectric layer is flush with the surface of the second interconnecting layer.

[0007] Optionally, the surface of the first connecting layer is flush with the surface of the first dielectric structure.

[0008] Optionally, the thickness of the dielectric layer ranges from 10 Å to 10,000 Å.

[0009] Optionally, the material of the first connecting layer includes metal, the material of the second connecting layer includes metal, the material of the first electrode layer includes metal, and the material of the second electrode layer includes metal, wherein the metal material includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0010] Optionally, the dielectric layer material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0011] Optionally, the surface of the second electrode layer does not have a dielectric layer; the first dielectric structure also has a plurality of fifth grooves, the plurality of fifth grooves being connected to adjacent second grooves; a first metal layer is located in the fifth grooves, and a plurality of first electrode layers are connected through the first metal layer, the second electrode layer, the first electrode layer and the first metal layer constituting an inductor structure.

[0012] Optionally, the projection pattern of the plurality of the first metal layers and the plurality of the first electrode layers on the first substrate is annular or rectangular.

[0013] Optionally, the second dielectric structure further includes a plurality of sixth grooves, which are connected to adjacent fourth grooves; a second metal layer is located within the sixth grooves; a plurality of second electrode layers are connected through the second metal layer; the first metal layer and the second metal layer are connected in a one-to-one correspondence; and the second electrode layer, the second metal layer, the first electrode layer and the first metal layer constitute an inductor structure.

[0014] Optionally, the projection pattern of the plurality of second metal layers and the plurality of second electrode layers on the second substrate is annular or rectangular.

[0015] Optionally, the first substrate has a plurality of first device structures on its first surface, and the first connection layer and the first electrode layer are electrically connected to a portion of the first device structures, respectively.

[0016] Optionally, the third surface of the second substrate has a plurality of second device structures, and the second connection layer and the second electrode layer are electrically connected to a portion of the second device structures, respectively.

[0017] Optionally, the thickness of the first electrode layer ranges from 0.1 micrometers to 100 micrometers; the thickness of the second electrode layer ranges from 0.1 micrometers to 100 micrometers.

[0018] Optionally, the projection pattern of the first electrode layer on the first substrate surface is a circle, a rectangle, or an ellipse; the projection pattern of the second electrode layer on the second substrate surface is a circle, a rectangle, or an ellipse.

[0019] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a first substrate, the first substrate including opposing first and second surfaces; forming a first dielectric structure on the first surface, the first dielectric structure having parallel arranged first and second grooves; forming a first interconnect layer in the first groove and forming a first electrode layer in the second groove; providing a second substrate, the second substrate including opposing third and fourth surfaces; forming a second dielectric structure on the third surface, the second dielectric structure having parallel arranged third and fourth grooves; forming a second interconnect layer in the third groove and forming a second electrode layer in the fourth groove; forming a dielectric layer on the surface of the second electrode layer; bonding the first surface of the first substrate and the third surface of the second substrate, the first interconnect layer and the second interconnect layer being connected one-to-one, and the first electrode layer and the dielectric layer being connected one-to-one; or, not forming the dielectric layer on the surface of the second electrode layer, the first electrode layer and the second electrode layer being connected one-to-one.

[0020] Optionally, the first connection layer and the second connection layer are connected in a one-to-one correspondence, and the first electrode layer and the dielectric layer are connected in a one-to-one correspondence; the method for forming the second connection layer, the second electrode layer, and the dielectric layer includes: forming a connection material layer in a third groove, a fourth groove, and on a second dielectric structure; planarizing the connection material layer until the surface of the second dielectric structure is exposed, forming a second connection layer in the third groove, and forming an initial second electrode layer in the fourth groove; etching back the initial second electrode layer to form a second electrode layer, wherein the top plane of the second electrode layer is lower than the top surface of the second dielectric structure; forming a dielectric material layer on the surface of the second electrode layer, the surface of the second connection layer, and the surface of the second dielectric structure; planarizing the dielectric material layer until the surface of the second connection layer is exposed, and forming a dielectric layer on the surface of the second electrode layer.

[0021] Optionally, the method of etching back the initial second electrode layer to form the second electrode layer includes: forming a patterned layer on the initial second electrode layer, on the second interconnect layer, and on the second dielectric structure, the patterned layer exposing the surface of the initial second electrode layer; etching the initial second electrode layer using the patterned layer as a mask until a portion of the four groove sidewall surfaces is exposed to form the second electrode layer.

[0022] Optionally, the method for forming the first connecting layer and the first electrode layer includes: forming a connecting material layer in a first groove, a second groove, and on a first dielectric structure; planarizing the connecting material layer until the surface of the first dielectric structure is exposed; forming the first connecting layer in the first groove; and forming the first electrode layer in the second groove.

[0023] Optionally, the method for bonding the first substrate and the second substrate includes: attaching a first surface of the first substrate to a third surface of the second substrate, wherein the first connecting layer and the second connecting layer correspond one-to-one, and the dielectric layers on the surfaces of the first electrode layer and the second electrode layer correspond one-to-one; performing heat treatment on the first substrate and the second substrate to bond the first connecting layer and the second connecting layer, to attach the dielectric layers on the surfaces of the first electrode layer and the second electrode layer, and to bond the first dielectric structure and the second dielectric structure.

[0024] Optionally, the first electrode layer and the second electrode layer are connected in a one-to-one correspondence; the first dielectric structure also has a plurality of fifth grooves, and the plurality of fifth grooves are connected to adjacent second grooves; while forming the first electrode layer in the second groove, it also includes: forming a first metal layer in the fifth groove, the plurality of first electrode layers being connected through the first metal layer, and the projection pattern of the plurality of first metal layers and the plurality of first electrode layers on the first substrate being annular or rectangular.

[0025] Optionally, the second dielectric structure further includes a plurality of sixth grooves, which are connected to adjacent fourth grooves; while forming a second electrode layer in the fourth groove, it also includes: forming a second metal layer in the sixth groove, with the plurality of second electrode layers connected through the second metal layer, and the projection pattern of the plurality of second metal layers and the plurality of second electrode layers on the second substrate being annular or rectangular, and the first metal layer and the second metal layer being connected in a one-to-one correspondence.

[0026] Optionally, the first substrate has a plurality of first device structures on its first surface, and the first connection layer and the first electrode layer are electrically connected to a portion of the first device structures, respectively.

[0027] Optionally, the third surface of the second substrate has a plurality of second device structures, and the second connection layer and the second electrode layer are electrically connected to a portion of the second device structures, respectively.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The technical solution of this invention involves forming a dielectric layer on the surface of a second electrode layer on a second substrate. After bonding the first and second substrates, the first electrode layer, the second electrode layer, and the dielectric layer located between the first and second electrode layers form a capacitor structure; alternatively, the surface of the second electrode layer does not have a dielectric layer, allowing the first and second electrode layers to be connected one-to-one for subsequent formation of an inductor structure. This improves the utilization rate of the first and second electrode layers, increases the integration of the device, and simplifies the fabrication process for individual capacitor and inductor structures. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the semiconductor structure formation process in one embodiment;

[0031] Figures 2 to 10 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention;

[0032] Figures 11 to 17 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention;

[0033] Figures 18 to 21 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention. Detailed Implementation

[0034] As described in the background section, the existing 3D stacking methods for forming semiconductor devices still need improvement. This will now be analyzed and explained with reference to specific embodiments.

[0035] Figure 1 This is a schematic diagram of the semiconductor structure formation process in one embodiment.

[0036] Please refer to Figure 1 A first substrate 100 is provided; a device layer 101 is formed on the first substrate 100, the device layer 101 having a device structure 102 therein; a dielectric structure 103 is formed on the device layer 101; a connection layer 104 and a pseudo-connection layer 105 are formed in the dielectric structure 103, the connection layer 104 being electrically connected to the device structure 102.

[0037] Next, a second substrate is provided, and the above structure is repeatedly formed on the second substrate. The first substrate 100 and the second substrate are bonded together so that the connecting layer 104 on the first substrate 100 and the connecting layer on the second substrate are connected one-to-one.

[0038] During the formation of the semiconductor structure, the method for forming the interconnect layer 104 and the pseudo-interconnect layer 105 includes: forming a plurality of first grooves and second grooves within a dielectric structure, wherein the first grooves expose the surface of the interconnect layer 104; forming an interconnect material layer within the first grooves, within the second grooves, and on the dielectric structure; planarizing the interconnect material layer until the surface of the dielectric structure is exposed; forming the interconnect layer 104 within the first grooves; and forming the pseudo-interconnect layer 105 within the second grooves. The pseudo-interconnect layer 105 is used to increase the uniformity of the planarization process when forming the interconnect layer 104 by planarizing the interconnect material layer, resulting in better flatness of the surface of the formed interconnect layer 104, which facilitates subsequent bonding.

[0039] The connection layer 104 is used to electrically connect the device structure 102, and the pseudo connection layer 105 is not connected to the device structure. Therefore, the present invention provides a technical solution that enables the pseudo connection layer 105 to be utilized to further increase the device integration of the semiconductor structure.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 10 This is a schematic diagram of the semiconductor structure formation process in one embodiment of the present invention.

[0042] Please refer to Figure 2 A first substrate 200 is provided, the first substrate 200 including opposing first and second surfaces.

[0043] The first substrate 200 has a plurality of first device structures 201 and a first isolation layer 202 on its first surface, wherein the first device structures 201 are located within the first isolation layer 202.

[0044] The first device structure 201 includes transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0045] In this embodiment, the material of the first substrate 200 includes silicon.

[0046] Please refer to Figure 3 A first dielectric structure 203 is formed on a first surface of a first substrate 200, and the first dielectric structure 203 has a first groove 204 and a second groove 205 arranged in parallel.

[0047] In this embodiment, the first groove 204 exposes a portion of the top surface of the first device structure 201; the second groove 205 exposes a portion of the top surface of the first device structure 201.

[0048] In other embodiments, the first groove exposes a portion of the top surface of the first device structure; the second groove exposes a portion of the top surface of the first insulating layer.

[0049] In this embodiment, the first groove 204 and the second groove 205 are damascus structures, that is, the first groove 204 and the second groove 205 include a first part (not shown) that exposes the first device structure 201, and a second part (not shown) on the remaining first part and communicating with the first part. The projected area of ​​the second part on the surface of the first substrate 200 is greater than the projected area of ​​the first part on the surface of the first substrate 200.

[0050] In other embodiments, the top and bottom areas of the first groove are equal, and the top and bottom areas of the second groove are equal.

[0051] The projection pattern of the first groove 204 on the surface of the first base 200 is a circle, a rectangle or an ellipse; the projection pattern of the second groove 205 on the surface of the first base 200 is a circle, a rectangle or an ellipse.

[0052] In this embodiment, the projection pattern of the first groove 204 on the surface of the first substrate 200 is rectangular; the projection pattern of the second groove 205 on the surface of the first substrate 200 is rectangular.

[0053] The material of the first dielectric structure 203 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0054] In this embodiment, the material of the first dielectric structure 203 includes silicon oxide.

[0055] Please refer to Figure 4 A first connecting layer 206 is formed in the first groove 204, and a first electrode layer 207 is formed in the second groove 205.

[0056] The method for forming the first connecting layer 206 and the first electrode layer 207 includes: forming a connecting material layer (not shown) in the first groove 204, the second groove 205 and on the first dielectric structure 203; planarizing the connecting material layer until the surface of the first dielectric structure 203 is exposed; forming the first connecting layer 206 in the first groove 204 and forming the first electrode layer 207 in the second groove 205.

[0057] The first electrode layer 207 is made of metal, and the first connecting layer 206 is made of metal, wherein the metal material includes one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0058] The thickness of the first electrode layer 207 ranges from 0.1 micrometers to 100 micrometers.

[0059] In this embodiment, the thickness of the first electrode layer 207 ranges from 0.5 micrometers to 5 micrometers.

[0060] The first electrode layer 207 has a projected pattern of a circle, a rectangle, or an ellipse on the surface of the first substrate 200; the first connecting layer 206 has a projected pattern of a circle, a rectangle, or an ellipse on the surface of the first substrate 200.

[0061] In this embodiment, the projection pattern of the first electrode layer 207 on the surface of the first substrate 200 is a first rectangle; the projection pattern of the first connecting layer 206 on the surface of the first substrate 200 is a first rectangle.

[0062] The side length of the first rectangle ranges from 0.5 micrometers to 500 micrometers.

[0063] In this embodiment, the first connection layer 206 and the first electrode layer 207 are electrically connected to a portion of the first device structure 201.

[0064] In other embodiments, the first electrode layer may not be electrically connected to the first device structure, but may be electrically connected to other devices through other wiring methods.

[0065] Please refer to Figure 5 A second substrate 300 is provided, the second substrate 300 including opposing third and fourth surfaces.

[0066] The second substrate 300 has a plurality of second device structures 301 and a second isolation layer 302 on its third surface, wherein the second device structures 301 are located within the second isolation layer 302.

[0067] The second device structure 301 includes transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0068] In this embodiment, the material of the second substrate 300 includes silicon.

[0069] Please refer to Figure 6 A second dielectric structure 303 is formed on the third surface of the second substrate 300, and the second dielectric structure 303 has a third groove 304 and a fourth groove 305 arranged in parallel.

[0070] In this embodiment, the third groove 304 exposes a portion of the top surface of the second device structure 301; the fourth groove 305 exposes a portion of the top surface of the second device structure 301.

[0071] In other embodiments, the third groove exposes a portion of the top surface of the second device structure; the fourth groove exposes a portion of the top surface of the second isolation layer.

[0072] In this embodiment, the third groove 304 and the fourth groove 305 are damascus structures, that is, the third groove 304 and the fourth groove 305 include a first part (not shown) that exposes the second device structure 301, and a second part (not shown) on the remaining first part and communicating with the first part. The projected area of ​​the second part on the surface of the second substrate 300 is greater than the projected area of ​​the first part on the surface of the second substrate 300.

[0073] In other embodiments, the top and bottom areas of the third groove are equal, and the top and bottom areas of the second groove and the fourth groove are equal.

[0074] The projection pattern of the third groove 304 on the surface of the second base 300 is a circle, a rectangle, or an ellipse; the projection pattern of the fourth groove 305 on the surface of the second base 300 is a circle, a rectangle, or an ellipse.

[0075] In this embodiment, the projection pattern of the third groove 304 on the surface of the second substrate 300 is rectangular; the projection pattern of the fourth groove 305 on the surface of the second substrate 300 is rectangular.

[0076] The side length range of the rectangle is

[0077] The material of the second dielectric structure 303 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0078] In this embodiment, the material of the second dielectric structure 303 includes silicon oxide.

[0079] Next, a second connecting layer is formed in the third groove 304, and a second electrode layer is formed in the fourth groove 305. Please refer to [reference needed] for the formation process of the second connecting layer and the second electrode layer. Figure 7 and Figure 8 .

[0080] Please refer to Figure 7 A second connecting layer 306 is formed in the third groove 304, and an initial second electrode layer 307 is formed in the fourth groove 305.

[0081] The method for forming the second connecting layer 306 and the initial second electrode layer 307 includes: forming a connecting material layer (not shown) in the third groove 304, the fourth groove 305, and on the second dielectric structure 303; planarizing the connecting material layer until the surface of the second dielectric structure 303 is exposed; forming the second connecting layer 306 in the third groove 304; and forming the initial second electrode layer 307 in the fourth groove 305.

[0082] The initial second electrode layer 307 is made of metal, and the second connecting layer 306 is made of metal, wherein the metal material includes one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0083] The projection pattern of the second connecting layer 306 on the surface of the second substrate 300 is a circle, a rectangle or an ellipse.

[0084] In this embodiment, the projection pattern of the second connecting layer 306 on the surface of the second substrate 300 is a second rectangle.

[0085] In this embodiment, the side length of the second rectangle is equal to the side length of the first rectangle.

[0086] In other embodiments, the side length of the second rectangle is greater than the side length of the first rectangle by 0.1 micrometers to 100 micrometers; or the side length of the second rectangle is less than the side length of the first rectangle by 0.1 micrometers to 100 micrometers.

[0087] Please refer to Figure 8 The initial second electrode layer 307 is etched back to form the second electrode layer 308, and the top plane of the second electrode layer 308 is lower than the top surface of the second dielectric structure 303.

[0088] The method of etching back the initial second electrode layer 307 to form the second electrode layer 308 includes: forming a patterned layer (not shown) on the initial second electrode layer 307, the second interconnect layer 306, and the second dielectric structure 303, the patterned layer exposing the surface of the initial second electrode layer 307; etching the initial second electrode layer 307 using the patterned layer as a mask until a portion of the sidewall surface of the four grooves 305 is exposed, thereby forming the second electrode layer 308.

[0089] The thickness of the second electrode layer 308 ranges from 0.1 micrometers to 100 micrometers.

[0090] In this embodiment, the thickness of the second electrode layer 308 ranges from 0.5 micrometers to 5 micrometers.

[0091] The projection pattern of the second electrode layer 308 on the surface of the second substrate 300 is circular, rectangular or elliptical.

[0092] In this embodiment, the projection pattern of the second electrode layer 308 on the surface of the second substrate 300 is rectangular.

[0093] In this embodiment, the second connection layer 306 and the second electrode layer 308 are electrically connected to a portion of the second device structure 301.

[0094] In other embodiments, the second electrode layer may not be electrically connected to the second device structure, but may be electrically connected to other devices through other wiring methods.

[0095] Please refer to Figure 9 A dielectric layer 309 is formed on the surface of the second electrode layer 308.

[0096] The method for forming the dielectric layer 309 includes: forming a dielectric material layer (not shown) on the surface of the second electrode layer 308, the surface of the second connection layer 306, and the surface of the second dielectric structure 303; planarizing the dielectric material layer until the surface of the second connection layer 306 is exposed; and forming the dielectric layer 309 on the surface of the second electrode layer 308.

[0097] The processes for forming dielectric material layers include atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0098] The thickness of the dielectric layer 309 ranges from 10 Å to 10,000 Å.

[0099] The dielectric layer 309 is made of one or more of the following materials: silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0100] Please refer to Figure 10 The first surface of the first substrate 200 and the third surface of the second substrate 300 are bonded together, the first connecting layer 206 and the second connecting layer 306 are connected in a one-to-one correspondence, and the first electrode layer 207 and the dielectric layer 309 are connected in a one-to-one correspondence.

[0101] The method for bonding the first substrate 200 and the second substrate 300 includes: attaching a first surface of the first substrate 200 to a third surface of the second substrate 300, wherein the first connecting layer 206 and the second connecting layer 306 correspond one-to-one, and the dielectric layers 309 on the surfaces of the first electrode layer 207 and the second electrode layer 308 correspond one-to-one; performing heat treatment on the first substrate 200 and the second substrate 300 to bond the first connecting layer 206 and the second connecting layer 306, to attach the dielectric layers 309 on the surfaces of the first electrode layer 207 and the second electrode layer 308, and to bond the first dielectric structure 203 and the second dielectric structure 303.

[0102] The first electrode layer 207, the second electrode layer 308, and the dielectric layer 309 constitute a capacitor structure.

[0103] The method improves the utilization rate of the first electrode layer 207 and the second electrode layer 308, increases the integration of the device, and simplifies the process of fabricating the capacitor structure separately.

[0104] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 10 ,include:

[0105] A first substrate 200, the first substrate 200 including opposing first and second surfaces;

[0106] A first dielectric structure 203 located on the first surface, the first dielectric structure 203 having a first groove and a second groove arranged in parallel;

[0107] A first connecting layer 206 located in the first groove, and a first electrode layer 207 located in the second groove;

[0108] A second substrate 300 bonded to a first surface of a first substrate 200, the second substrate 300 including opposing third and fourth surfaces, the third surface of the second substrate 300 being bonded to the first surface of the first substrate 200 facing each other;

[0109] A second dielectric structure 303 is located on the third surface of the second substrate 300, and the second dielectric structure 303 has a third groove and a fourth groove arranged in parallel.

[0110] The second connecting layer 306 is located in the third groove, and the second connecting layer 306 is connected to the first connecting layer 206 in a one-to-one correspondence.

[0111] The second electrode layer 308 is located in the fourth groove. The surface of the second electrode layer 308 has a dielectric layer 309. The first electrode layer 207 and the dielectric layer 309 are connected in a one-to-one correspondence. The first electrode layer 207, the second electrode layer 308 and the dielectric layer 309 constitute a capacitor structure.

[0112] In this embodiment, the top surface of the dielectric layer 309 is flush with the surface of the second dielectric structure 303, and the top surface of the dielectric layer 309 is flush with the surface of the second interconnecting layer 306.

[0113] In this embodiment, the surface of the first connecting layer 206 is flush with the surface of the first dielectric structure 203.

[0114] In this embodiment, the thickness of the dielectric layer 309 ranges from 10 Å to 10,000 Å.

[0115] In this embodiment, the material of the first connecting layer 206 includes metal, the material of the second connecting layer 306 includes metal, the material of the first electrode layer 207 includes metal, and the material of the second electrode layer 308 includes metal. The metal material includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

[0116] In this embodiment, the dielectric layer 309 is made of one or more of the following materials: silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0117] In this embodiment, the first substrate 200 has a plurality of first device structures 201 on its first surface, and the first connection layer 206 and the first electrode layer 207 are electrically connected to a portion of the first device structures 201 respectively.

[0118] In this embodiment, the third surface of the second substrate 300 has a plurality of second device structures 301, and the second connection layer 306 and the second electrode layer 308 are electrically connected to a portion of the second device structures 301 respectively.

[0119] In this embodiment, the thickness of the first electrode layer 207 ranges from 0.1 micrometers to 100 micrometers; the thickness of the second electrode layer 308 ranges from 0.1 micrometers to 100 micrometers.

[0120] In this embodiment, the projection pattern of the first electrode layer 207 on the surface of the first substrate 200 is a circle, a rectangle, or an ellipse; the projection pattern of the second electrode layer 308 on the surface of the second substrate 300 is a circle, a rectangle, or an ellipse.

[0121] Figures 11 to 17 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0122] Please refer to Figure 11 , Figure 12 and Figure 13 , Figure 11 for Figure 12 and Figure 13 Top view, Figure 12 for Figure 11 A schematic diagram of the cross-sectional structure along section line AA1. Figure 13 for Figure 11 A schematic diagram of the cross-sectional structure along section line BB1. Figure 12 Is Figure 2 The schematic diagram shows that a first dielectric structure 203 is formed on the first surface of the first substrate 200. The first dielectric structure 203 has a first groove 404 and a second groove 405 arranged in parallel. The first dielectric structure 201 also has a plurality of fifth grooves 406, and the plurality of fifth grooves 406 are connected to adjacent second grooves 405.

[0123] For a detailed description of the first groove 404 and the second groove 405, please refer to [link / reference]. Figure 3 This will not be elaborated upon here.

[0124] Please refer to Figure 14 , Figure 15 and Figure 16 , Figure 14 for Figure 15 and Figure 16 Top view, Figure 15 for Figure 14A schematic diagram of the cross-sectional structure along section line AA1. Figure 16 for Figure 14 A cross-sectional structural diagram along the section line BB1 ​​shows that a first connecting layer 407 is formed in the first groove 404, a first electrode layer 408 is formed in the second groove 405, and a first metal layer 409 is formed in the fifth groove 406. Several first electrode layers 408 are connected through the first metal layer 409.

[0125] The first connecting layer 407, the first electrode layer 408, and the first metal layer 409 are formed simultaneously. For details on the formation process of the first connecting layer 407, the first electrode layer 408, and the first metal layer 409, please refer to [link / reference needed]. Figure 4 This will not be elaborated upon here.

[0126] A plurality of the first metal layers 409 and a plurality of the first electrode layers 408 are connected to form an inductor structure.

[0127] In this embodiment, the projection patterns of the plurality of first metal layers 409 and the plurality of first electrode layers 408 on the first substrate 200 are annular or rectangular.

[0128] Please refer to Figure 17 Provide such as Figure 7 The second substrate 300 is bonded to the first surface of the first substrate 200 and the third surface of the second substrate 300. The first connecting layer 407 and the second connecting layer 306 are connected in a one-to-one correspondence. The first electrode layer 408 and the initial second electrode layer 307 are connected in a one-to-one correspondence.

[0129] For details on the bonding process of the first surface of the first substrate 200 and the third surface of the second substrate 300, please refer to [link / reference]. Figure 10 This will not be elaborated upon here.

[0130] The initial second electrode layer 307 has no dielectric layer on its surface. The first electrode layer 408 and the initial second electrode layer 307 are connected in a one-to-one correspondence to form an inductor structure. This improves the utilization rate of the first electrode layer 408 and the initial second electrode layer 307, increases the integration of the device, and simplifies the process of fabricating the inductor structure separately.

[0131] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 17 , Figure 17 Semiconductor structure and Figure 10 The difference in semiconductor structures lies in:

[0132] In this embodiment, the surface of the initial second electrode layer 307 does not have a dielectric layer, and the initial second electrode layer 307 is connected to the first electrode layer 408 in a one-to-one correspondence.

[0133] In this embodiment, the first dielectric structure 203 also has a plurality of fifth grooves, which are connected to adjacent second grooves; a first metal layer 409 is located in the fifth groove, and a plurality of first electrode layers 408 are connected through the first metal layer 409. The first electrode layer 408, the initial second electrode layer 307 and the first metal layer 409 constitute an inductor structure.

[0134] In this embodiment, the projection patterns of the plurality of first metal layers 409 and the plurality of first electrode layers 408 on the first substrate 200 are annular or rectangular.

[0135] Figures 18 to 21 This is a schematic diagram of the semiconductor structure formation process in another embodiment of the present invention.

[0136] Please refer to Figure 18 , Figure 19 and Figure 20 , Figure 18 for Figure 19 and Figure 20 Top view, Figure 19 for Figure 18 A schematic diagram of the cross-sectional structure along the section line CC1. Figure 20 for Figure 18 A schematic diagram of the cross-sectional structure along section line DD1. Figure 19 In order to be in Figure 5 The schematic diagram is based on the structure. A second dielectric structure 303 is formed on the third surface of the second substrate 300. The second dielectric structure 303 has parallel arranged third grooves (not shown) and fourth grooves (not shown). The second dielectric structure 303 also has a plurality of sixth grooves (not shown). The plurality of sixth grooves are connected to adjacent fourth grooves. A second connecting layer 507 is formed in the third groove, a second electrode layer 508 is formed in the fourth groove, and a second metal layer 509 is formed in the sixth groove.

[0137] The second connecting layer 507, the second electrode layer 508, and the second metal layer 509 are formed simultaneously. For the specific formation process of the second connecting layer 507, the second electrode layer 508, and the second metal layer 509, please refer to [reference needed]. Figure 6 and Figure 7 This will not be elaborated upon here.

[0138] A plurality of second metal layers 509 and a plurality of second electrode layers 508 are connected to form an inductor structure.

[0139] In this embodiment, the projection patterns of the plurality of second metal layers 509 and the plurality of second electrode layers 508 on the second substrate 300 are annular or rectangular.

[0140] Please refer to Figure 21Provide such as Figures 14 to 16 The first substrate 200 is bonded to the first surface of the first substrate 200 and the third surface of the second substrate 300. The first connecting layer 407 and the second connecting layer 507 are connected in a one-to-one correspondence. The first electrode layer 408 and the second electrode layer 508 are connected in a one-to-one correspondence. The first metal layer 409 and the second metal layer 509 are connected in a one-to-one correspondence.

[0141] For details on the bonding process of the first surface of the first substrate 200 and the third surface of the second substrate 300, please refer to [link / reference]. Figure 10 This will not be elaborated upon here.

[0142] A plurality of first metal layers 409 and a plurality of first electrode layers 408 are connected to form an inductor structure, and a plurality of second metal layers 509 and a plurality of second electrode layers 508 are connected to form an inductor structure. The first electrode layers 408 and the second electrode layers 508 are connected in a one-to-one correspondence, and the first metal layers 409 and the second metal layers 509 are connected in a one-to-one correspondence, so that the plurality of first metal layers 409 and the plurality of first electrode layers 408 and the corresponding plurality of second metal layers 509 and the plurality of second electrode layers 508 form a two-layer inductor structure, thereby further increasing the area of ​​the inductor structure.

[0143] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 21 , Figure 21 Semiconductor structure and Figure 10 The difference in semiconductor structures lies in:

[0144] In this embodiment, the surface of the second electrode layer 508 does not have a dielectric layer, and the second electrode layer 508 is connected to the first electrode layer 408 in a one-to-one correspondence.

[0145] In this embodiment, the first dielectric structure 203 also has a plurality of fifth grooves, which are connected to adjacent second grooves; a first metal layer 409 is located in the fifth groove, and a plurality of first electrode layers 408 are connected through the first metal layer 409, and the first electrode layer 408 and the first metal layer 409 constitute an inductor structure.

[0146] In this embodiment, the projection patterns of the plurality of first metal layers 409 and the plurality of first electrode layers 408 on the first substrate 200 are annular or rectangular.

[0147] In this embodiment, the second dielectric structure 303 also has a plurality of sixth grooves, which are connected to adjacent fourth grooves; a second metal layer 509 is located in the sixth groove, and a plurality of second electrode layers 508 are connected through the second metal layer 509; the first metal layer 409 and the second metal layer 509 are connected in a one-to-one correspondence; the second electrode layer 508, the second metal layer 509, the first electrode layer 408 and the first metal layer 409 constitute an inductor structure.

[0148] In this embodiment, the projection patterns of the plurality of second metal layers 509 and the plurality of second electrode layers 508 on the second substrate 300 are annular or rectangular.

[0149] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first substrate, the first substrate including opposing first and second surfaces; A first dielectric structure located on a first surface, the first dielectric structure having a first groove and a second groove arranged in parallel, the first dielectric structure also having a plurality of fifth grooves, the plurality of fifth grooves being connected to adjacent second grooves; A first connecting layer located in the first groove, and a first electrode layer located in the second groove; A first metal layer is located within the fifth groove, and several first electrode layers are connected through the first metal layer; A second substrate bonded to a first surface of a first substrate, the second substrate including opposing third and fourth surfaces, wherein the third surface of the second substrate is bonded to the first surface of the first substrate facing each other; A second dielectric structure located on the third surface, wherein the second dielectric structure has a third groove and a fourth groove arranged in parallel; A second connecting layer is located within the third groove, and the second connecting layer is connected to the first connecting layer in a one-to-one correspondence; The second electrode layer is located within the fourth groove; The first electrode layer and the second electrode layer are connected in a one-to-one correspondence, and the second electrode layer, the first electrode layer and the first metal layer constitute an inductor structure.

2. The semiconductor structure as described in claim 1, characterized in that, The first connecting layer is made of metal, the second connecting layer is made of metal, the first electrode layer is made of metal, and the second electrode layer is made of metal, wherein the metal material includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

3. The semiconductor structure as described in claim 1, characterized in that, The projection pattern of the first metal layer and the first electrode layer on the first substrate is annular or rectangular.

4. The semiconductor structure as described in claim 1, characterized in that, The second dielectric structure also has a plurality of sixth grooves, which are connected to adjacent fourth grooves; a second metal layer is located in the sixth groove; a plurality of second electrode layers are connected through the second metal layer; the first metal layer and the second metal layer are connected in a one-to-one correspondence; the second electrode layer, the second metal layer, the first electrode layer and the first metal layer constitute an inductor structure.

5. The semiconductor structure as described in claim 4, characterized in that, The projection pattern of several second metal layers and several second electrode layers on the second substrate is annular or rectangular.

6. The semiconductor structure as described in claim 1, characterized in that, The first substrate has a plurality of first device structures on its first surface, and the first connection layer and the first electrode layer are electrically connected to a portion of the first device structures, respectively.

7. The semiconductor structure as described in claim 1, characterized in that, The second substrate has a plurality of second device structures on its third surface, and the second connection layer and the second electrode layer are electrically connected to a portion of the second device structures, respectively.

8. The semiconductor structure as described in claim 1, characterized in that, The thickness of the first electrode layer ranges from 0.1 micrometers to 100 micrometers; the thickness of the second electrode layer ranges from 0.1 micrometers to 100 micrometers.

9. The semiconductor structure as described in claim 1, characterized in that, The projection pattern of the first electrode layer on the first substrate surface is a circle, a rectangle, or an ellipse; the projection pattern of the second electrode layer on the second substrate surface is a circle, a rectangle, or an ellipse.

10. A method for forming a semiconductor structure, characterized in that, include: A first substrate is provided, the first substrate including opposing first and second surfaces; A first dielectric structure is formed on a first surface. The first dielectric structure has a first groove and a second groove arranged in parallel. The first dielectric structure also has a plurality of fifth grooves, and the plurality of fifth grooves are connected to adjacent second grooves. A first connecting layer is formed in a first groove, and a first electrode layer is formed in a second groove; A first metal layer is formed in the fifth groove, and several first electrode layers are connected through the first metal layer; A second substrate is provided, the second substrate including opposing third and fourth surfaces; A second dielectric structure is formed on the third surface, and the second dielectric structure has a third groove and a fourth groove arranged in parallel. A second connecting layer is formed in the third groove, and a second electrode layer is formed in the fourth groove; The first surface of the first substrate and the third surface of the second substrate are bonded together. The first connecting layer and the second connecting layer are connected in a one-to-one correspondence. The first electrode layer and the second electrode layer are connected in a one-to-one correspondence. The second electrode layer, the first electrode layer and the first metal layer constitute an inductor structure.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first connecting layer and the second connecting layer are connected in a one-to-one correspondence, and the first electrode layer and the second electrode layer are connected in a one-to-one correspondence; the method for forming the second connecting layer and the second electrode layer includes: forming a connecting material layer in a third groove, a fourth groove, and a second dielectric structure; planarizing the connecting material layer until the surface of the second dielectric structure is exposed; forming the second connecting layer in the third groove; and forming the second electrode layer in the fourth groove.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the first connecting layer and the first electrode layer includes: forming a connecting material layer in a first groove, a second groove, and on a first dielectric structure; planarizing the connecting material layer until the surface of the first dielectric structure is exposed; forming a first connecting layer in the first groove; and forming a first electrode layer in the second groove.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for bonding the first substrate and the second substrate includes: attaching a first surface of the first substrate to a third surface of the second substrate, wherein the first connecting layer and the second connecting layer correspond one-to-one, and the first electrode layer and the second electrode layer correspond one-to-one; performing heat treatment on the first substrate and the second substrate to bond the first connecting layer and the second connecting layer, to bond the surfaces of the first electrode layer and the second electrode layer, and to bond the first dielectric structure and the second dielectric structure.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first electrode layer in the second groove and the first metal layer in the fifth groove are formed simultaneously. A plurality of first electrode layers are connected through the first metal layer. The projection pattern of the plurality of first metal layers and the plurality of first electrode layers on the first substrate is annular or rectangular.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The second dielectric structure also has a plurality of sixth grooves, which are connected to adjacent fourth grooves. While forming a second electrode layer in the fourth groove, it also includes: forming a second metal layer in the sixth groove, with the plurality of second electrode layers connected through the second metal layer. The projection pattern of the plurality of second metal layers and the plurality of second electrode layers on the second substrate is annular or rectangular, and the first metal layer and the second metal layer are connected in a one-to-one correspondence.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first substrate has a plurality of first device structures on its first surface, and the first connection layer and the first electrode layer are electrically connected to a portion of the first device structures, respectively.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, The second substrate has a plurality of second device structures on its third surface, and the second connection layer and the second electrode layer are electrically connected to a portion of the second device structures, respectively.

Images