Semiconductor structure and its fabrication method, three-dimensional memory

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a three-dimensional memory, relating to the field of semiconductor chip technology, aiming to solve the problem of the high difficulty in forming stepped structures and gate trenches in 3D NAND. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a first conductive pillar, and a second conductive pillar. The second stacked structure includes at least a virtual gate layer, a second insulating layer, a select gate layer, and a third insulating layer arranged sequentially; the edges of the virtual gate layer and the select gate layer extend to a transition region; the first conductive pillar passes through the third insulating layer and is electrically connected to the select gate layer; the second conductive pillar passes through the third insulating layer, the select gate layer, and the second insulating layer and is electrically connected to the virtual gate layer. The above semiconductor structure is applied in a three-dimensional memory to realize data read and write operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, and a three-dimensional memory. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate.

[0003] In 3D NAND, memory cells are arranged three-dimensionally on a substrate. The gate consists of three parts: the bottom select gate, the middle control gate, and the top select gate (TSG). Gate spacers between the top select gates, between the middle control gates, and between the bottom select gates can be formed simultaneously. The bottom select gate, the middle control gate, and the top select gate can form a stepped structure.

[0004] However, when the material of the top-layer select gate is different from the material of the sacrificial layer corresponding to the middle-layer control gate and the bottom-layer select gate, the formation process of the step structure in 3D NAND and the formation process of the gate line slot are more complex and difficult to form. Summary of the Invention

[0005] The embodiments of this disclosure provide a semiconductor structure and its fabrication method, as well as a three-dimensional memory, aiming to solve the problem of the high difficulty in forming step structures and gate slots in 3D NAND.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a first conductive pillar, and a second conductive pillar. The first stacked structure is disposed on the substrate and includes a plurality of alternately arranged first insulating layers and a plurality of gate lines. The second stacked structure is disposed on the side of the first stacked structure away from the substrate and includes at least a dummy gate line layer, a second insulating layer, a select gate line layer, and a third insulating layer arranged sequentially. Along a first direction parallel to the substrate, the semiconductor structure includes an array region, a transition region, and a step region arranged sequentially, with the edges of the dummy gate line layer and the select gate line layer extending into the transition region. The first conductive pillar and the second conductive pillar are disposed in the transition region; the first conductive pillar passes through the third insulating layer and is electrically connected to the select gate line layer; the second conductive pillar passes through the third insulating layer, the select gate layer, and the second insulating layer and is electrically connected to the dummy gate line layer.

[0008] The semiconductor structure provided in the above embodiments of this disclosure has the edges of the virtual gate layer and the select gate layer extending to a transition region. A first conductive pillar and a second conductive pillar are disposed in the transition region. The second conductive pillar can pass through the third insulating layer, the select gate layer, and the second insulating layer, and is electrically connected to the virtual gate layer. Thus, during the fabrication of the semiconductor structure, it is unnecessary to form a stepped structure in the second stacked structure, thereby simplifying the process of forming a stepped structure in the semiconductor structure fabrication process.

[0009] In some embodiments, the semiconductor structure further includes: a plurality of first gate isolation patterns extending along the first direction, and at least one select gate isolation pattern extending along the first direction. The first gate isolation patterns penetrate the second stacked structure to divide the virtual gate layer into multiple virtual gate lines and the select gate layer into multiple select gate lines. At least one select gate isolation pattern is disposed between two adjacent first gate isolation patterns, and the select gate isolation pattern penetrates the select gate layer to divide the select gate line into multiple sub-gate lines. The select gate isolation pattern is located on the side of the virtual gate line away from the substrate.

[0010] In some embodiments, the first gate isolation pattern includes a first portion located between two adjacent selected gate lines and a second portion located between two adjacent virtual gate lines; the size of the second portion is smaller than the size of the first portion along a second direction; the second direction is parallel to the substrate and perpendicular to the first direction.

[0011] In some embodiments, between two adjacent first gate line isolation patterns, each sub-gate line is electrically connected to at least one first conductive post.

[0012] In some embodiments, between two adjacent first gate isolation patterns, a plurality of first conductive pillars are arranged along a second direction; the second direction is parallel to the substrate and perpendicular to the first direction.

[0013] In some embodiments, between two adjacent first gate line isolation patterns, at least one sub-gate line corresponds to at least one second conductive pillar, the at least one second conductive pillar passing through the corresponding sub-gate line and electrically connected to a virtual gate line located on the side of the corresponding sub-gate line closer to the substrate.

[0014] In some embodiments, between two adjacent first gate line isolation patterns, each sub-gate line corresponds to at least one second conductive pillar, the at least one second conductive pillar passing through the corresponding sub-gate line and electrically connected to the virtual gate line on the side of the sub-gate line closer to the substrate.

[0015] In some embodiments, the first grid line isolation pattern includes an air gap, which is located at least between two adjacent virtual grid lines.

[0016] In some embodiments, the selected gate layer is provided with a contact hole located in the transition region, and the second conductive post passes through the contact hole and is electrically connected to the virtual gate layer; an isolation layer is provided on the inner wall of the contact hole, and the isolation layer surrounds the portion of the second conductive post located inside the contact hole.

[0017] In some embodiments, the second conductive post is located on the side of the first conductive post away from the array region.

[0018] In some embodiments, the materials of the selected gate layer and the virtual gate layer both include polycrystalline silicon or germanium silicon.

[0019] In some embodiments, the thickness of the selected gate layer is greater than the thickness of the gate layer.

[0020] In some embodiments, the thickness of the selected gate layer is 2 to 8 times the thickness of the gate layer.

[0021] In some embodiments, the semiconductor structure further includes: a plurality of second gate isolation patterns extending along the first direction. The second gate isolation patterns penetrate the first stacked structure to divide the gate layer into multiple gate lines; the orthographic projection of the second gate isolation pattern on the substrate overlaps with the orthographic projection of the first gate isolation pattern on the substrate, and the first gate isolation pattern is connected to the second gate isolation pattern.

[0022] In some embodiments, the semiconductor structure further includes a third conductive pillar. The third conductive pillar is disposed in the stepped region; the third conductive pillar passes through the first insulating layer and is electrically connected to the gate line.

[0023] In some embodiments, the alternating plurality of first insulating layers and plurality of gate line layers extend from the array region through the transition region to the step region, and form a step structure in the step region.

[0024] In some embodiments, both the virtual grid layer and the selected grid layer extend from the array region to the boundary line between the transition region and the step region.

[0025] In some embodiments, the semiconductor structure further includes a plurality of first channel structures and a plurality of second channel structures. The plurality of first channel structures are disposed in the array region and penetrate the first stacked structure; each first channel structure includes a barrier layer, a charge storage layer, a tunnel insulating layer, and a first channel layer. The plurality of second channel structures are disposed in the array region and penetrate the second stacked structure; each second channel structure includes a gate dielectric layer and a second channel layer; wherein, a second channel structure is correspondingly disposed on the side of each first channel structure away from the substrate, and the first channel layer of the first channel structure is electrically connected to the second channel layer of the corresponding second channel structure.

[0026] In some embodiments, the radial dimension of the second channel structure is smaller than the radial dimension of the corresponding first channel structure.

[0027] On the other hand, a method for fabricating a semiconductor structure is provided, comprising: forming a first stacked structure on a substrate; forming a second stacked structure on a side of the first stacked structure away from the substrate; the second stacked structure comprising at least a virtual gate layer, a second insulating layer, a select gate layer and a third insulating layer disposed sequentially; forming a first conductive pillar and a second conductive pillar; the first conductive pillar passing through the third insulating layer and electrically connected to the select gate layer; the second conductive pillar passing through the third insulating layer, the select gate layer and the second insulating layer and electrically connected to the virtual gate layer.

[0028] In some embodiments, prior to forming the first conductive pillar and the second conductive pillar, the preparation method further includes:

[0029] The third insulating layer, the select gate layer, and the second insulating layer are etched to form a plurality of contact holes, a plurality of first slits, and at least one second slit that expose the virtual gate layer; the plurality of first slits divide the select gate layer into a plurality of select gate lines; at least one second slit is formed between two adjacent first slits, and the second slit divides the select gate line into a plurality of sub-gate lines.

[0030] A first dielectric layer is formed; the first dielectric layer fills the plurality of contact holes, the plurality of first slits and the at least one second slit, the first dielectric layer filled in the at least one second slit forms a selective gate isolation pattern, and the first dielectric layer filled in the plurality of contact holes forms an isolation layer.

[0031] A third slit is formed that penetrates the virtual gate layer; the orthographic projection of the third slit on the substrate overlaps with the orthographic projection of the first slit on the substrate, and the third slit divides the virtual gate layer into multiple virtual gate lines.

[0032] A second dielectric layer is formed; the second dielectric layer fills the third slit, and the first dielectric layer filled in the first slit and the second dielectric layer filled in the third slit form a first gate line isolation pattern.

[0033] In some embodiments, forming the second dielectric layer includes:

[0034] A second dielectric layer is deposited on the bottom and sidewalls of the third slit at a first deposition rate.

[0035] After depositing a second dielectric layer of a predetermined thickness at the bottom of the third slit, a second dielectric layer is deposited in the third slit at a second deposition rate to form a first gate line isolation pattern including an air gap.

[0036] Wherein, the second deposition rate is greater than the first deposition rate; the air gap is located between at least two adjacent virtual grid lines.

[0037] In some embodiments, along a first direction parallel to the substrate, the semiconductor structure includes an array region, a transition region, and a step region arranged sequentially; forming the first stacked structure on the substrate includes:

[0038] Multiple first insulating layers and multiple sacrificial layers are formed alternately stacked on the substrate.

[0039] The plurality of first insulating layers and the plurality of sacrificial layers are etched to form a stepped structure in the stepped region.

[0040] A plurality of fourth slits are formed, the fourth slits extending along the first direction and penetrating the plurality of first insulating layers and the plurality of sacrificial layers.

[0041] The plurality of fourth slits are used to replace the plurality of sacrificial layers with the plurality of gate line layers.

[0042] In some embodiments, the thickness of the selected gate layer is greater than the thickness of the gate layer.

[0043] In some embodiments, the thickness of the selected gate layer is 2 to 8 times the thickness of the gate layer.

[0044] In some embodiments, along a first direction parallel to the substrate, the semiconductor structure includes an array region, a transition region, and a step region arranged sequentially; in the step of forming a second stacked structure on the side of the first stacked structure away from the substrate, the dummy gate layer and the selected gate layer cover the array region, the transition region, and the step region; before forming the first conductive pillar and the second conductive pillar, the fabrication method further includes:

[0045] Remove the portion of the selected gate layer that covers the stepped area.

[0046] Remove the portion of the virtual grid layer that covers the step area.

[0047] In some embodiments, before forming a second stacked structure on the side of the first stacked structure away from the substrate, the fabrication method further includes: forming a plurality of first channel structures; the first channel structures penetrate the first stacked structure, and the first channel structures include a barrier layer, a charge storage layer, a tunneling layer and a first channel layer.

[0048] Before forming the first conductive pillar and the second conductive pillar, the fabrication method further includes: forming a plurality of second channel structures; the second channel structures penetrate the second stacked structure, and the second stacked structure includes a gate dielectric layer and a second channel layer.

[0049] In this configuration, a second channel structure is provided on the side of each first channel structure away from the substrate, and the first channel layer of the first channel structure is electrically connected to the second channel layer of the corresponding second channel structure.

[0050] In some embodiments, the materials of the selected gate layer and the virtual gate layer both include polycrystalline silicon or germanium silicon.

[0051] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure and peripheral circuitry as described in some of the embodiments above, wherein the peripheral circuitry is electrically connected to the semiconductor structure.

[0052] It is understood that the beneficial effects of the semiconductor structure preparation method and three-dimensional memory provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0054] Figure 1A This is a cross-sectional view of a semiconductor structure in the related technology;

[0055] Figure 1B This is a schematic diagram of the stepped structure of a semiconductor structure in related technologies;

[0056] Figure 2A This is a top view of a semiconductor structure according to some embodiments;

[0057] Figure 2B for Figure 2A The semiconductor structure shown is a cross-sectional view along section line A-A'.

[0058] Figure 3 for Figure 2A A cross-sectional view of a semiconductor structure along section line N-N' is shown.

[0059] Figure 4 for Figure 2A A cross-sectional view of another semiconductor structure along section line N-N' is shown;

[0060] Figure 5 for Figure 2A A cross-sectional view of a semiconductor structure along section line M-M' is shown.

[0061] Figure 6 for Figure 2A The diagram shows a cross-sectional view of a semiconductor structure along section line B-B'.

[0062] Figure 7 for Figure 2A A cross-sectional view of another semiconductor structure along section line B-B' is shown.

[0063] Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments;

[0064] Figure 9 This is a step diagram illustrating the preparation of a first layered structure according to some embodiments;

[0065] Figure 10 This is a step diagram illustrating the preparation of a second layered structure according to some embodiments;

[0066] Figure 11 This is a flowchart illustrating a method for fabricating another semiconductor structure according to some embodiments;

[0067] Figures 12-15 To and Figure 11 The flowchart of the preparation method shown corresponds to the step diagram.

[0068] Figure 16 This is a flowchart of a method for preparing a second dielectric according to some embodiments;

[0069] Figure 17 This is a flowchart of a method for forming a first layered structure according to some embodiments;

[0070] Figures 18-22 To and Figure 17 The flowchart of the preparation method shown corresponds to the step diagram.

[0071] Figure 23 This is a flowchart illustrating a method for fabricating another semiconductor structure according to some embodiments;

[0072] Figure 24 and Figure 25 To and Figure 23 The flowchart of the preparation method shown corresponds to the step diagram.

[0073] Figure 26 This is a flowchart illustrating a method for fabricating another semiconductor structure according to some embodiments;

[0074] Figure 27 and Figure 28 To and Figure 26 The flowchart of the preparation method shown corresponds to the step diagram.

[0075] Figure 29 This is a cross-sectional view of a three-dimensional memory according to some embodiments. Detailed Implementation

[0076] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0077] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0078] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0079] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0080] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0081] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0082] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0083] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0084] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0085] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0086] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0087] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0088] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0089] like Figure 1AAs shown, in the related technology, a semiconductor structure is provided with multiple top select gate layers 01, and the material of the top select gate layer 01 is polysilicon, while the materials of the middle select gate layer 02 and the bottom select gate layer 03 are both metals. Because the material of the top select gate layer 01 is polysilicon, the resistance on the top select gate line is relatively high.

[0090] Meanwhile, the gate line slot 04 passes through the top selection gate layer 01, the middle selection gate layer 02, and the bottom selection gate layer 03. Thus, when forming the gate line slot 04, the top selection gate layer 01, the sacrificial layer 05, and the insulating layer 06 must be etched simultaneously, making the etching process complex and difficult.

[0091] Figure 1B This is a partial stepped structure in a semiconductor structure in related technologies, in which the multilayer top select gate layer 01 and the multilayer sacrificial layer 05 form a stepped structure. Therefore, when forming the stepped structure, it is also necessary to etch the top select gate layer 01, the sacrificial layer 05, and the insulating layer 06. The etching process is also relatively complex and difficult.

[0092] Based on this, this disclosure provides a semiconductor structure 100. Please refer to [link / reference]. Figure 2A and Figure 2B , Figure 2A This is a top view of a semiconductor structure 100 provided in some embodiments of this disclosure. Figure 2B for Figure 2A A cross-sectional view of the semiconductor structure 100 along section line A-A'.

[0093] like Figure 2A and Figure 2B As shown, the semiconductor structure 100 includes a substrate 10, a first stacked structure 20, a second stacked structure 30, a first conductive pillar 40, and a second conductive pillar 50.

[0094] The first stacked structure 20 is disposed on the substrate 10. The first stacked structure 20 includes a plurality of alternating first insulating layers 21 and a plurality of gate line layers 22.

[0095] The second stacked structure 30 is disposed on the side of the first stacked structure 20 away from the substrate 10. The second stacked structure 30 includes at least a virtual gate layer 31, a second insulating layer 32, a select gate layer 33, and a third insulating layer 34 disposed sequentially. Along a first direction X parallel to the substrate 10, the semiconductor structure 100 includes an array region 101, a transition region 102, and a step region 103 arranged sequentially. The edges of the virtual gate layer 31 and the select gate layer 33 extend to the transition region 102.

[0096] The first conductive post 40 and the second conductive post 50 are disposed in the transition region 102. The first conductive post 40 passes through the third insulating layer 34 and is electrically connected to the selection gate layer 33. The second conductive post 50 passes through the third insulating layer 34, the selection gate layer 33 and the second insulating layer 32, and is electrically connected to the virtual gate layer 31.

[0097] For example, the first conductive post 40 is configured to bring out the select gate layer 33, thereby facilitating the provision of electrical signals to the select gate layer 33. The second conductive post 50 is configured to bring out the dummy gate layer 31, thereby facilitating the provision of electrical signals to the dummy gate layer 31.

[0098] Since the second conductive post 50 passes through the third insulating layer 34, the selected gate layer 33, and the second insulating layer 32 and is electrically connected to the virtual gate layer 31, there is no need to set a step structure in the second stacked structure 30. Only the step structure needs to be set in the first stacked structure 20, which simplifies the fabrication process of the steps of the semiconductor structure 100.

[0099] For example, the memory cell string can be controlled by a virtual gate layer 31 and a selected gate layer 33, with the virtual gate layer 31 configured to reduce interference from gate-induced drain leakage.

[0100] For example, the material of the first insulating layer 21 may include oxides, such as silicon oxide.

[0101] The material of the gate layer 22 may include metals such as tungsten, metal nitrides, and / or metal silicides. In some examples, the gate layer 22 may have a multilayer structure including metal nitrides such as tungsten nitrides and metals such as tungsten. Of course, the material of the gate layer 22 in this disclosure is not limited to these.

[0102] For example, the thickness of the gate layer 22 along the third direction Z perpendicular to the substrate 10 can be 20nm to 30nm. For instance, the thickness of the gate layer 22 can be 20nm, 22nm, 25nm, 28nm, 30nm, etc.

[0103] It should be noted that the number of gate line layers 22 is not limited in this disclosure. For example, the first stacked structure 20 may include 16 gate line layers 22, or 24 gate line layers 22, or 32 gate line layers 22, or 48 gate line layers 22, or more than 48 gate line layers 22, etc.

[0104] For example, the materials of the second insulating layer 32 and the third insulating layer 34 may include oxides, such as silicon oxide.

[0105] In some embodiments, such as Figure 2BAs shown, the thickness of the selected gate layer 33 can be greater than the thickness of the gate layer 22. This configuration results in a larger cross-sectional area for the selected gate layer 33, which helps to reduce the resistance on the selected gate layer 33 and lower power consumption.

[0106] For example, the thickness of the gate layer 33 can be selected from 50nm to 200nm. For instance, the thickness of the gate layer 33 can be 50nm, 100nm, 150nm, 200nm, etc.

[0107] For example, the thickness of the selected gate layer 33 can be 2 to 8 times that of the gate layer 22. This configuration results in a larger thickness of the selected gate layer 33 and a lower resistance on it. Simultaneously, the fabrication cost of the selected gate layer 33 is lower, which helps reduce the fabrication cost of the semiconductor structure 100.

[0108] For example, the materials of the virtual gate layer 31 and the selected gate layer 33 may include polysilicon or germanium silicon.

[0109] At this point, only the gate dielectric layer and the channel layer can be provided in the channel structure through the second stacked structure 30, without the need for a charge storage layer and a tunneling layer, thereby constructing a simple metal-oxide-semiconductor (MOS) transistor and reducing the fabrication cost of the channel structure in the second stacked structure 30. Of course, the materials of the virtual gate layer 31 and the selected gate layer 33 in this disclosure are not limited to these, and can also be other materials that can simplify the channel structure through the second stacked structure 30.

[0110] For example, the materials of the first conductive post 40 and the second conductive post 50 may include metals (e.g., tungsten, copper, aluminum, etc.), metal silicides, metal nitrides, and / or doped polycrystalline silicon, etc.

[0111] In some examples, the material of the first conductive post 40 can be the same as the material of the second conductive post 50. In other examples, the material of the first conductive post 40 can be different from the material of the second conductive post 50.

[0112] It should be noted that the shape of the first conductive post 40 and the second conductive post 50 is not limited in this disclosure. For example, both the first conductive post 40 and the second conductive post 50 can be cylinders.

[0113] As can be seen from the above, in the semiconductor structure 100 provided in some embodiments of this disclosure, the edges of the virtual gate layer 31 and the select gate layer 33 extend to the transition region 102. A first conductive pillar 40 and a second conductive pillar 50 are disposed in the transition region 102. The second conductive pillar 50 can pass through the third insulating layer 34, the select gate layer 33, and the second insulating layer 32, and is electrically connected to the virtual gate layer 31. Thus, during the fabrication of the semiconductor structure 100, it is unnecessary to form a stepped structure in the second stacked structure 30, thereby simplifying the process of forming the stepped structure in the semiconductor structure 100.

[0114] like Figure 2A , Figure 3 and Figure 4 As shown, the semiconductor structure 100 also includes a plurality of first gate isolation patterns 60 extending along the first direction X, and at least one select gate isolation pattern 70 extending along the first direction X.

[0115] The first grid isolation pattern 60 penetrates the second stacked structure 30 to divide the virtual grid layer 31 into multiple virtual grid lines 311 and the selection grid layer 33 into multiple selection grid lines 331.

[0116] At least one selection gate isolation pattern 70 is provided between two adjacent first gate line isolation patterns 60. The selection gate isolation pattern 70 penetrates the selection gate line layer 33 to divide the selection gate line 331 into multiple sub-gate lines 332. The selection gate isolation pattern 70 is located on the side of the virtual gate line 311 away from the substrate 10.

[0117] "At least one selective gate isolation pattern 70 is provided between two adjacent first gate isolation patterns 60". For example, only one selective gate isolation pattern 70 is provided between two adjacent first gate isolation patterns 60. Or, multiple selective gate isolation patterns 70 are provided between two adjacent first gate isolation patterns 60. Figure 2A The following is an example of setting three selection gate isolation patterns 70 between two adjacent first gate line isolation patterns 60.

[0118] It should be noted that the material of the first gate isolation pattern 60 may include insulating materials, such as silicon oxide. However, the material of the first gate isolation pattern 60 in this disclosure is not limited to this.

[0119] The material chosen for the gate isolation pattern 70 may also include insulating materials, such as silicon oxide. However, the materials chosen for the gate isolation pattern 70 in this disclosure are not limited to these.

[0120] In some examples, the material of the first gate isolation pattern 60 can be the same as the material of the selected gate isolation pattern 70. In other examples, the material of the first gate isolation pattern 60 can be different from the material of the selected gate isolation pattern 70.

[0121] As can be seen from the above, the second stacked structure 30 is located on the side of the first stacked structure 20 away from the substrate 10, and the second stacked structure 30 can be fabricated after the first stacked structure 20 is formed. Therefore, in the second stacked structure 30, the slit containing the first gate isolation pattern 60 can only pass through the second stacked structure 30. That is, when forming the slit containing the first gate isolation pattern 60, only the polysilicon layer and the insulating layer in the second stacked structure 30 need to be etched, thereby reducing the etching difficulty of the first gate isolation pattern 60, simplifying the fabrication process of the first gate isolation pattern 60, and further simplifying the fabrication process of the semiconductor structure 100.

[0122] In some embodiments disclosed herein, by providing at least one selection gate isolation pattern 70 between two adjacent first gate line isolation patterns 60, the selection gate line 331 is divided into multiple sub-gate lines 332, thereby enabling higher control precision when controlling multiple memory cells corresponding to the selection gate line 331.

[0123] In one embodiment, such as Figure 2A As shown, the selected gate isolation pattern 70 may include a first extension 71 located in the array region 101, and a second extension 72 connected to the first extension 71 and located in the transition region 102. The first extension 71 extends in a serpentine manner along the first direction X, and the second extension 72 extends in a straight manner along the first direction X.

[0124] Thus, when the semiconductor structure 100 also includes a plurality of second channel structures 92 located in the array region 101 and penetrating the second stacked structure, the first extension 71 can be arranged between two adjacent second channel structures 92, thereby avoiding occupying additional area of ​​the second stacked structure 30 in the second direction Y, which is beneficial to improving the utilization rate of the second stacked structure 30 and realizing the miniaturization of the semiconductor structure 100.

[0125] In some embodiments, such as Figure 3 and Figure 4 As shown, the first grid line isolation pattern 60 includes an air gap 61, which is located at least between two adjacent virtual grid lines 311.

[0126] Among them, such as Figure 3 As shown, "air gap 61 is located at least between two adjacent virtual grid lines 311", for example, air gap 61 can be located only between two adjacent virtual grid lines 311. Or, as... Figure 4 As shown, "the air gap 61 is located at least between two adjacent virtual grid lines 311". For example, the air gap 61 can be located between two adjacent virtual grid lines 311, and the air gap 61 can also be located between two adjacent selection grid lines 331.

[0127] In this way, an air gap 61 is provided between two adjacent virtual gate lines 311, which reduces the dielectric constant of the first gate line isolation pattern 60 between the two adjacent virtual gate lines 311, enhances the insulation performance, and reduces the coupling between the two adjacent virtual gate lines 311, thereby helping to avoid crosstalk between signals transmitted on the two adjacent virtual gate lines 311.

[0128] Similarly, when the air gap 61 in the first gate isolation pattern 60 is also located between two adjacent selection gate lines 331, the dielectric constant of the first gate isolation pattern 60 between the two adjacent selection gate lines 331 decreases, the insulation performance is enhanced, the coupling between the two adjacent selection gate lines 331 is reduced, which helps to avoid crosstalk between the two adjacent selection gate lines 331.

[0129] In some embodiments, such as Figure 3 As shown, between two adjacent first gate line isolation patterns 60, each sub-gate line 332 is electrically connected to at least one first conductive post 40. Thus, the drain select signal line can be electrically connected to the sub-gate line 332 via at least one first conductive post 40, enabling control of the multiple memory cells connected to the sub-gate line 332.

[0130] like Figure 3 and Figure 4 As shown, "each sub-gate line 332 is electrically connected to at least one first conductive post 40", for example, each sub-gate line 332 is electrically connected to one first conductive post 40.

[0131] Alternatively, "each sub-gate line 332 is electrically connected to at least one first conductive post 40", for example, each sub-gate line 332 can be electrically connected to multiple first conductive posts 40.

[0132] like Figure 2A As shown, in some examples, between two adjacent first gate isolation patterns 60, a plurality of first conductive pillars 40 are arranged along a second direction Y. The second direction Y is parallel to the substrate and perpendicular to the first direction X. This helps to reduce the size of the arrangement area of ​​the plurality of first conductive pillars 40 in the second direction and improves the effective utilization of the insulating layer above the selected gate layer 33.

[0133] In some embodiments, such as Figure 5 As shown, between two adjacent first gate line isolation patterns 60, at least one sub-gate line 332 corresponds to at least one second conductive post 50. At least one second conductive post 50 passes through the corresponding sub-gate line 332 and is electrically connected to a virtual gate line 311 located on the side of the corresponding sub-gate line 332 near the substrate 10.

[0134] It should be noted that "between two adjacent first grid line isolation patterns 60, at least one sub-grid line 332 corresponds to at least one second conductive post 50". For example, between two adjacent first grid line isolation patterns 60, only one sub-grid line 332 corresponds to one or more second conductive posts 50.

[0135] Or, such as Figure 5 As shown, "between two adjacent first grid line isolation patterns 60, at least one sub-grid line 332 corresponds to at least one second conductive post 50". For example, it can also be that between two adjacent first grid line isolation patterns 60, each of the multiple sub-grid lines 332 corresponds to one or more second conductive posts 50.

[0136] With this configuration, the second conductive post 50 can pass through the sub-gate line 332 and be electrically connected to the virtual gate line 311, so that when fabricating the semiconductor structure 100, the step structure only needs to be formed in the first stacked structure 20, without the need to form the step structure in the second stacked structure 30, thereby simplifying the step formation process in the semiconductor structure 100.

[0137] In some examples, such as Figure 5 As shown, between two adjacent first gate line isolation patterns 60, each sub-gate line 332 corresponds to at least one second conductive post 50. The at least one second conductive post 50 passes through the corresponding sub-gate line 332 and is electrically connected to the virtual gate line 311 located on the side of the sub-gate line 332 near the substrate 10.

[0138] In this way, multiple second conductive posts 50 can pass through multiple sub-grid lines 332 and be electrically connected to the same virtual grid line 311 to provide driving electrical signals to the virtual grid line 311 and improve the driving speed of the virtual grid line 311.

[0139] In some examples, such as Figure 2A As shown, between two adjacent first gate line isolation patterns 60, a plurality of second conductive pillars 50 are arranged along the second direction Y. This helps to reduce the size of the arrangement area of ​​the plurality of second conductive pillars 500 in the second direction and improves the effective utilization rate of the insulating layer above the selected gate line layer 33.

[0140] In some embodiments, such as Figure 5 As shown, the first gate isolation pattern 60 includes a first portion 62 located between two adjacent selected gate lines 331, and a second portion 63 located between two adjacent virtual gate lines 311. Along the second direction Y, the size of the second portion 63 is smaller than the size of the first portion 62.

[0141] Thus, during the formation of the first gate isolation pattern 60, the size of the first slit 35 is relatively large along the second direction Y, and the thickness of the first dielectric layer 37 in the first slit 35 is relatively thin when the first dielectric layer 37 is deposited, making it easier to etch the third slit 38 and reducing the difficulty of the process.

[0142] In some embodiments, such as Figure 2B and Figure 5 As shown, a contact hole 333 is provided in the selected gate layer 33, located in the transition region 102. The second conductive post 50 passes through the contact hole 333 and is electrically connected to the virtual gate layer 31. An isolation layer 3331 is covered on the inner wall of the contact hole 333, and the isolation layer 3331 surrounds the portion of the second conductive post 50 located inside the contact hole 333.

[0143] It should be noted that this disclosure does not limit the shape and size of the contact hole 333. In some examples, such as Figure 2A As shown, the orthographic projection of the contact hole 333 onto the substrate 10 can be approximately circular. In other examples, the orthographic projection of the contact hole 333 onto the substrate 10 can be approximately rectangular.

[0144] Here, "approximately" refers to both the described shape and shapes that are generally similar to the described shape. For example, "approximately circular" can be a circle or a shape that is generally similar to a circle, where at least some of the boundaries of the shape are allowed to be different from at least some of the boundaries of a circle, that is, at least some of the boundaries of the shape are allowed to be non-curved, such as at least some of the boundaries of the shape being serrated.

[0145] The material of the isolation layer 3331 may include an insulating material, such as silicon oxide. This disclosure is not limited to this.

[0146] This avoids the second conductive post 50 from contacting the inner wall of the contact hole 333, thereby preventing the second conductive post 50 from being electrically connected to the selection gate layer 33, ensuring accurate control of the virtual gate line 311 and the selection gate line 331, and avoiding mutual interference of signals.

[0147] In some embodiments, such as Figure 2A and Figure 2B As shown, the second conductive post 50 is located on the side of the first conductive post 40 away from the array region 101.

[0148] In other embodiments, the second conductive post 50 may also be located on the side of the first conductive post 40 adjacent to the array region 101.

[0149] This configuration helps to prevent the first conductive post 40 and the second conductive post 50 from coming into contact, which would affect the normal control of the selected gate line 331 (or sub-gate line) and the virtual gate line 311 in the semiconductor structure.

[0150] In some embodiments, such as Figure 2A and Figure 5 As shown, the semiconductor structure 100 also includes a plurality of second gate isolation patterns 80 extending along a first direction X. The second gate isolation patterns 80 penetrate the first stacked structure 20 to divide the gate layer 22 into a plurality of gate lines 221. The orthographic projection of the second gate isolation pattern 80 on the substrate 10 overlaps with the orthographic projection of the first gate isolation pattern 60 on the substrate 10, and the first gate isolation pattern 60 is connected to the second gate isolation pattern 80.

[0151] Wherein, “the orthographic projection of the second gate isolation pattern 80 on the substrate 10 overlaps with the orthographic projection of the first gate isolation pattern 60 on the substrate 10”, for example, the boundary of the orthographic projection of the second gate isolation pattern 80 on the substrate 10 completely overlaps with the boundary of the orthographic projection of the first gate isolation pattern 60 on the substrate 10.

[0152] Alternatively, "the orthogonal projection of the second gate isolation pattern 80 on the substrate 10 overlaps with the orthogonal projection of the first gate isolation pattern 60 on the substrate 10", for example, the orthogonal projection of the second gate isolation pattern 80 on the substrate 10 may be located inside the orthogonal projection of the first gate isolation pattern 60 on the substrate 10.

[0153] Or, as Figure 2A As shown, "the orthogonal projection of the second gate isolation pattern 80 on the substrate 10 overlaps with the orthogonal projection of the first gate isolation pattern 60 on the substrate 10". For example, it can also be that the orthogonal projection of the first gate isolation pattern 60 on the substrate 10 is located inside the orthogonal projection of the second gate isolation pattern 80 on the substrate 10.

[0154] It should be noted that the material of the second gate isolation pattern 80 may include an insulating material, such as an oxide. For example, the material of the second gate isolation pattern 80 may include silicon oxide.

[0155] In this way, the first gate isolation pattern 60 and the second gate isolation pattern 80 are interconnected, dividing the semiconductor structure 100 into multiple memory cell blocks, thereby increasing the storage density in the semiconductor structure 100.

[0156] In some embodiments, such as Figure 6 As shown, the semiconductor structure 100 also includes a third conductive post 90. The third conductive post 90 is disposed in the step region 103. The third conductive post 90 passes through the first insulating layer 21 and is electrically connected to the gate line 221.

[0157] The material of the third conductive post 90 may include metals (e.g., tungsten, copper, aluminum, etc.), metal silicides, metal nitrides, and / or doped polycrystalline silicon. The material of the third conductive post 90 in this disclosure is not limited to these.

[0158] By setting multiple third conductive posts 90 in the step area 103, multiple gate lines 221 can be connected to the selection line, thereby realizing data writing and erasing of the storage cell.

[0159] In some embodiments, such as Figure 6 As shown, multiple alternating first insulating layers 21 and multiple gate line layers 22 extend from the array region 101 through the transition region 102 to the step region 103, forming a step structure in the step region 103. The step structure facilitates the electrical connection of the third conductive post 90 with the gate lines 221 located at different heights, simplifying the wiring in the semiconductor structure 100.

[0160] In some embodiments, such as Figure 7 As shown, the semiconductor structure 100 also includes a plurality of first channel structures 91 and a plurality of second channel structures 92.

[0161] Multiple first channel structures 91 are disposed in the array region 101 and penetrate the first stacked structure 20. The first channel structure 91 includes a barrier layer 911, a charge storage layer 912, a tunneling layer 913 and a first channel layer 914.

[0162] Multiple second channel structures 92 are disposed in the array region 101 and penetrate the second stacked structure 30. The second channel structure 92 includes a gate dielectric layer 921 and a second channel layer 922.

[0163] In this configuration, a second channel structure 92 is provided on the side of each first channel structure 91 that is away from the substrate 10, and the first channel layer 914 of the first channel structure 91 is electrically connected to the second channel layer 922 of the corresponding second channel structure 92.

[0164] It should be noted that the barrier layer 911 is used to prevent charge from being transferred to the gate layer 22. The charge storage layer 912 covers the barrier layer 911 and is used to store charge. The tunneling layer 913 covers the charge storage layer 912. In this case, during a write operation, when the voltage of the word line (i.e., the gate line in the gate layer 22 closest to the substrate 10) is higher than the tunneling voltage, electrons from the first channel layer 914 reach the charge storage layer 912 via the tunneling layer 913, thereby converting data into charge and storing it in the charge storage layer 912.

[0165] The barrier layer 911 may include a single layer, for example, a SiO2 layer. The barrier layer 911 may also include multiple layers, for example, a SiO2 and Al2O3 stack. The charge storage layer 912 may include a single layer, for example, a SiN layer. The charge storage layer 912 may also include multiple layers, for example, a SiN, SiON, and SiN stack. The tunneling layer 913 may include multiple layers, for example, a SiO, SiON, and SiO stack.

[0166] The material of the gate dielectric layer 921 may include silicon oxide, but this disclosure is not limited thereto. The material of the second channel layer 922 includes a semiconductor material. Exemplarily, the material of the second channel layer 922 includes polycrystalline silicon and / or monocrystalline silicon.

[0167] This disclosure does not limit the number or arrangement of the first channel structure 91 and the second channel structure 92. For example, the first channel structure 91 and the second channel structure 92 can be as follows: Figure 2A As shown, they are arranged in array area 101.

[0168] In some embodiments disclosed herein, the materials of the virtual gate layer 31 and the select gate layer 33 include polysilicon or germanium silicon. Therefore, the second channel structure 92 only needs to have a second channel layer 922 electrically connected to the first channel layer 914 in the first channel structure 91, and a gate dielectric layer 921 spaced between the second channel layer 922 and the select gate layer 33 and between the second channel layer 922 and the virtual gate layer 31. There is no need to provide a charge storage layer and a tunneling layer, thereby enabling the construction of a simple MOS transistor and reducing the manufacturing cost of the second channel structure 92.

[0169] In some embodiments, see Figure 2A The radial dimension of the second channel structure 92 is smaller than the radial dimension of the corresponding first channel structure 91.

[0170] By setting it in this way, the spacing between two adjacent second channel structures 92 is greater than the spacing between the two first channel structures 91 located on the side of the two adjacent second channel structures 92 that are close to the substrate 10 and respectively corresponding to the two adjacent second channel structures 92, thereby facilitating the setting of a first gate isolation pattern 60 and / or a selected gate isolation pattern 70 between two adjacent second channel structures 92.

[0171] like Figure 8 As shown, this disclosure also provides a method for fabricating a semiconductor structure 100. The fabrication method includes:

[0172] S1, such as Figure 9 As shown, a first stacked structure 20 is formed on the substrate 10.

[0173] S2, such as Figure 10 As shown, a second stacked structure 30 is formed on the side of the first stacked structure 20 away from the substrate 10. The second stacked structure 30 includes at least a virtual gate layer 31, a second insulating layer 32, a select gate layer 33, and a third insulating layer 34 arranged sequentially.

[0174] The materials of the virtual gate layer 31 and the selected gate layer 33 can be polysilicon or germanium silicon.

[0175] S3, such as Figure 2B As shown, a first conductive post 40 and a second conductive post 50 are formed. The first conductive post 40 passes through the third insulating layer 34 and is electrically connected to the select gate layer 33. The second conductive post 50 passes through the third insulating layer 34, the select gate layer 33, and the second insulating layer 32 and is electrically connected to the virtual gate layer 31.

[0176] For example, the materials of the first conductive post 40 and the second conductive post 50 may include metals (e.g., tungsten, copper, aluminum, etc.), metal silicides, metal nitrides, and / or doped polycrystalline silicon, etc.

[0177] It should be noted that the material of the first conductive post 40 can be the same as the material of the second conductive post 50. Alternatively, the material of the first conductive post 40 can be different from the material of the second conductive post 50.

[0178] The shape of the first conductive post 40 and the second conductive post 50 is not limited in this disclosure. For example, both the first conductive post 40 and the second conductive post 50 can be cylinders.

[0179] In some embodiments of this disclosure, the second conductive post 50 can pass through the third insulating layer 34, the select gate layer 33, and the second insulating layer 32, and be electrically connected to the virtual gate layer 31. Thus, during the fabrication of the semiconductor structure 100, it is unnecessary to form a stepped structure in the second stacked structure 30, thereby simplifying the process for forming the stepped structure of the semiconductor structure 100.

[0180] In some embodiments, such as Figure 11 As shown, before step S3 and the formation of the first conductive pillar 40 and the second conductive pillar 50, the preparation method further includes:

[0181] S31, such as Figure 12 As shown, the third insulating layer 34, the select gate layer 33, and the second insulating layer 32 are etched to form a plurality of contact holes 333, a plurality of first slits 35, and at least one second slit 36 ​​exposing the virtual gate layer 31. The plurality of first slits 35 divide the select gate layer 33 into a plurality of select gate lines 331. At least one second slit 36 ​​is formed between two adjacent first slits 35, and the second slit 36 ​​divides the select gate line 331 into a plurality of sub-gate lines 332.

[0182] S32, such as Figure 13 As shown, a first dielectric layer 37 is formed. The first dielectric layer 37 fills a plurality of contact holes 333, a plurality of first slits 35 and at least one second slit 36. The first dielectric layer 37 filled in the at least one second slit 36 ​​forms a selective gate isolation pattern 70, and the first dielectric layer 37 filled in the plurality of contact holes forms an isolation layer 3331.

[0183] S33, such as Figure 14 As shown, a third slit 38 is formed that penetrates the virtual gate layer 31. The orthographic projection of the third slit 38 on the substrate 10 overlaps with the orthographic projection of the first slit 35 on the substrate 10, and the third slit 38 divides the virtual gate layer 31 into multiple virtual gate lines 311.

[0184] S34, such as Figure 15 As shown, a second dielectric layer 39 is formed. The second dielectric layer 39 fills the third slit 38, and the first dielectric layer 37 filled in the first slit 35 and the second dielectric layer 39 filled in the third slit 38 form a first gate line isolation pattern 60.

[0185] The first dielectric layer 37 can be made of an insulating material, such as an oxide. For example, the first dielectric layer 37 can be made of silicon oxide.

[0186] It should be noted that "the orthographic projection of the third slit 38 on the substrate 10 overlaps with the orthographic projection of the first slit 35 on the substrate 10" can mean that the boundary of the orthographic projection of the third slit 38 on the substrate 10 completely overlaps with the boundary of the orthographic projection of the first slit 35 on the substrate 10.

[0187] Alternatively, "the orthographic projection of the third slit 38 on the substrate 10 overlaps with the orthographic projection of the first slit 35 on the substrate 10" can mean that the orthographic projection of the third slit 38 on the substrate 10 is located inside the orthographic projection of the first slit 35 on the substrate 10.

[0188] Alternatively, "the orthographic projection of the third slit 38 on the substrate 10 overlaps with the orthographic projection of the first slit 35 on the substrate 10" could mean that the orthographic projection of the first slit 35 on the substrate 10 is located inside the orthographic projection of the third slit 38 on the substrate 10.

[0189] The material of the second dielectric layer 39 can be an insulating material, such as an oxide. For example, the material of the second dielectric layer 39 can be silicon oxide.

[0190] In some embodiments disclosed herein, by simultaneously forming a plurality of contact holes 333, a plurality of first slits 35, and at least one second slit 36 ​​exposing the virtual gate layer 31, the number of photomasks used can be reduced, thereby lowering costs.

[0191] The contact hole 333 can facilitate the formation of a second conductive pillar 50 through the selected gate layer in subsequent steps, so that the second stacked structure 30 does not need to be set with a step structure, which simplifies the formation process of the step structure in the semiconductor structure.

[0192] At this time, the first slit 35 for forming the first grid isolation pattern 60 can be formed simultaneously with the second slit 36 ​​for forming the selective grid isolation pattern 70, without having to be formed simultaneously with the fourth slit 81 for forming the second grid isolation pattern 80. That is, the second grid isolation pattern 80 can be formed before the second stacked structure 30 is made, and the first grid isolation pattern 60 is formed after the second stacked structure 30 is made.

[0193] Thus, when etching the fourth slit 81 where the second gate isolation pattern 80 is located, only the sacrificial layer and the first insulating layer need to be etched. Similarly, when etching the first slit 35 and the third slit 38 where the first gate isolation pattern 60 is located, only the insulating layer and the polysilicon layer need to be etched. The fabrication processes of the first gate isolation pattern 60 and the second gate isolation pattern 80 are relatively simple, and the etching of the gate trenches in the semiconductor structure 100 is less difficult.

[0194] In some embodiments, such as Figure 16 As shown, step S34, forming the second dielectric layer 39, includes:

[0195] S341. Deposit a second dielectric layer 39 on the bottom and sidewalls of the third slit 38 at a first deposition rate;

[0196] S342. After depositing a second dielectric 39 of a predetermined thickness at the bottom of the third slit 38, the second dielectric layer 39 is deposited in the third slit 38 at a second deposition rate to form a first gate line isolation pattern 60 including an air gap 61.

[0197] The second deposition rate is greater than the first deposition rate. The air gap 61 is located between at least two adjacent virtual grid lines 31.

[0198] To form a gap similar to gap 61 in the upper portion of the third slit 38, oxide material can be grown on the sidewalls and bottom of the third slit 38 at a relatively slow deposition rate. During deposition, if a gap forms in the lower portion, a dry etching process can be performed to remove some of the oxide material, allowing for continuous deposition of oxide material until the lower portion of the third slit 38 is filled with oxide material. Thereafter, the deposition rate can be increased to seal the third slit 38 and form a gap similar to gap 61.

[0199] To form a gap similar to gap 61 in the lower portion of the third slit 38, the deposition rate can initially be relatively slow. Once the oxide material thickness at the bottom of the third slit 38 reaches a certain value, the deposition rate can be increased. If the top of the gap is too high after its formation, a dry etching process can be performed to remove some of the oxide material deposited above the gap. The deposition process can then continue at a relatively high rate until the gap is formed again. If the top of the gap is still too high in the Z direction, the etching deposition process can be repeated until a gap similar to gap 61 is formed.

[0200] For example, the preset thickness can be the same as the height difference between the bottom of the third slit 38 near the substrate 10 and the bottom surface of the virtual gate layer 31 near the substrate 10, or the preset thickness can be greater than the height difference between the bottom of the third slit near the substrate 10 and the bottom surface of the virtual gate layer 31 near the substrate 10.

[0201] In some embodiments, such as Figure 2B As shown, along a first direction X parallel to the substrate 10, the semiconductor structure 100 includes an array region 101, a transition region 102, and a step region 103 arranged sequentially.

[0202] Based on this, for example, such as Figure 17 As shown, S1, a first stacked structure 20 is formed on the substrate 10, including:

[0203] S11, such as Figure 18 As shown, a plurality of first insulating layers 21 and a plurality of sacrificial layers 23 are formed alternately stacked on the substrate 10.

[0204] S12, such as Figure 19 As shown, multiple first insulating layers 21 and multiple sacrificial layers 05 are etched to form a stepped structure in the step region 103;

[0205] S13, such as Figure 20 As shown, a plurality of fourth slits 81 are formed, which extend along the first direction X and penetrate a plurality of first insulating layers 21 and a plurality of sacrificial layers 23.

[0206] S14, such as Figure 21 and Figure 22 As shown, multiple fourth slits 81 are used to replace multiple sacrificial layers 23 with gate line layers 22.

[0207] For example, in the first stacked structure 20 formed by the above steps, the dimensions of the multilayer gate line layers 22 that are sequentially moved away from the substrate 10 in the first direction X can be successively reduced.

[0208] In some embodiments of this disclosure, before the second stacked structure 30 is formed, a step structure has already been formed in the portion of the first stacked structure 20 corresponding to the step region 103. Therefore, the simultaneous formation of step structures in the first and second stacked structures is avoided, simplifying the fabrication process of the semiconductor structure 100.

[0209] The material of the first insulating layer 21 may include an oxide, such as silicon oxide. The material of the gate layer 22 may include a metal, such as tungsten, a metal nitride, and / or a metal silicide. Alternatively, the gate layer 22 may also have a multilayer structure including a metal nitride, such as tungsten nitride, and a metal, such as tungsten.

[0210] This disclosure does not limit the number of the first insulating layer 21 and the gate line layer 22 in the first stacked structure 20. For example, the first stacked structure 20 may include 16 gate line layers 22, or 24 gate line layers 22, or 32 gate line layers 22, or 48 gate line layers 22, or more than 48 gate line layers, etc.

[0211] In some embodiments, such as Figure 2B As shown, the thickness of the selected gate layer 33 can be greater than the thickness of the gate layer 22. This configuration results in a larger cross-sectional area for the selected gate layer 33, which helps to reduce the resistance on the selected gate layer 33 and lower power consumption.

[0212] For example, the thickness of the gate layer 33 can be selected from 50nm to 200nm. For instance, the thickness of the gate layer 33 can be 50nm, 100nm, 150nm, 200nm, etc.

[0213] For example, the thickness of the selected gate layer 33 can be 2 to 8 times that of the gate layer 22. This configuration results in a larger thickness of the selected gate layer 33 and a lower resistance on it. Simultaneously, the fabrication cost of the selected gate layer 33 is lower, which helps reduce the fabrication cost of the semiconductor structure 100.

[0214] In some embodiments, such as Figure 2B As shown, along a first direction X parallel to the substrate 10, the semiconductor structure 100 includes an array region 101, a transition region 102, and a step region 103 arranged sequentially.

[0215] like Figure 10 As shown, in the step of forming the second stacked structure 30 on the side of the first stacked structure 20 away from the substrate 10, the virtual gate layer 31 and the selected gate layer 33 cover the array region 101, the transition region 102 and the step region 103.

[0216] like Figure 23 As shown, before step S3 and the formation of the first conductive pillar 40 and the second conductive pillar 50, the preparation method further includes:

[0217] S35, such as Figure 24 As shown, the portion of the selected grid layer 33 covering the step area 103 is removed.

[0218] S36, such as Figure 25 As shown, the portion of the virtual grid layer 31 covering the step area 103 is removed.

[0219] For example, step S35, removing the portion of the selected gate layer 33 covering the step region 103, can be performed simultaneously with step S31, etching the third insulating layer 34, selecting the gate layer 33 and the second insulating layer 32 to form multiple contact holes 333, multiple first slits 35, and at least one second slit 36 ​​exposing the virtual gate layer 31. In this way, contact holes 333, first slits 35, and second slits 36 can be obtained in the selected gate layer 33 using only one mask, while simultaneously removing the portion of the selected gate layer 33 covering the step region 103, saving on the number of masks used and reducing process costs.

[0220] For example, step S36, removing the portion of the virtual grid layer 31 that covers the step area 103, can be performed simultaneously with step S33, forming the third slit 38 that penetrates the virtual grid layer 31. In this way, the third slit 38 can be obtained in the virtual grid layer 31 using the same mask, and the portion of the virtual grid layer 31 that covers the step area 103 can be removed, thereby saving the number of masks used and reducing the process cost.

[0221] This configuration also prevents the virtual gate layer 31 and the selection gate layer 33 located in the step region 103 from making electrical contact with the third conductive post 90, thereby improving the signal stability of the virtual gate line 311, the selection gate line 331 (or the sub-gate line 332) and the gate line 221, and improving the stability of the semiconductor structure 100 in use.

[0222] In some embodiments, such as Figure 26 As shown, before step S2, where the second stacked structure 30 is formed on the side of the first stacked structure 20 away from the substrate 10, the fabrication method further includes:

[0223] S20, such as Figure 27 As shown, multiple first channel structures 91 are formed. The first channel structure 91 penetrates the first stacked structure 20, which includes a barrier layer 911, a charge storage layer 912, a tunneling layer 913, and a first channel layer 914.

[0224] The barrier layer 911 may include a single layer, for example, a SiO2 layer. The barrier layer 911 may also include multiple layers, for example, a SiO2 and Al2O3 stack. The charge storage layer 912 may include a single layer, for example, a SiN layer. The charge storage layer 912 may also include multiple layers, for example, a SiN, SiON, and SiN stack. The tunneling layer 913 may include multiple layers, for example, a SiO, SiON, and SiO stack.

[0225] For example, the material of the first channel layer 914 includes polycrystalline silicon and / or monocrystalline silicon.

[0226] In some embodiments, such as Figure 26 As shown, before step S3 and the formation of the first and second conductive pillars, the preparation method further includes:

[0227] S30, such as Figure 28 As shown, multiple second channel structures 92 are formed. The second channel structures 92 penetrate the second stacked structure 30, which includes a gate dielectric layer 921 and a second channel layer 922.

[0228] In this configuration, a second channel structure 92 is provided on the side of each first channel structure 91 that is away from the substrate 10, and the first channel layer 914 of the first channel structure 91 is electrically connected to the second channel layer 922 of the corresponding second channel structure 92.

[0229] The gate dielectric layer 921 may be made of silicon oxide, but this disclosure is not limited thereto. The second channel layer 922 may be made of a semiconductor material. Exemplarily, the second channel layer 922 may be made of polycrystalline silicon and / or monocrystalline silicon.

[0230] Please see Figure 29 Some embodiments of this disclosure also provide a three-dimensional memory 200. The three-dimensional memory includes the semiconductor structure 100 and peripheral circuitry 300 described in any of the above embodiments. The semiconductor structure 100 is electrically connected to the peripheral circuitry 300 to enable the peripheral circuitry 300 to support the functions of the semiconductor structure 100, such as reading, writing, and erasing data in the memory cells.

[0231] See Figure 29In some embodiments, the 3D memory 200 further includes an array interconnect layer 400 on the side of the semiconductor structure 100 adjacent to the peripheral circuit 300, and the semiconductor structure 100 is electrically connected to the array interconnect layer 400. The peripheral circuit 300 includes a series of circuits 310 such as a page buffer, and a peripheral interconnect layer 320 disposed on the side of the series of circuits 310 adjacent to the array interconnect layer 400, and the series of circuits 310 is electrically connected to the peripheral interconnect layer 320. The semiconductor structure 100 and the peripheral circuit 300 are electrically connected through the array interconnect layer 400 and the peripheral interconnect layer 320, thereby achieving electrical connection between the semiconductor structure 100 and the series of circuits 310.

[0232] The beneficial effects of the three-dimensional memory 200 provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure 100 described above, and will not be repeated here.

[0233] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first stacked structure disposed on the substrate, the first stacked structure comprising a plurality of alternating first insulating layers and a plurality of gate line layers; A second stacked structure is disposed on the side of the first stacked structure away from the substrate. The second stacked structure includes at least a virtual gate layer, a second insulating layer, a select gate layer, and a third insulating layer disposed sequentially. Along a first direction parallel to the substrate, the semiconductor structure includes an array region, a transition region, and a step region arranged sequentially. The edges of the virtual gate layer and the select gate layer extend to the transition region. A first conductive post and a second conductive post are disposed in the transition region. The first conductive post passes through the third insulating layer and is electrically connected to the select gate layer. The second conductive post passes through the third insulating layer, the select gate layer, and the second insulating layer and is electrically connected to the virtual gate layer. Multiple first gate line isolation patterns extending along the first direction, the first gate line isolation patterns penetrating the second stacked structure, to divide the virtual gate line layer into multiple virtual gate lines and the selected gate line layer into multiple selected gate lines; Multiple second gate line isolation patterns extending along the first direction, the second gate line isolation patterns penetrating the first stacked structure, to divide the gate line layer into multiple gate lines; In this configuration, a first gate isolation pattern and a second gate isolation pattern are arranged in a third direction, which is perpendicular to the substrate.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: At least one select gate isolation pattern extending along the first direction, at least one select gate isolation pattern is disposed between two adjacent first gate line isolation patterns, the select gate isolation pattern penetrates the select gate line layer to divide the select gate line into multiple sub-gate lines, and the select gate isolation pattern is located on the side of the virtual gate line away from the substrate.

3. The semiconductor structure according to claim 2, characterized in that, The first gate isolation pattern includes a first portion located between two adjacent selected gate lines and a second portion located between two adjacent virtual gate lines; along the second direction, the size of the second portion is smaller than the size of the first portion; The second direction is parallel to the substrate and perpendicular to the first direction.

4. The semiconductor structure according to claim 2, characterized in that, Between two adjacent first gate line isolation patterns, each sub-gate line is electrically connected to at least one first conductive post.

5. The semiconductor structure according to claim 4, characterized in that, Between two adjacent first gate line isolation patterns, a plurality of first conductive pillars are arranged along a second direction; the second direction is parallel to the substrate and perpendicular to the first direction.

6. The semiconductor structure according to claim 2, characterized in that, Between two adjacent first gate isolation patterns, at least one sub-gate line corresponds to at least one second conductive pillar, and the at least one second conductive pillar passes through the corresponding sub-gate line and is electrically connected to a virtual gate line located on the side of the corresponding sub-gate line closer to the substrate.

7. The semiconductor structure according to claim 6, characterized in that, Between two adjacent first gate line isolation patterns, each sub-gate line corresponds to at least one second conductive pillar, and the at least one second conductive pillar passes through the corresponding sub-gate line and is electrically connected to the virtual gate line on the side of the sub-gate line closer to the substrate.

8. The semiconductor structure according to claim 2, characterized in that, The first grid line isolation pattern includes an air gap, which is located at least between two adjacent virtual grid lines.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The selected gate layer has a contact hole located in the transition region, and the second conductive post passes through the contact hole and is electrically connected to the virtual gate layer; an isolation layer is provided on the inner wall of the contact hole, and the isolation layer surrounds the portion of the second conductive post located inside the contact hole.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The second conductive post is located on the side of the first conductive post away from the array region.

11. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The materials of both the selected gate layer and the virtual gate layer include polycrystalline silicon or germanium silicon.

12. The semiconductor structure according to claim 11, characterized in that, The thickness of the selected gate layer is greater than the thickness of the gate layer.

13. The semiconductor structure according to claim 12, characterized in that, The thickness of the selected gate layer is 2 to 8 times the thickness of the gate layer.

14. The semiconductor structure according to any one of claims 1 to 8, characterized in that, Also includes: The orthographic projection of the second gate isolation pattern on the substrate overlaps with the orthographic projection of the first gate isolation pattern on the substrate, and the first gate isolation pattern and the second gate isolation pattern are connected.

15. The semiconductor structure according to claim 14, characterized in that, Also includes: A third conductive post is disposed in the stepped area; the third conductive post passes through the first insulating layer and is electrically connected to the grid line.

16. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The alternating plurality of first insulating layers and plurality of gate line layers extend from the array region through the transition region to the step region, and form a step structure in the step region.

17. The semiconductor structure according to any one of claims 1 to 8, characterized in that, Both the virtual grid layer and the selected grid layer extend from the array region to the boundary line between the transition region and the step region.

18. The semiconductor structure according to any one of claims 1 to 8, characterized in that, Also includes: Multiple first channel structures are disposed in the array region and penetrate the first stacked structure; The first channel structure includes a barrier layer, a charge storage layer, a tunneling layer, and a first channel layer; Multiple second channel structures are disposed in the array region and penetrate the second stacked structure; the second channel structure includes a gate dielectric layer and a second channel layer; In this configuration, a second channel structure is provided on the side of each first channel structure away from the substrate, and the first channel layer of the first channel structure is electrically connected to the second channel layer of the corresponding second channel structure.

19. The semiconductor structure according to claim 18, characterized in that, The radial dimension of the second channel structure is smaller than the radial dimension of the corresponding first channel structure.

20. A method for fabricating a semiconductor structure, characterized in that, include: A first layered structure is formed on the substrate; Forming a second grid line isolation pattern; The second gate line isolation pattern extends along the first direction and penetrates the first stacked structure; A second stacked structure is formed on the side of the first stacked structure away from the substrate; the second stacked structure includes at least a virtual gate line layer, a second insulating layer, a select gate line layer and a third insulating layer arranged sequentially. A first gate isolation pattern is formed; the first gate isolation pattern extends along the first direction and penetrates the second stacked structure to divide the virtual gate layer into multiple virtual gate lines and the selected gate layer into multiple selected gate lines; a first gate isolation pattern and a second gate isolation pattern are arranged in a third direction, which is perpendicular to the substrate; A first conductive post and a second conductive post are formed; the first conductive post passes through a third insulating layer and is electrically connected to the select gate layer; the second conductive post passes through the third insulating layer, the select gate layer and the second insulating layer, and is electrically connected to the virtual gate layer.

21. The preparation method according to claim 20, characterized in that, Before forming the first and second conductive pillars, the preparation method further includes: The third insulating layer, the select gate line layer, and the second insulating layer are etched to form a plurality of contact holes, a plurality of first slits, and at least one second slit that expose the virtual gate line layer; the plurality of first slits divide the select gate line layer into a plurality of select gate lines; at least one second slit is formed between two adjacent first slits, and the second slit divides the select gate line into a plurality of sub-gate lines; A first dielectric layer is formed; the first dielectric layer fills the plurality of contact holes, the plurality of first slits and the at least one second slit, the first dielectric layer filled in the at least one second slit forms a selective gate isolation pattern, and the first dielectric layer filled in the plurality of contact holes forms an isolation layer; A third slit is formed that penetrates the virtual gate layer; the orthographic projection of the third slit on the substrate overlaps with the orthographic projection of the first slit on the substrate, and the third slit divides the virtual gate layer into multiple virtual gate lines; A second dielectric layer is formed; the second dielectric layer fills the third slit, and the first dielectric layer filled in the first slit and the second dielectric layer filled in the third slit form a first gate line isolation pattern.

22. The preparation method according to claim 21, characterized in that, The formation of the second dielectric layer includes: A second dielectric layer is deposited on the bottom and sidewalls of the third slit at a first deposition rate; After depositing a second dielectric layer of a predetermined thickness at the bottom of the third slit, the second dielectric layer is deposited in the third slit at a second deposition rate to form a first gate line isolation pattern including an air gap. Wherein, the second deposition rate is greater than the first deposition rate; the air gap is located between at least two adjacent virtual grid lines.

23. The preparation method according to claim 20, characterized in that, Along a first direction parallel to the substrate, the semiconductor structure includes an array region, a transition region, and a step region arranged sequentially. The formation of the first stacked structure on the substrate includes: Multiple first insulating layers and multiple sacrificial layers are formed alternately stacked on the substrate; The plurality of first insulating layers and the plurality of sacrificial layers are etched to form a stepped structure in the stepped region; A plurality of fourth slits are formed, the fourth slits extending along the first direction and penetrating the plurality of first insulating layers and the plurality of sacrificial layers; The plurality of fourth slits are used to replace the plurality of sacrificial layers with the plurality of gate line layers.

24. The preparation method according to claim 23, characterized in that, The thickness of the selected gate layer is greater than the thickness of the gate layer.

25. The preparation method according to claim 24, characterized in that, The thickness of the selected gate layer is 2 to 8 times the thickness of the gate layer.

26. The preparation method according to claim 20, characterized in that, Along a first direction parallel to the substrate, the semiconductor structure includes an array region, a transition region, and a step region arranged sequentially. In the step of forming a second stacked structure on the side of the first stacked structure away from the substrate, the virtual gate layer and the selected gate layer cover the array region, the transition region and the step region; Before forming the first and second conductive pillars, the preparation method further includes: Remove the portion of the selected gate layer that covers the stepped area; Remove the portion of the virtual grid layer that covers the step area.

27. The preparation method according to claim 20, characterized in that, Before forming the second stacked structure on the side of the first stacked structure away from the substrate, the fabrication method further includes: Multiple first channel structures are formed; the first channel structure penetrates the first stacked structure, and the first channel structure includes a barrier layer, a charge storage layer, a tunneling layer and a first channel layer; Before forming the first and second conductive pillars, the preparation method further includes: Multiple second channel structures are formed; the second channel structures penetrate the second stacked structure, and the second stacked structure includes a gate dielectric layer and a second channel layer; In this configuration, a second channel structure is provided on the side of each first channel structure away from the substrate, and the first channel layer of the first channel structure is electrically connected to the second channel layer of the corresponding second channel structure.

28. The preparation method according to any one of claims 20 to 27, characterized in that, The materials of both the selected gate layer and the virtual gate layer include polycrystalline silicon or germanium silicon.

29. A three-dimensional memory, characterized in that, include: The semiconductor structure as described in any one of claims 1 to 19; The peripheral circuit is electrically connected to the semiconductor structure.

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