Detection method, circuit, power supply and electronic equipment

Abstract

The present disclosure relates to a detection method, circuit, power supply, and electronic device. The circuit is used to detect the connection status between an output node of a power driver circuit and an inductor. The circuit includes a first detection module, a second detection module, and a status determination module, wherein: the first detection module and the second detection module are respectively used to detect whether the output node is connected to the inductor, ground, or power supply voltage, or whether the output node is floating, and output a first signal and a second signal based on the detection results; the status determination module is used to determine the connection status between the output node and the inductor based on the first signal and the second signal. Embodiments of the present disclosure can quickly and accurately determine the connection status of the output node of the power driver circuit, and can quickly and accurately determine the connection status of the output node of the power driver circuit and the inductor, thereby achieving efficient control of the power supply, improving power supply efficiency, and reducing power consumption.

Description

Technical Field

[0001] The present disclosure relates to the field of power supply technology, and in particular to a detection method, circuit, power supply and electronic equipment. Background Art

[0002] Currently, certain systems require higher output current (such as those powered by a DC-DC output). This results in higher inductor current under heavy loads. Limited by the inductor's saturation current, the DC-DC needs to be multi-channeled. This reduces the inductor current in each channel while maintaining drive capability. Therefore, it's crucial to determine whether the DC-DC controller is connected to the inductor. Summary of the Invention

[0003] According to one aspect of the present disclosure, a detection circuit is provided for detecting a connection state between an output node of a power drive circuit and an inductor. The circuit includes a first detection module, a second detection module, and a state determination module, wherein:

[0004] The first detection module and the second detection module are both connected to the output node, and are respectively used to detect whether the output node is connected to the inductor, the ground, or the power supply voltage, or whether the output node is floating, and output a first signal and a second signal respectively according to the detection results;

[0005] The state determination module is connected to the first detection module and the second detection module, and is configured to determine a connection state between the output node and the inductor according to the first signal and the second signal.

[0006] In a possible implementation, the first detection module is configured to detect whether the output node is connected to the ground, connected to the power supply voltage, floating, or connected to an inductor.

[0007] In a possible implementation, the second detection module is used to detect whether the output node is connected to the ground, connected to the power supply voltage, or floating, or connected to an inductor.

[0008] The first detection module and the second detection module respectively detect different detection items among the output node being connected to the ground, being connected to the power supply voltage, and the output node being floating.

[0009] In a possible implementation, the first detection module is used to detect that the output node is connected to the ground, and the second detection module is used to detect that the output node is connected to the power supply voltage and that the output node is floating.

[0010] In a possible implementation, the state determination module includes an AND logic circuit, and determining the connection state between the output node and the inductor according to the first signal and the second signal includes:

[0011] Performing AND logic processing on the first signal and the second signal, and when an output result of the AND logic circuit is a high level, determining that the output node is connected to the inductor; otherwise, determining that the output node is not connected to the inductor.

[0012] In a possible implementation, the first detection module includes a first non-logic circuit, an odd number of second non-logic circuits, a first timing circuit, a first OR logic circuit, a first PMOS transistor, a first resistor, a second resistor, a first capacitor, a first Schmitt trigger circuit, and a first latch circuit.

[0013] The input end of the first NOT logic circuit receives an enable signal, and the output end of the first NOT logic circuit is connected to the reset end of the first timing circuit, the reset end of the first latch circuit, and the first input end of the first OR logic circuit.

[0014] The clock signal terminal of the first timing circuit is used to receive a clock signal, and the output terminal of the first timing circuit is connected to the second input terminal of the first OR logic circuit and the latch control terminal of the first latch circuit.

[0015] The output terminal of the first OR logic circuit is connected to the control terminal of the first PMOS transistor,

[0016] The source of the first PMOS transistor is used to receive a power supply voltage, and the drain of the first PMOS transistor is connected to the first end of the first resistor.

[0017] The second end of the first resistor is connected to the output node and the first end of the second resistor,

[0018] The second end of the second resistor is connected to the first end of the first capacitor and the input end of the first Schmitt trigger circuit, and the second end of the first capacitor is grounded.

[0019] The output terminal of the first Schmitt trigger circuit is connected to the data input terminal of the first latch circuit,

[0020] The latch output terminal of the first latch circuit is connected to the input terminal of the second non-logic circuit,

[0021] The second NOT logic circuit is configured to output the first signal.

[0022] In a possible implementation, the second detection module includes a third non-logical circuit, a fourth non-logical circuit, an even number of fifth non-logical circuits, a second timing circuit, a second OR logic circuit, a second PMOS transistor, a first NMOS transistor, a third resistor, a fourth resistor, a second Schmitt trigger circuit, a first delay circuit, a first AND logic circuit, and a second latch circuit.

[0023] The input end of the third NOT logic circuit receives an enable signal, and the output end of the third NOT logic circuit is connected to the reset end of the second timing circuit, the reset end of the second latch circuit, and the first input end of the second OR logic circuit.

[0024] The clock signal terminal of the second timing circuit is used to receive a clock signal. The output terminal of the second timing circuit is connected to the second input terminal of the second OR logic circuit and the input terminal of the fourth NOT logic circuit. The output terminal of the fourth NOT logic circuit is connected to the enable terminal of the second Schmitt trigger circuit and the first input terminal of the first AND logic circuit.

[0025] The third input terminal of the second OR logic circuit is connected to the output terminal of the second latch circuit and the input terminal of the fifth NOT logic circuit, and the output terminal of the second OR logic circuit is connected to the control terminal of the second PMOS transistor and the control terminal of the first NMOS transistor.

[0026] The source of the second PMOS transistor is connected to the data input terminal of the second latch circuit for receiving a power supply voltage, and the drain of the second PMOS transistor is connected to the first terminal of the third resistor.

[0027] The second end of the third resistor is connected to the output node and the first end of the fourth resistor.

[0028] The second end of the fourth resistor is connected to the drain of the first NMOS transistor and the input end of the second Schmitt trigger circuit, and the source of the first NMOS transistor is grounded.

[0029] The output end of the second Schmitt trigger circuit is connected to the input end of the first delay circuit,

[0030] The output end of the first delay circuit is connected to the second input end of the first AND logic circuit.

[0031] The output terminal of the first AND logic circuit is connected to the latch control terminal of the second latch circuit.

[0032] The output terminal of the fifth NOT logic circuit is used to output the second signal.

[0033] In a possible implementation, the power drive circuit includes a DC-DC power drive circuit and / or an AC-DC power drive circuit.

[0034] According to one aspect of the present disclosure, a power supply is provided, comprising the detection circuit.

[0035] According to one aspect of the present disclosure, an electronic device is provided, including the power supply described in the electronic device.

[0036] According to one aspect of the present disclosure, a detection method is provided. The method is applied to a detection circuit for detecting a connection state between an output node of a power drive circuit and an inductor. The circuit includes a first detection module, a second detection module, and a state determination module. The method includes:

[0037] Using the first detection module and the second detection module to respectively detect whether the output node is connected to the inductor, the ground, or the power supply voltage or whether the output node is floating, and outputting a first signal and a second signal respectively according to the detection results;

[0038] The state determination module is utilized to determine a connection state between the output node and the inductor according to the first signal and the second signal.

[0039] In one possible implementation, the method further includes:

[0040] The first detection module is used to detect whether the output node is connected to the ground, connected to the power supply voltage, floating, or connected to the inductor.

[0041] The second detection module is used to detect whether the output node is connected to the ground, connected to the power supply voltage, floating, or connected to the inductor.

[0042] The first detection module and the second detection module respectively detect different detection items among the output node being connected to the ground, being connected to the power supply voltage, and the output node being floating.

[0043] In a possible implementation, the state determination module includes an AND logic circuit, and determining the connection state between the output node and the inductor according to the first signal and the second signal includes:

[0044] Performing AND logic processing on the first signal and the second signal, and when an output result of the AND logic circuit is a high level, determining that the output node is connected to the inductor; otherwise, determining that the output node is not connected to the inductor.

[0045] The detection circuit proposed in the embodiment of the present disclosure includes a first detection module, a second detection module and a state determination module, wherein: the first detection module and the second detection module are both connected to the output node, and are respectively used to detect whether the output node is connected to the inductor, the ground, the power supply voltage or the output node is floating, and output a first signal and a second signal according to the detection results; the state determination module is connected to the first detection module and the second detection module, and is used to determine the connection state of the output node and the inductor according to the first signal and the second signal. Through the detection circuit, the embodiment of the present disclosure can realize the rapid and accurate determination of the connection state of the output node of the power driving circuit, and in particular, can realize the rapid and accurate determination of the connection state of the output node of the power driving circuit and the inductor, so as to realize efficient control of the power supply, improve the power supply efficiency, and reduce power consumption.

[0046] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0048] Figure 1 A block diagram of a detection circuit according to an embodiment of the present disclosure is shown.

[0049] Figure 2a FIG. 1 is a schematic diagram showing the connection between the output node SW of each power drive circuit in the power supply system and the inductor. Figure 2b The diagram shows a schematic diagram of the output nodes SW of each power driving circuit in the power supply system being connected to the inductor, the ground, the power supply voltage and being floating.

[0050] Figure 3a A schematic diagram of a first detection module according to an embodiment of the present disclosure is shown.

[0051] Figure 3b 、 Figure 3c 、 Figure 3d 、 Figure 3e Schematic diagrams showing the first detection module detecting connection with an inductor, grounding, floating, and connection with a power supply voltage according to an embodiment of the present disclosure are respectively shown.

[0052] Figure 4a A schematic diagram of a first detection module according to an embodiment of the present disclosure is shown.

[0053] Figure 4b 、 Figure 4d 、 Figure 4e 、 Figure 4f Schematic diagrams showing the second detection module detecting connection with an inductor, grounding, floating, and connection with a power supply voltage according to an embodiment of the present disclosure are shown respectively. Figure 4c A schematic diagram showing the waveform amplification when connected to an inductor is shown.

[0054] Figure 5 A flow chart of a detection method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0055] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0056] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0058] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0059] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0060] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0061] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0062] The related technical solutions cannot accurately and quickly determine the connection status of the output stage of the power drive circuit. In particular, they cannot quickly and accurately determine the connection status between the output stage of the power drive circuit and the inductor. This makes the power supply efficiency of the related technical power supply solution low and the power consumption high.

[0063] The detection circuit proposed in the embodiment of the present disclosure includes a first detection module, a second detection module and a state determination module, wherein: the first detection module and the second detection module are both connected to the output node, and are respectively used to detect whether the output node is connected to the inductor, the ground, the power supply voltage or the output node is floating, and output a first signal and a second signal according to the detection results; the state determination module is connected to the first detection module and the second detection module, and is used to determine the connection state of the output node and the inductor according to the first signal and the second signal. Through the detection circuit, the embodiment of the present disclosure can realize the rapid and accurate determination of the connection state of the output node of the power driving circuit, and in particular, can realize the rapid and accurate determination of the connection state of the output node of the power driving circuit and the inductor, so as to realize efficient control of the power supply, improve the power supply efficiency, and reduce power consumption.

[0064] In the embodiment of the present disclosure, when all phases need to work, the correct connection of the inductor can be ensured. When the system does not need all DCDC phases to work, but only some phases need to work, whether to open the driving circuit of the corresponding path can also be determined based on whether the inductor is connected to the power tube, thereby achieving the purpose of reducing power consumption.

[0065] See also Figure 1 , Figure 1 A block diagram of a detection circuit according to an embodiment of the present disclosure is shown.

[0066] like Figure 1 As shown, the circuit is used to detect the connection status between the output node SW of the power drive circuit and the inductor. The circuit includes a first detection module 10, a second detection module 20 and a status determination module 30, wherein:

[0067] The first detection module 10 and the second detection module 20 are both connected to the output node SW, and are respectively used to detect whether the output node SW is connected to the inductor, the ground, or the power supply voltage, or whether the output node SW is floating, and output a first signal and a second signal respectively according to the detection results;

[0068] The state determination module 30 is connected to the first detection module 10 and the second detection module 20 , and is configured to determine the connection state between the output node SW and the inductor according to the first signal and the second signal.

[0069] The connection state of the embodiment of the present disclosure may include connected and unconnected, such as the output node SW is connected to the inductor, or the output node SW is not connected to the inductor.

[0070] In the embodiment of the present disclosure, the output node SW is connected to the power supply voltage, which may mean that the voltage connected to the output node SW is higher than the first preset voltage. The first preset voltage can be determined according to actual conditions, and the embodiment of the present disclosure does not limit this.

[0071] In the embodiment of the present disclosure, the output node SW is connected to the ground, which may mean that the voltage connected to the output node SW is lower than the second preset voltage. The second preset voltage can be determined according to actual conditions, and the embodiment of the present disclosure does not limit this.

[0072] The floating in the embodiment of the present disclosure may mean that the output node SW is not connected to a high level or a low level.

[0073] See also Figure 2a 、 Figure 2b , Figure 2a FIG. 1 is a schematic diagram showing the connection between the output node SW of each power drive circuit in the power supply system and the inductor. Figure 2b The diagram shows a schematic diagram of the output nodes SW of each power driving circuit in the power supply system being connected to the inductor, the ground, the power supply voltage and being floating.

[0074] The embodiments of the present disclosure do not limit the specific implementation methods of the power supply and the power drive circuit. The embodiments of the present disclosure are described using the power drive circuit as BUCK-BOOST. Each power drive circuit includes two upper and lower transistors connected as the output power stage, and the output node SW is the power output voltage of the two transistors. Of course, the power drive circuit can be in other forms, and the embodiments of the present disclosure do not limit this.

[0075] In this embodiment, Figure 2b As shown in the figure, when the inductor (L1~LN) is not connected to the power tube in the application, the output node of the power tube can be selected to be floating, grounded, or shorted to a high potential. Figure 2b As shown, the output node SW1 of path 1 is normally connected to the inductor, the output node SW2 of path 2 is in a floating connection mode, the output node SW3 of path 3 is directly shorted to GND, and the output node SW4 of path 4 is directly shorted to a high potential.

[0076] The embodiments of the present disclosure do not limit the specific implementation methods of the first detection module 10 and the second detection module 20, and do not limit the specific implementation methods of the state determination module 30. Those skilled in the art can determine according to actual conditions and needs. As long as the first detection module 10 and the second detection module 20 can respectively detect whether the output node SW is connected to the inductor, the ground, and the power supply voltage, or the output node SW is floating, and output the first signal and the second signal respectively according to the detection results, the state determination module 30 can determine the connection status of the output node SW and the inductor according to the first signal and the second signal. The following is an illustrative introduction to possible implementation methods of the first detection module 10, the second detection module 20 and the state determination module 30.

[0077] The embodiments of the present disclosure do not limit the specific forms of the first signal and the second signal. Those skilled in the art can set them as needed. For example, the first signal and the second signal can each include at least one signal bit. When the detection items are different, the results corresponding to the signal bit can be different. Of course, the first signal and the second signal can each include one bit, and each detection item can share the same signal bit; the first signal and the second signal can also include multiple bits, for example, 4 bits, each bit corresponding to the state of detecting the output node SW being connected to the inductor, ground, or power supply voltage or the output node SW being floating. For example, each bit can be a high level (logic 1) or a low level (logic 0). The high level can correspond to any one of the output node SW being connected to the inductor, ground, or power supply voltage or the output node SW being floating. The low level can correspond to any one of the output node SW not being connected to the inductor, ground, or power supply voltage or the output node SW not being floating. In this way, the embodiment of the present disclosure can determine the connection state of the output node SW and the inductor through the first signal and the second signal obtained by the first detection module 10 and the second detection module 20. The following will be introduced as an example with the first signal and the second signal including one bit.

[0078] In a possible implementation, the first detection module 10 may be configured to detect whether the output node SW is connected to the ground, connected to the power supply voltage, floating, or connected to an inductor.

[0079] In a possible implementation, the second detection module 20 may be used to detect whether the output node SW is connected to the ground, connected to the power supply voltage, or floating, or connected to an inductor.

[0080] The first detection module 10 and the second detection module 20 respectively detect different detection items of the output node SW being connected to the ground, connected to the power supply voltage, and the output node SW being floating.

[0081] In the embodiment of the present disclosure, the first detection module 10 is used to detect that the output node SW is connected to the ground, connected to the power supply voltage, the output node SW is floating, and connected to the inductor, and the second detection module 20 is used to detect that the output node SW is connected to the ground, connected to the power supply voltage, the output node SW is floating, and connected to the inductor. The first detection module 10 and the second detection module 20 are set to respectively detect different detection items among the three: the output node SW is connected to the ground, connected to the power supply voltage, and the output node SW is floating, and the corresponding detection signals (first signal and second signal) can be obtained, thereby quickly determining the connection status of the output node SW and the inductor.

[0082] The embodiment of the present disclosure does not limit the specific detection items that the first detection module 10 and the second detection module 20 respectively detect, among which the output node SW is connected to the ground, connected to the power supply voltage, and the output node SW is floating.

[0083] In one possible implementation, the first detection module 10 is configured to detect that the output node SW is connected to ground, and the second detection module 20 is configured to detect that the output node SW is connected to a power supply voltage or is floating. For example, when the first detection module 10 detects that the output node SW is connected to ground, the first detection module 10 may output a first signal corresponding to a high level; otherwise, the signal may be low. When the second detection module detects that the output node SW is connected to a power supply voltage or is floating, the second detection module 20 may output a second signal corresponding to a high level.

[0084] In a possible implementation, the state determination module 30 includes an AND logic circuit, and determining the connection state between the output node SW and the inductor according to the first signal and the second signal may include:

[0085] AND logic processing is performed on the first signal and the second signal. When the output result of the AND logic circuit is a high level, it is determined that the output node SW is connected to the inductor; otherwise, it is determined that the output node SW is not connected to the inductor.

[0086] The following is an introduction with specific examples.

[0087] Table 1 shows a signal diagram of a detection circuit according to an embodiment of the present disclosure.

[0088] Table 1

[0089]

[0090] As shown in Table 1, in one example, the first detection module 10 detects whether the output node SW is connected to the ground, connected to the power supply voltage, or floating, and connected to the inductor, and the second detection module 20 is used to detect whether the output node SW is connected to the ground, connected to the power supply voltage, or floating, and connected to the inductor. The first detection module 10 and the second detection module 20 are set to respectively detect different detection items among the three: the output node SW is connected to the ground, connected to the power supply voltage, and the output node SW is floating. As an example, the first detection module 10 can be set to detect that the output node SW is connected to the ground, and the second detection module 20 can be used to detect that the output node SW is connected to the power supply voltage and the output node SW is floating.

[0091] In this embodiment, when the output node SW is connected to the inductor, the corresponding signal bits in the first signal and the second signal outputted by the first detection module 10 and the second detection module 20 are both high level (1); when the output node SW is grounded, the corresponding signal bits in the first signal and the second signal outputted by the first detection module 10 and the second detection module 20 are high level (1) and low level (0) respectively; when the output node SW is connected to the power supply voltage, the corresponding signal bits in the first signal and the second signal outputted by the first detection module 10 and the second detection module 20 are low level (0) and high level (1) respectively; when the output node SW is in a floating state, the corresponding signal bits in the first signal and the second signal outputted by the first detection module 10 and the second detection module 20 are low level (0) and high level (1) respectively. It should be noted that the aforementioned "corresponding signal bits" can be determined according to the actual settings of the first signal and the second signal. If it includes only one bit, the corresponding signal bits corresponding to each detection item are all the same signal bit; if each detection item is set to correspond to a different signal bit, the "corresponding signal bits" are a one-to-one correspondence relationship with each detection item.

[0092] In this embodiment, as shown in Table 1, the state determination module performs an AND logic operation on the first signal and the second signal only when the output node SW is connected to the inductor, and all other conditions are low (0). Therefore, the embodiment of the present disclosure performs an AND logic operation on the first signal and the second signal. When the output result of the AND logic circuit is a high level, it can be quickly and accurately determined that the output node SW is connected to the inductor. Otherwise, it is determined that the output node SW is not connected to the inductor.

[0093] The following is an exemplary introduction to possible implementations of the first detection module 10 and the second detection module 20 in this embodiment.

[0094] See also Figure 3a , Figure 3a A schematic diagram of a first detection module according to an embodiment of the present disclosure is shown.

[0095] In one possible implementation, Figure 3a As shown, the first detection module 10 may include a first NOT logic circuit NOT1, an odd number of second NOT logic circuits NOT2, a first timing circuit Timer1, a first OR logic circuit OR1, a first PMOS transistor MP1, a first resistor R1, a second resistor R2, a first capacitor C1, a first Schmitt trigger circuit SMIT1 and a first latch circuit LATCH1.

[0096] The input end of the first NOT logic circuit NOT1 receives an enable signal en, and the output end of the first NOT logic circuit NOT1 is connected to the reset end reset of the first timing circuit Timer1, the reset end reset of the first latch circuit LATCH1, and the first input end of the first OR logic circuit OR1.

[0097] The clock signal terminal of the first timing circuit Timer1 is used to receive the clock signal clk, and the output terminal of the first timing circuit Timer1 is connected to the second input terminal of the first OR logic circuit OR1 and the latch control terminal latch of the first latch circuit LATCH1.

[0098] The output terminal of the first OR logic circuit OR1 is connected to the control terminal of the first PMOS transistor MP1.

[0099] The source of the first PMOS transistor MP1 is used to receive the power supply voltage VDD, and the drain of the first PMOS transistor MP1 is connected to the first end of the first resistor R1.

[0100] The second end of the first resistor R1 is connected to the output node SW and the first end of the second resistor R2.

[0101] The second end of the second resistor R2 is connected to the first end of the first capacitor C1 and the input end of the first Schmitt trigger circuit SMIT1. The second end of the first capacitor C1 is grounded.

[0102] The output terminal of the first Schmitt trigger circuit SMIT1 is connected to the data input terminal data of the first latch circuit LATCH1.

[0103] The latch output terminal of the first latch circuit LATCH1 is connected to the input terminal of the second NOT logic circuit NOT2.

[0104] The second NOT logic circuit NOT2 is configured to output the first signal.

[0105] The working process of the first detection module is exemplarily introduced below.

[0106] See also Figure 3b 、 Figure 3c 、 Figure 3d 、 Figure 3e , Figure 3b 、 Figure 3c 、 Figure 3d 、 Figure 3e Schematic diagrams showing the first detection module detecting connection with an inductor, grounding, floating, and connection with a power supply voltage according to an embodiment of the present disclosure are respectively shown.

[0107] Exemplarily, the enable signal en can be set to 0 initially, and the time_out signal output by the first timing circuit can be reset to 0, wherein the first PMOS transistor MP1 is a pull-up transistor. If the control terminal (gate) receives a high level (logic 1), the pull-up P transistor is turned off; when en changes from 0 to 1, the pull-up P transistor is turned on.

[0108] In one example, if Figure 3b 、 Figure 3cAs shown, if the output node SW is connected to an inductor or ground at this time, the potential of the output node SW is 0. Controlled by resistor R1, the current in the inductor will not be large. Since the current does not change suddenly, the inductor can be considered a short circuit, so the inductor current will drop to 0 in a very short time, generating a short voltage glitch at the SW terminal (RC filtering, i.e., R2 & C1, will filter out this glitch). The current then flows through the first PMOS transistor MP1, the first resistor R1, and the inductor to GND or VOUT (VOUT is connected to a large capacitor, and VOUT cannot charge from GND to a logic high before the count ends). Since the output node SW cannot go high, the first capacitor C1 cannot be charged, which means that the smit_in signal at the connection point between the first capacitor C1 and the second resistor R2 cannot pass through the pull-up transistor MP1 and resistors R1 and R2. After passing through the RC delay unit, it is set to a logic high, and the output of the first Schmitt trigger circuit (SMIT trigger) is 0. When the first timer circuit expires, the time_out signal output by the first timer circuit becomes 1, the mpg signal output by the first OR logic circuit OR1 becomes 1, and the first PMOS transistor MP1 is turned off. Simultaneously, the output signal of the SMIT trigger is latched to 0 by the first latch circuit, and the latch_out signal output by the first latch circuit becomes 0. After an odd number of second NOT logic circuits NOT2 logically invert the signal, the output signal out becomes 1.

[0109] In one example, if Figure 3d As shown, if the output node SW is floating, this means that the smit_in signal at the connection point between the first capacitor C1 and the second resistor R2 is set to logic high after passing through the pull-up transistor first PMOS transistor MP1 and the first and second resistors R1 and R2, and then through the RC ((R1+R2)*C1) delay unit. The output of the first Schmitt trigger circuit (SMIT trigger) is 1. When the timing ends, the time_out signal output by the first timing circuit becomes 1, and the mpg signal output by the first OR logic circuit OR1 is 1, turning off the first PMOS transistor MP1. Simultaneously, the output signal of the first Schmitt trigger circuit SMIT1 is latched to 1 by the first latch circuit, and the latch_out signal sent by the first latch circuit is 1. After the odd number of second NOT logic circuits NOT2 are used for logical inversion, the output signal out is 0.

[0110] In one example, if Figure 3eAs shown, if the output node SSW is connected to the high-potential power supply voltage VDD, this means that the smit_in signal at the connection point between the first capacitor C1 and the second resistor R2 is set to a logic high by the output node SW when power is applied, and the output of the first Schmitt trigger circuit SMIT trigger 1 is 1. When the timing ends, the time_out signal output by the first timing circuit becomes 1, and the mpg signal output by the first OR logic circuit OR1 is 1, turning off the first PMOS transistor MP1. Simultaneously, the output signal of the first Schmitt trigger circuit SMIT1 is latched to 1 by the first latch circuit, and the latch_out signal sent by the first latch circuit is 1. After being logically inverted by an odd number of second NOT logic circuits NOT2, the output signal out is 0.

[0111] For example, the timing time of the timing circuit in the embodiment of the present disclosure can be set to be greater than three time constants R2*C1, and is generally set to 30us to 50us.

[0112] See also Figure 4a , Figure 4a A schematic diagram of a first detection module according to an embodiment of the present disclosure is shown.

[0113] In one possible implementation, Figure 4a As shown, the second detection module 20 may include a third NOT logic circuit NOT3, a fourth NOT logic circuit NOT4, an even number of fifth NOT logic circuits NOT5, a second timing circuit Timer2, a second OR logic circuit OR2, a second PMOS transistor MP2, a first NMOS transistor MN1, a third resistor R3, a fourth resistor R4, a second Schmitt trigger circuit SMIT2, a first delay circuit delay, a first AND logic circuit AND1, and a second latch circuit LATCH2.

[0114] The input end of the third NOT logic circuit NOT3 receives an enable signal en, and the output end of the third NOT logic circuit NOT3 is connected to the reset end reset of the second timing circuit Timer2, the reset end reset of the second latch circuit LATCH2, and the first input end of the second OR logic circuit OR2.

[0115] The clock signal terminal of the second timing circuit Timer2 is used to receive the clock signal clk. The output terminal of the second timing circuit Timer2 is connected to the second input terminal of the second OR logic circuit OR2 and the input terminal of the fourth NOT logic circuit NOT4. The output terminal of the fourth NOT logic circuit NOT4 is connected to the enable terminal en of the second Schmitt trigger circuit SMIT2 and the first input terminal of the first AND logic circuit AND1.

[0116] The third input terminal of the second OR logic circuit OR2 is connected to the output terminal of the second latch circuit LATCH2 and the input terminal of the fifth NOT logic circuit NOT5. The output terminal of the second OR logic circuit OR2 is connected to the control terminal of the second PMOS transistor MP2 and the control terminal of the first NMOS transistor MN1.

[0117] The source of the second PMOS transistor MP2 is connected to the data input terminal data of the second latch circuit LATCH2 for receiving the power supply voltage VDD, and the drain of the second PMOS transistor MP2 is connected to the first end of the third resistor R3.

[0118] The second end of the third resistor R3 is connected to the output node SW and the first end of the fourth resistor R4.

[0119] The second end of the fourth resistor R4 is connected to the drain of the first NMOS transistor MN1 and the input end of the second Schmitt trigger circuit SMIT2. The source of the first NMOS transistor MN1 is grounded.

[0120] The output end of the second Schmitt trigger circuit SMIT2 is connected to the input end of the first delay circuit delay,

[0121] The output end of the first delay circuit delay is connected to the second input end of the first AND logic circuit AND1.

[0122] The output terminal of the first AND logic circuit AND1 is connected to the latch control terminal latch of the second latch circuit LATCH2.

[0123] The output terminal of the fifth NOT logic circuit NOT5 is used to output the second signal.

[0124] See also Figure 4b 、 Figure 4c 、 Figure 4d 、 Figure 4e 、 Figure 4f , Figure 4b 、 Figure 4d 、 Figure 4e 、 Figure 4f Schematic diagrams showing the second detection module detecting connection with an inductor, grounding, floating, and connection with a power supply voltage according to an embodiment of the present disclosure are shown respectively. Figure 4c A schematic diagram showing the waveform amplification when connected to an inductor is shown.

[0125] Exemplarily, the enable signal en can be set to be initially low level 0, the time_out signal output by the second timing circuit can be reset to low level 0, and the output signal of the second latch circuit can be reset to low level 0, wherein the second PMOS transistor MP2 is a pull-up transistor. If the control terminal (gate) receives a high level (logic 1), the pull-up P transistor, the second PMOS transistor MP2, is turned off, and the first NMOS transistor MN1 is a pull-down transistor. If the control terminal (gate) receives a high level (logic 1), the pull-down N transistor is turned on, and the smit_in signal at the connection point between the first NMOS transistor MN1 and the fourth resistor R4 is 0; when the enable signal en changes from 0 to 1, the pull-up P transistor, i.e., the second PMOS transistor MP2, is turned on (conducted), and the pull-down N transistor, i.e., the first NMOS transistor MN1, is turned off.

[0126] In one example, if Figure 4b 、 Figure 4c As shown, if the output node SW is connected to an inductor at this point, the inductor's current cannot change suddenly, which means that the output node SW will be set high at the moment the second PMOS transistor turns on. As the current in the inductor gradually increases, the voltage at the output node SW gradually decreases. Before the output node SW drops sufficiently low, the smit_in at the connection point between the first NMOS transistor MN1 and the fourth resistor R4 is set to logic high, and the output of the second Schmitt trigger circuit SMIT2 is 1. At this time, the output signal time_outb of the fourth NOT logic circuit is 1, the pulse signal output by the first AND logic circuit AND1 changes from 0 to 1, the second latch circuit LATCH2 latches VDD, and the second latch circuit LATCH2 sends latch_out as 1, resulting in an output signal out of 1. In this case, the gate of the second PMOS transistor is set to 1, and the second PMOS transistor is turned off. After a set delay time, the pulse signal output by the first AND logic circuit AND1 changes from 1 to 0. When the timing ends, the output signal time_outb of the fourth NOT logic circuit changes from 0 to 1, shielding the delay signal delay_out output by the first delay circuit to prevent the subsequent output node SW from being disturbed, causing the pulse signal output by the first AND logic circuit AND1 to produce a logic flip.

[0127] In one example, if Figure 4dAs shown, if the output node SW is connected to the low-level GND at this time, after the second PMOS transistor is turned on, the smit_in signal at the connection point between the first NMOS transistor MN1 and the fourth resistor R4 remains at 0, and the output of the second Schmitt trigger circuit SMIT2 is 0. At this time, the output signal time_outb of the fourth NOT logic circuit is 1, and the pulse signal output by the first AND logic circuit AND1 remains 0, with no signal latching VDD. The second latch circuit LATCH2 outputs latch_out as 0, and the output signal out is 0. When the timing ends, the output signal time_outb of the fourth NOT logic circuit changes from 0 to 1, turning off the second PMOS transistor. The output signal time_outb of the fourth NOT logic circuit changes from 0 to 1, shielding the delay signal delay_out output by the first delay circuit and preventing subsequent disturbances at the output node SW, causing the pulse signal output by the first AND logic circuit AND1 to undergo a logic flip.

[0128] In one example, if Figure 4e As shown, if the output node SW is floating at this time, after the second PMOS transistor is turned on, the output node SW is set to high, the smit_in signal at the connection point between the first NMOS transistor MN1 and the fourth resistor R4 is set to logic high, and the output of the second Schmitt trigger circuit SMIT2 is 1. At this time, the output signal time_outb of the fourth NOT logic circuit is 1, the pulse signal output by the first AND logic circuit AND1 changes from 0 to 1, the second latch circuit LATCH2 latches VDD, and the second latch circuit LATCH2 sends latch_out as 1, and the output signal out is 1. Simultaneously, the gate of the second PMOS transistor is set to 1, and the second PMOS transistor is turned off. After the set delay time, the pulse signal output by the first AND logic circuit AND1 changes from 1 to 0. When the timing ends, the output signal time_outb of the fourth NOT logic circuit changes from 0 to 1, blocking the delay signal delay_out signal output by the first delay circuit, preventing subsequent disturbances on the output node SW, and causing the pulse signal output by the first AND logic circuit AND1 to undergo a logic flip.

[0129] In one example, if Figure 4fAs shown, if the output node SW is connected to VDD at this time, after the NMOS transistor is turned off, the smit_in at the connection point between the first NMOS transistor MN1 and the fourth resistor R4 is set to logic high, and the output of the second Schmitt trigger circuit SMIT2 is 1. At this time, the output signal time_outb of the fourth NOT logic circuit is 1, and the pulse signal output by the first AND logic circuit AND1 changes from 0 to 1. The second latch circuit LATCH2 latches VDD, and the second latch circuit LATCH2 sends latch_out as 1, and the output signal out is 1. Simultaneously, the gate of the second PMOS transistor is set to 1, and the second PMOS transistor is turned off. After a set delay time, the pulse signal output by the first AND logic circuit AND1 changes from 1 to 0. When the timing ends, the output signal time_outb of the fourth NOT logic circuit changes from 0 to 1, shielding the delay signal delay_out output by the first delay circuit, preventing subsequent disturbances at the output node SW, causing the pulse signal output by the first AND logic circuit AND1 to undergo a logic flip.

[0130] Of course, the above introduction to the first detection module and the second detection module is exemplary. Those skilled in the art may modify the first detection module and the second detection module according to actual conditions and needs, or design the corresponding first detection module and the second detection module according to "using the first detection module 10 and the second detection module 20 to respectively detect whether the output node SW is connected to the inductor, the ground, and the power supply voltage VDD, or the output node SW is floating, and outputting the first signal and the second signal respectively according to the detection results; and using the state determination module 30 to determine the connection state between the output node SW and the inductor based on the first signal and the second signal." Accordingly, the state determination module may also be adaptively designed. For example, as shown in Table 2, the first detection module and the second detection module may be configured to output a low level (logic 0) when detecting that the output node SW is electrically connected to the inductor, and output different logic levels for other detection items, as long as the connection state between the output node SW and the inductor obtained by performing an OR operation on the first signal and the second signal is different from the states of other connection modes.

[0131] Table 2

[0132] Output node SW The first detection module output The second detection module output Status determination module output Connect inductor 0 0 0 Grounding GDN 1 0 1 Connect to power supply voltage VDD 0 1 1 Floating state 1 1 1

[0133] As shown in Table 2, the first detection module detects whether the output node SW is connected to the inductor, the ground, the power supply voltage VDD, or the output node SW is floating, and can output (0, 1, 0, 1) respectively. The second detection module detects whether the output node SW is connected to the inductor, the ground, the power supply voltage VDD, or the output node SW is floating, and can output (0, 1, 1, 1) respectively. In this way, the state determination module can be implemented by an OR logic operation circuit, which performs an OR operation on the first signal and the second signal. Only when the first detection module and the second detection module are both connected to the inductor, the OR logic operation circuit outputs a low level (logic 0). In this way, the embodiment of the present disclosure can determine that the output node SW is connected to the inductor based on the output result (0) of the OR logic operation circuit. Otherwise, it is determined that the output node SW is not connected to the inductor.

[0134] According to the above operation logic, those skilled in the art can design corresponding circuit implementations of the first detection module and the second detection module, which is not limited in the embodiments of the present disclosure.

[0135] Of course, in other embodiments, other first detection modules and second detection modules may be provided through other logical operations or designs, as long as the first detection module 10 and the second detection module 20 can be used to respectively detect whether the output node SW is connected to the inductor, the ground, and the power supply voltage VDD, or whether the output node SW is floating, and the first signal and the second signal are output respectively according to the detection results; and the state determination module 30 can be used to determine the connection state between the output node SW and the inductor according to the first signal and the second signal.

[0136] In a possible implementation, the power drive circuit includes a DC-DC power drive circuit and / or an AC-DC power drive circuit, etc.

[0137] According to one aspect of the present disclosure, a power supply is provided, comprising the detection circuit.

[0138] According to one aspect of the present disclosure, an electronic device is provided, including the power supply described in the electronic device.

[0139] The electronic devices of the embodiments of the present disclosure may include terminals, servers, and other devices that require power. In one example, a terminal is also referred to as user equipment (UE), mobile station (MS), mobile terminal (MT), etc., and is a device that provides voice and / or data connectivity to users, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. Currently, some examples of terminals include: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving (Self-driving), wireless terminals in remote medical surgery (Remote Medical Surgery), wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in the Internet of Vehicles, etc.

[0140] See also Figure 5 , Figure 5 A flow chart of a detection method according to an embodiment of the present disclosure is shown.

[0141] The method is applied to Figure 1 In the detection circuit shown in FIG, the detection circuit is used to detect the connection status between the output node SW of the power drive circuit and the inductor. The circuit includes a first detection module 10, a second detection module 20 and a state determination module 30. Figure 5 As shown, the method includes:

[0142] Step S11, using the first detection module 10 and the second detection module 20 to respectively detect whether the output node SW is connected to the inductor, the ground, or the power supply voltage, or whether the output node SW is floating, and outputting a first signal and a second signal respectively according to the detection results;

[0143] In step S12 , the state determination module 30 is used to determine the connection state between the output node SW and the inductor according to the first signal and the second signal.

[0144] The detection method proposed in the embodiment of the present disclosure detects whether the output node is connected to the inductor, ground, power supply voltage or the output node is floating, and outputs a first signal and a second signal respectively according to the detection results; and determines the connection status of the output node and the inductor according to the first signal and the second signal. The embodiment of the present disclosure can quickly and accurately determine the connection status of the output node of the power drive circuit. In particular, it can quickly and accurately determine the connection status of the output node of the power drive circuit and the inductor, so as to achieve efficient control of the power supply, improve the power supply efficiency, and reduce power consumption.

[0145] In the embodiment of the present disclosure, when all phases need to work, the correct connection of the inductor can be ensured. When the system does not need all DCDC phases to work, but only some phases need to work, whether to open the driving circuit of the corresponding path can also be determined based on whether the inductor is connected to the power tube, thereby achieving the purpose of reducing power consumption.

[0146] In a possible implementation, the method may further include:

[0147] The first detection module 10 is used to detect whether the output node SW is connected to the ground, connected to the power supply voltage, floating, or connected to the inductor.

[0148] The second detection module 20 is used to detect whether the output node SW is connected to the ground, connected to the power supply voltage, floating, or connected to the inductor.

[0149] The first detection module 10 and the second detection module 20 respectively detect different detection items of the output node SW being connected to the ground, connected to the power supply voltage, and the output node SW being floating.

[0150] In a possible implementation, the state determination module 30 includes an AND logic circuit, and determining the connection state between the output node SW and the inductor according to the first signal and the second signal includes:

[0151] AND logic processing is performed on the first signal and the second signal. When the output result of the AND logic circuit is a high level, it is determined that the output node SW is connected to the inductor; otherwise, it is determined that the output node SW is not connected to the inductor.

[0152] In one possible implementation, Figure 3aAs shown, the first detection module 10 may include a first NOT logic circuit NOT1, an odd number of second NOT logic circuits NOT2, a first timing circuit Timer1, a first OR logic circuit OR1, a first PMOS transistor MP1, a first resistor R1, a second resistor R2, a first capacitor C1, a first Schmitt trigger circuit SMIT1 and a first latch circuit LATCH1.

[0153] The input end of the first NOT logic circuit NOT1 receives an enable signal en, and the output end of the first NOT logic circuit NOT1 is connected to the reset end reset of the first timing circuit Timer1, the reset end reset of the first latch circuit LATCH1, and the first input end of the first OR logic circuit OR1.

[0154] The clock signal terminal of the first timing circuit Timer1 is used to receive the clock signal clk, and the output terminal of the first timing circuit Timer1 is connected to the second input terminal of the first OR logic circuit OR1 and the latch control terminal latch of the first latch circuit LATCH1.

[0155] The output terminal of the first OR logic circuit OR1 is connected to the control terminal of the first PMOS transistor MP1.

[0156] The source of the first PMOS transistor MP1 is used to receive the power supply voltage VDD, and the drain of the first PMOS transistor MP1 is connected to the first end of the first resistor R1.

[0157] The second end of the first resistor R1 is connected to the output node SW and the first end of the second resistor R2.

[0158] The second end of the second resistor R2 is connected to the first end of the first capacitor C1 and the input end of the first Schmitt trigger circuit SMIT1. The second end of the first capacitor C1 is grounded.

[0159] The output terminal of the first Schmitt trigger circuit SMIT1 is connected to the data input terminal data of the first latch circuit LATCH1.

[0160] The latch output terminal of the first latch circuit LATCH1 is connected to the input terminal of the second NOT logic circuit NOT2.

[0161] The second NOT logic circuit NOT2 is used to output the first signal. In a possible implementation, Figure 4aAs shown, the second detection module 20 may include a third NOT logic circuit NOT3, a fourth NOT logic circuit NOT4, an even number of fifth NOT logic circuits NOT5, a second timing circuit Timer2, a second OR logic circuit OR2, a second PMOS transistor MP2, a first NMOS transistor MN1, a third resistor R3, a fourth resistor R4, a second Schmitt trigger circuit SMIT2, a first delay circuit delay, a first AND logic circuit AND1, and a second latch circuit LATCH2.

[0162] The input end of the third NOT logic circuit NOT3 receives an enable signal en, and the output end of the third NOT logic circuit NOT3 is connected to the reset end reset of the second timing circuit Timer2, the reset end reset of the second latch circuit LATCH2, and the first input end of the second OR logic circuit OR2.

[0163] The clock signal terminal of the second timing circuit Timer2 is used to receive the clock signal clk. The output terminal of the second timing circuit Timer2 is connected to the second input terminal of the second OR logic circuit OR2 and the input terminal of the fourth NOT logic circuit NOT4. The output terminal of the fourth NOT logic circuit NOT4 is connected to the enable terminal en of the second Schmitt trigger circuit SMIT2 and the first input terminal of the first AND logic circuit AND1.

[0164] The third input terminal of the second OR logic circuit OR2 is connected to the output terminal of the second latch circuit LATCH2 and the input terminal of the fifth NOT logic circuit NOT5. The output terminal of the second OR logic circuit OR2 is connected to the control terminal of the second PMOS transistor MP2 and the control terminal of the first NMOS transistor MN1.

[0165] The source of the second PMOS transistor MP2 is connected to the data input terminal data of the second latch circuit LATCH2 for receiving the power supply voltage VDD, and the drain of the second PMOS transistor MP2 is connected to the first end of the third resistor R3.

[0166] The second end of the third resistor R3 is connected to the output node SW and the first end of the fourth resistor R4.

[0167] The second end of the fourth resistor R4 is connected to the drain of the first NMOS transistor MN1 and the input end of the second Schmitt trigger circuit SMIT2. The source of the first NMOS transistor MN1 is grounded.

[0168] The output end of the second Schmitt trigger circuit SMIT2 is connected to the input end of the first delay circuit delay,

[0169] The output end of the first delay circuit delay is connected to the second input end of the first AND logic circuit AND1.

[0170] The output terminal of the first AND logic circuit AND1 is connected to the latch control terminal latch of the second latch circuit LATCH2.

[0171] The output terminal of the fifth NOT logic circuit NOT5 is used to output the second signal.

[0172] It is understood that the above-mentioned various method embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, this disclosure will not go into details. It is understood by those skilled in the art that in the above-mentioned methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0173] The detection method of the embodiment of the present disclosure corresponds to the aforementioned detection circuit. For a detailed description thereof, please refer to the previous introduction to the detection circuit, which will not be repeated here.

[0174] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A detection circuit, characterized in that: The circuit is used to detect the connection status between the output node of the power drive circuit and the inductor. The circuit includes a first detection module, a second detection module and a status determination module, wherein: The first detection module and the second detection module are both connected to the output node, and are respectively used to detect whether the output node is connected to the inductor, the ground, or the power supply voltage, or whether the output node is floating, and output a first signal and a second signal respectively according to the detection results; The state determination module is connected to the first detection module and the second detection module, and is used to determine the connection state between the output node and the inductor according to the first signal and the second signal. The first detection module includes a first non-logic circuit, an odd number of second non-logic circuits, a first timing circuit, a first OR logic circuit, a first PMOS transistor, a first resistor, a second resistor, a first capacitor, a first Schmitt trigger circuit and a first latch circuit. The input end of the first NOT logic circuit receives an enable signal, and the output end of the first NOT logic circuit is connected to the reset end of the first timing circuit, the reset end of the first latch circuit, and the first input end of the first OR logic circuit. The clock signal terminal of the first timing circuit is used to receive a clock signal, and the output terminal of the first timing circuit is connected to the second input terminal of the first OR logic circuit and the latch control terminal of the first latch circuit. The output terminal of the first OR logic circuit is connected to the control terminal of the first PMOS transistor, The source of the first PMOS transistor is used to receive a power supply voltage, and the drain of the first PMOS transistor is connected to the first end of the first resistor. The second end of the first resistor is connected to the output node and the first end of the second resistor, The second end of the second resistor is connected to the first end of the first capacitor and the input end of the first Schmitt trigger circuit, and the second end of the first capacitor is grounded. The output terminal of the first Schmitt trigger circuit is connected to the data input terminal of the first latch circuit, The latch output terminal of the first latch circuit is connected to the input terminal of the second non-logic circuit, The second NOT logic circuit is used to output the first signal, The second detection module includes a third non-logic circuit, a fourth non-logic circuit, an even number of fifth non-logic circuits, a second timing circuit, a second OR logic circuit, a second PMOS transistor, a first NMOS transistor, a third resistor, a fourth resistor, a second Schmitt trigger circuit, a first delay circuit, a first AND logic circuit, and a second latch circuit. The input end of the third NOT logic circuit receives an enable signal, and the output end of the third NOT logic circuit is connected to the reset end of the second timing circuit, the reset end of the second latch circuit, and the first input end of the second OR logic circuit. The clock signal terminal of the second timing circuit is used to receive a clock signal. The output terminal of the second timing circuit is connected to the second input terminal of the second OR logic circuit and the input terminal of the fourth NOT logic circuit. The output terminal of the fourth NOT logic circuit is connected to the enable terminal of the second Schmitt trigger circuit and the first input terminal of the first AND logic circuit. The third input terminal of the second OR logic circuit is connected to the output terminal of the second latch circuit and the input terminal of the fifth NOT logic circuit, and the output terminal of the second OR logic circuit is connected to the control terminal of the second PMOS transistor and the control terminal of the first NMOS transistor. The source of the second PMOS transistor is connected to the data input terminal of the second latch circuit for receiving a power supply voltage, and the drain of the second PMOS transistor is connected to the first terminal of the third resistor. The second end of the third resistor is connected to the output node and the first end of the fourth resistor. The second end of the fourth resistor is connected to the drain of the first NMOS transistor and the input end of the second Schmitt trigger circuit, and the source of the first NMOS transistor is grounded. The output end of the second Schmitt trigger circuit is connected to the input end of the first delay circuit, The output end of the first delay circuit is connected to the second input end of the first AND logic circuit. The output terminal of the first AND logic circuit is connected to the latch control terminal of the second latch circuit. The output terminal of the fifth NOT logic circuit is used to output the second signal.

2. The circuit according to claim 1, wherein: The power drive circuit includes a DC-DC power drive circuit and / or an AC-DC power drive circuit.

3. A power supply, characterized in that: The power supply comprises the detection circuit according to any one of claims 1-2.

4. An electronic device, characterized in that: The electronic device comprises the power supply according to claim 3.

5. A detection method, characterized in that: The method is applied to a detection circuit, which is used to detect the connection status between the output node of the power drive circuit and the inductor. The circuit includes a first detection module, a second detection module, and a status determination module. The method includes: Using the first detection module and the second detection module to respectively detect whether the output node is connected to the inductor, the ground, or the power supply voltage or whether the output node is floating, and outputting a first signal and a second signal respectively according to the detection results; Determining the connection state between the output node and the inductor according to the first signal and the second signal using the state determination module, The first detection module includes a first non-logic circuit, an odd number of second non-logic circuits, a first timing circuit, a first OR logic circuit, a first PMOS transistor, a first resistor, a second resistor, a first capacitor, a first Schmitt trigger circuit and a first latch circuit. The input end of the first NOT logic circuit receives an enable signal, and the output end of the first NOT logic circuit is connected to the reset end of the first timing circuit, the reset end of the first latch circuit, and the first input end of the first OR logic circuit. The clock signal terminal of the first timing circuit is used to receive a clock signal, and the output terminal of the first timing circuit is connected to the second input terminal of the first OR logic circuit and the latch control terminal of the first latch circuit. The output terminal of the first OR logic circuit is connected to the control terminal of the first PMOS transistor, The source of the first PMOS transistor is used to receive a power supply voltage, and the drain of the first PMOS transistor is connected to the first end of the first resistor. The second end of the first resistor is connected to the output node and the first end of the second resistor, The second end of the second resistor is connected to the first end of the first capacitor and the input end of the first Schmitt trigger circuit, and the second end of the first capacitor is grounded. The output terminal of the first Schmitt trigger circuit is connected to the data input terminal of the first latch circuit, The latch output terminal of the first latch circuit is connected to the input terminal of the second non-logic circuit, The second NOT logic circuit is used to output the first signal, The second detection module includes a third non-logic circuit, a fourth non-logic circuit, an even number of fifth non-logic circuits, a second timing circuit, a second OR logic circuit, a second PMOS transistor, a first NMOS transistor, a third resistor, a fourth resistor, a second Schmitt trigger circuit, a first delay circuit, a first AND logic circuit, and a second latch circuit. The input end of the third NOT logic circuit receives an enable signal, and the output end of the third NOT logic circuit is connected to the reset end of the second timing circuit, the reset end of the second latch circuit, and the first input end of the second OR logic circuit. The clock signal terminal of the second timing circuit is used to receive a clock signal. The output terminal of the second timing circuit is connected to the second input terminal of the second OR logic circuit and the input terminal of the fourth NOT logic circuit. The output terminal of the fourth NOT logic circuit is connected to the enable terminal of the second Schmitt trigger circuit and the first input terminal of the first AND logic circuit. The third input terminal of the second OR logic circuit is connected to the output terminal of the second latch circuit and the input terminal of the fifth NOT logic circuit, and the output terminal of the second OR logic circuit is connected to the control terminal of the second PMOS transistor and the control terminal of the first NMOS transistor. The source of the second PMOS transistor is connected to the data input terminal of the second latch circuit for receiving a power supply voltage, and the drain of the second PMOS transistor is connected to the first terminal of the third resistor. The second end of the third resistor is connected to the output node and the first end of the fourth resistor. The second end of the fourth resistor is connected to the drain of the first NMOS transistor and the input end of the second Schmitt trigger circuit, and the source of the first NMOS transistor is grounded. The output end of the second Schmitt trigger circuit is connected to the input end of the first delay circuit, The output end of the first delay circuit is connected to the second input end of the first AND logic circuit. The output terminal of the first AND logic circuit is connected to the latch control terminal of the second latch circuit. The output terminal of the fifth NOT logic circuit is used to output the second signal.

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