A current source-based bias circuit

Abstract

The present invention discloses a bias circuit based on a current source, which relates to the field of circuit technologies and includes a P-type MOS transistor MP1, a P-type MOS transistor MP2, a P-type MOS transistor MP3, a P-type MOS transistor MP4, an N-type MOS transistor MN0, an N-type MOS transistor MN1, an N-type MOS transistor MN2, an N-type MOS transistor MN3, an N-type MOS transistor MN4, a resistor R1, a resistor R2, a bias current source Iref, a VDD voltage terminal, a reference voltage Vref1, a reference voltage Vref2, an S complementary signal terminal, an S' complementary signal terminal, and a bias current Ib. It segments the bias current source to ensure that while segmenting, the current magnitudes of the two current sources can be well matched.

Description

Technical Field

[0001] The present invention relates to the technical field of circuits, and in particular to a bias circuit based on a current source. Background Art

[0002] Currently, in a non-volatile memory, a charge pump system basically provides a working voltage required for the non-volatile memory. The charge pump system includes a bias circuit, a clock circuit, and a charge pump main body. The bias circuit generates a bias current, mirrors the bias current to the clock circuit, the clock circuit generates a clock signal and gives it to the charge pump main body, and the charge pump outputs a voltage according to the clock signal.

[0003] In order to ensure that when the current on the Flash word line is the largest, it can completely flow out to the load terminal, while taking into account power consumption savings, according to the weight stored in the Flash, the maximum value of the word line current can be estimated, so as to determine the required maximum bias current, and accordingly the bias current is set in a segmented adjustable form. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a bias circuit based on a current source for the deficiencies in the background art, which segments the bias current source and ensures that the currents of the two current sources can be well matched while segmenting.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A bias circuit based on a current source includes a P-type MOS transistor MP1, a P-type MOS transistor MP2, a P-type MOS transistor MP3, a P-type MOS transistor MP4, an N-type MOS transistor MN0, an N-type MOS transistor MN1, an N-type MOS transistor MN2, an N-type MOS transistor MN3, an N-type MOS transistor MN4, a resistor R1, a resistor R2, a bias current source Iref, a VDD voltage terminal, a reference voltage Vref1, a reference voltage Vref2, an S complementary signal terminal, an S' complementary signal terminal, and a bias current Ib;

[0007] Among them, one end of the bias current source Iref is respectively connected to the VDD voltage terminal, the source of the P-type MOS transistor MP1, and the source of the P-type MOS transistor MP3. The other end of the bias current source Iref is respectively connected to the drain of the N-type MOS transistor MN0, the gate of the N-type MOS transistor MN0, the gate of the N-type MOS transistor MN1, and the source of the N-type MOS transistor MN3. The source of the N-type MOS transistor MN0 is grounded, the source of the N-type MOS transistor MN1 is grounded, the drain of the N-type MOS transistor MN1 is connected to the source of the N-type MOS transistor MN2, the gate of the N-type MOS transistor MN2 is connected to the VDD voltage terminal, the drain of the N-type MOS transistor MN2 is respectively connected to one end of the resistor R1 and the reference voltage Vref1. The other end of the resistor R1 is respectively connected to one end of the resistor R2, the gate of the P-type MOS transistor MP1, and the gate of the P-type MOS transistor MP3. The other end of the resistor R2 is respectively connected to the reference voltage Vref2 and the drain of the P-type MOS transistor MP2. The gate of the P-type MOS transistor MP2 is grounded, the source of the P-type MOS transistor MP2 is connected to the drain of the P-type MOS transistor MP1, the drain of the P-type MOS transistor MP3 is connected to the source of the P-type MOS transistor MP4, the gate of the P-type MOS transistor MP4 is connected to the S' complementary signal terminal, the drain of the P-type MOS transistor MP4 is connected to the bias current Ib, the source of the N-type MOS transistor MN3 is grounded, the drain of the N-type MOS transistor MN3 is connected to the source of the N-type MOS transistor MN4, the gate of the N-type MOS transistor MN4 is connected to the S complementary signal terminal, and the drain of the N-type MOS transistor MN4 is connected to the bias current Ib.

[0008] Compared with the prior art, the present invention adopts the above technical solutions and has the following technical effects:

[0009] A bias circuit based on a current source according to the present invention segments the bias current source to ensure that the currents of the two current sources can be well matched while segmenting. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a circuit diagram of a bias circuit based on a current source according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] The technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings:

[0012] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0013] A bias circuit based on a current source, comprising a P-type MOS transistor MP1, a P-type MOS transistor MP2, a P-type MOS transistor MP3, a P-type MOS transistor MP4, an N-type MOS transistor MN0, an N-type MOS transistor MN1, an N-type MOS transistor MN2, an N-type MOS transistor MN3, an N-type MOS transistor MN4, a resistor R1, a resistor R2, a bias current source Iref, a VDD voltage terminal, a reference voltage Vref1, a reference voltage Vref2, an S complementary signal terminal, an S' complementary signal terminal, and a bias current Ib;

[0014] One end of the bias current source Iref is respectively connected to the VDD voltage terminal, the source of the P-type MOS transistor MP1, and the source of the P-type MOS transistor MP3. The other end of the bias current source Iref is respectively connected to the drain of the N-type MOS transistor MN0, the gate of the N-type MOS transistor MN0, the gate of the N-type MOS transistor MN1, and the source of the N-type MOS transistor MN3. The source of the N-type MOS transistor MN0 is grounded. The source of the N-type MOS transistor MN1 is grounded. The drain of the N-type MOS transistor MN1 is connected to the source of the N-type MOS transistor MN2. The gate of the N-type MOS transistor MN2 is connected to the VDD voltage terminal. The drain of the N-type MOS transistor MN2 is respectively connected to one end of the resistor R1 and the reference voltage Vref1. The other end of the resistor R1 is respectively connected to one end of the resistor R2, the gate of the P-type MOS transistor MP1, and the gate of the P-type MOS transistor MP3. The other end of the resistor R2 is respectively connected to the reference voltage Vref2 and the drain of the P-type MOS transistor MP2. The gate of the P-type MOS transistor MP2 is grounded. The source of the P-type MOS transistor MP2 is connected to the drain of the P-type MOS transistor MP1. The drain of the P-type MOS transistor MP3 is connected to the source of the P-type MOS transistor MP4. The gate of the P-type MOS transistor MP4 is connected to the S' complementary signal terminal. The drain of the P-type MOS transistor MP4 is connected to the bias current Ib. The source of the N-type MOS transistor MN3 is grounded. The drain of the N-type MOS transistor MN3 is connected to the source of the N-type MOS transistor MN4. The gate of the N-type MOS transistor MN4 is connected to the S complementary signal terminal. The drain of the N-type MOS transistor MN4 is connected to the bias current Ib.

[0015] The present invention segments the bias current source to ensure that the currents of the two current sources can be well matched while segmenting. MN3, MN4 and MP3, MP4 respectively represent NMOS and PMOS current sources with a size of Ib. MN1, MN2 and MP1, MP2 are respectively the mirror reference current sources thereof. The figure also shows the sources of the reference voltage Vref1 and the reference voltage Vref2. The reference voltages are set in this way to make the source voltage of the current source equal to the voltage of its reference drain terminal to ensure the matching of the current magnitudes. The S complementary signal terminal and the S' complementary signal terminal, as a pair of complementary signals, control the conduction and cutoff of MN4 and MP4 to achieve segmented regulation of the bias current Ib.

[0016] Only certain exemplary embodiments of the present invention have been described by way of illustration. Without doubt, for those of ordinary skill in the art, the described embodiments can be modified in various different ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A bias circuit based on a current source, characterized in that: It includes P-type MOS transistor MP1, P-type MOS transistor MP2, P-type MOS transistor MP3, P-type MOS transistor MP4, N-type MOS transistor MN0, N-type MOS transistor MN1, N-type MOS transistor MN2, N-type MOS transistor MN3, N-type MOS transistor MN4, resistor R1, resistor R2, bias current source Iref, VDD voltage terminal, reference voltage Vref1, reference voltage Vref2, S complementary signal terminal, S' complementary signal terminal, and bias current Ib; Among them, one end of the bias current source Iref is respectively connected to the VDD voltage terminal, the source of the P-type MOS transistor MP1, and the source of the P-type MOS transistor MP3. The other end of the bias current source Iref is respectively connected to the drain of the N-type MOS transistor MN0, the gate of the N-type MOS transistor MN0, the gate of the N-type MOS transistor MN1, and the gate of the N-type MOS transistor MN3. The source of the N-type MOS transistor MN0 is grounded. The source of the N-type MOS transistor MN1 is grounded. The drain of the N-type MOS transistor MN1 is connected to the source of the N-type MOS transistor MN2. The gate of the N-type MOS transistor MN2 is connected to the VDD voltage terminal. The drain of the N-type MOS transistor MN2 is respectively connected to one end of the resistor R1 and the reference voltage Vref1. The other end of the resistor R1 is respectively connected to one end of the resistor R2, the gate of the P-type MOS transistor MP1, and the gate of the P-type MOS transistor MP3. The other end of the resistor R2 is respectively connected to the reference voltage Vref2 and the drain of the P-type MOS transistor MP2. The gate of the P-type MOS transistor MP2 is grounded. The source of the P-type MOS transistor MP2 is connected to the drain of the P-type MOS transistor MP1. The drain of the P-type MOS transistor MP3 is connected to the source of the P-type MOS transistor MP4. The gate of the P-type MOS transistor MP4 is connected to the S' complementary signal terminal. The drain of the P-type MOS transistor MP4 is connected to the bias current Ib. The source of the N-type MOS transistor MN3 is grounded. The drain of the N-type MOS transistor MN3 is connected to the source of the N-type MOS transistor MN4. The gate of the N-type MOS transistor MN4 is connected to the S complementary signal terminal. The drain of the N-type MOS transistor MN4 is connected to the bias current Ib.

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