Assembly code file generation method, device and electronic equipment for test case

Abstract

The application provides a test case assembly code file generation method and device and electronic equipment, and relates to the technical field of computers. The method comprises the following steps: determining at least one target instruction meeting a preset limited condition from an instruction set test point file, reading test point information of the at least one target instruction; obtaining a random value generation condition corresponding to the at least one target instruction, and generating at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction, and generating an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value. The embodiment of the application realizes coverage of a critical scene, improves the coverage rate of the critical scene, can verify instruction set information comprehensively, and further finds potential abnormalities.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular, the present application relates to a test case assembly code file generation method and device and electronic equipment. BACKGROUND

[0002] RISCV (pronounced "RISC-FIVE") is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC), and V represents the fifth generation of RISC (reduced instruction set computer). RISC refers to a small number of instructions with high usage frequency, and provides some necessary instructions to support operating systems and high-level languages. According to this principle, the computer developed on this basis is RISC-V instruction set, which is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC). RISCV is a new instruction set based on the continuous development and maturity of the instruction set.

[0003] The existing RISCV instruction set test scheme is to manually edit the assembly code file of the test case corresponding to the RISCV instruction set test point file. The specific process is to manually select critical values, typical values and a small number of custom values as input source operands, and then edit the assembly code of the test case corresponding to the source operand, so as to test common function scenarios such as integer addition and subtraction by RISCV instruction set. Specifically, when performing logical and operation, "64'hffff_ffff_ffff_ffff, 64'h0000_0000_0000_0000" are selected as critical values, "64'h 5555_5555_5555_5555, 64'h AAAA_AAAA_AAAA_AAAA" are selected as typical values, and the above critical values, typical values and custom values are used to construct one by one test points, and then the assembly code of the test case corresponding to the test point of the target instruction is edited to verify each function scenario.

[0004] However, for various instructions, each input source operand has 64-bit or 32-bit random space, which means that there are 2 64 or 2 32 values, such as the above logical and operation has 2 64 *2 64 or 2 32 *2 32The combination of the source operands is basically unable to cover all the combinations, and most of the combination scenarios of the source operands are equivalent. The instruction test points are constructed by using the above critical values, typical values, and a small number of self-defined values, which can verify limited critical scenarios and cannot cover all critical scenarios, such as causing insufficient critical scenario coverage, thereby failing to comprehensively verify various test points of the instruction set, and causing some exceptions to be ignored. SUMMARY

[0005] The embodiment provides a method and device for generating an assembly code file of a test case, an electronic device, a computer readable storage medium, and a computer program product, to solve the technical problem of insufficient critical scenario coverage.

[0006] According to an aspect of an embodiment of the present application, a method for generating an assembly code file of a test case is provided, which includes:

[0007] Determining at least one target instruction meeting a preset limited condition from an instruction set test point file, and reading test point information of the at least one target instruction; the instruction set test point file includes at least one instruction and test point information of the at least one instruction;

[0008] Obtaining a random value generation condition corresponding to the at least one target instruction, and generating at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction;

[0009] Generating an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.

[0010] In a possible implementation, the test point information includes at least one source operand and a corresponding value of the source operand;

[0011] Generating at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction includes:

[0012] Obtaining a value of at least one source operand of the at least one target instruction, and determining a value range of the source operand according to the value of the source operand;

[0013] Determining a value range of the random value according to the value range of the source operand;

[0014] Generating at least one random value corresponding to the at least one target instruction according to the random value generation condition and the value range of the random value.

[0015] In a possible implementation, generating at least one random value corresponding to the at least one target instruction according to the random value generation condition and the value range of the random value includes:

[0016] If the random value generation condition comprises the setting seed condition, a seed set for the at least one target instruction is acquired, and at least one random value corresponding to the at least one target instruction is generated according to the value range of the random value and the seed set for the at least one target instruction.

[0017] In a possible implementation, generating at least one random value corresponding to the at least one target instruction according to the random value generation condition and the value range of the random value comprises:

[0018] If the random value generation condition comprises the setting iteration number condition, an iteration number of the random value set for the at least one target instruction is acquired, and at least one random value corresponding to the at least one target instruction is determined according to the value range of the random value and the iteration number of the random value.

[0019] In a possible implementation, generating the assembly code file of the test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value comprises:

[0020] Assembling the test case assembly code of each target instruction according to the test point information of each target instruction and the at least one random value of each target instruction;

[0021] Combining the test case assembly code of each target instruction according to a preset rule to generate the assembly code of the test case corresponding to the instruction file.

[0022] In a possible implementation, the test point information further comprises an instruction unique identifier; and the value of the source operand comprises a typical value, a critical value, and a user-defined value.

[0023] Assembling the test case assembly code of each target instruction according to the test point information of each target instruction and the at least one random value of each target instruction comprises:

[0024] Taking at least one of the typical value, the critical value, the user-defined value, and the random value as the input value of the source operand of the target instruction;

[0025] Calling the test case assembly template corresponding to each target instruction, and filling the instruction unique identifier of each target instruction and the input value of the source operand into the corresponding test case assembly template to generate the assembly code of the test case corresponding to each target instruction.

[0026] In a possible implementation, the test case assembly template comprises a placeholder corresponding to the unique identifier of the target instruction and the input value of the source operand.

[0027] According to another aspect of the embodiments of the present application, an apparatus is provided in a possible implementation, the apparatus comprising:

[0028] The target instruction obtaining module is configured to determine at least one target instruction meeting a preset limited condition from the instruction set test point file, and read test point information of the at least one target instruction; the instruction set test point file includes at least one instruction and test point information of the at least one instruction;

[0029] The random value generating module is configured to obtain a random value generation condition corresponding to the at least one target instruction, and generate at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction;

[0030] The assembly code generating module is configured to generate an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.

[0031] According to another aspect of the embodiments of the present application, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the method provided in the first aspect when executing the program.

[0032] According to another aspect of the embodiments of the present application, a computer readable storage medium is provided, which stores a computer program, and the computer program is executable on a processor to implement the steps of the method provided in the first aspect.

[0033] According to another aspect of the embodiments of the present application, a computer program product is provided, which includes computer instructions stored in a computer readable storage medium, and when a processor of a computer device reads the computer instructions from the computer readable storage medium, the processor executes the computer instructions to make the computer device execute the steps of the method provided in the first aspect.

[0034] The technical scheme provided by the embodiments of the present application has the beneficial effects that:

[0035] The embodiments of the present application first determine at least one target instruction meeting a preset specified condition from an instruction file, and read test point information of the at least one target instruction; then obtain a random value generation condition corresponding to the at least one target instruction, and generate at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction, and generate an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value. The embodiments of the present application implement coverage of critical scenarios, improve the coverage rate of critical scenarios, can comprehensively verify test points of an instruction set, and further find potential abnormalities. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced.

[0037] Figure 1 A flowchart of a test case assembly code file generation method provided by the embodiments of the present application;

[0038] Figure 2 A schematic diagram of instructions and test point information stored in an instruction set test point file provided by the embodiments of the present application;

[0039] Figure 3 A schematic diagram of an instruction set test point file generating a test case assembly code file provided by the embodiments of the present application;

[0040] Figure 4 A schematic diagram of a test case assembly template provided by the embodiments of the present application;

[0041] Figure 5 A schematic diagram of a test case assembly code file corresponding to an instruction file set provided by the embodiments of the present application;

[0042] Figure 6 A schematic diagram of the number of test cases generated by the embodiments of the present application in the case of the same random value of a target instruction;

[0043] Figure 7 A structural schematic diagram of a test case assembly code file generation device provided by the embodiments of the present application;

[0044] Figure 8 A structural schematic diagram of an electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0045] The embodiments of the present application will be described below in conjunction with the drawings in the present application. It should be understood that the embodiments described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.

[0046] Those skilled in the art can understand that the singular forms "a", "an" and "the" used herein include plural forms unless specifically stated otherwise. It should be further understood that the terms "include" and "contain" used in the embodiments of the present application mean that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude other features, information, data, steps, operations, elements, components and / or their combinations supported by the present technology. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or it can mean that the element and the other element are connected through an intermediate element. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The term "and / or" used herein indicates that at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0047] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0048] First, several terms related to the present application are introduced and explained:

[0049] RISCV (pronounced "RISC-FIVE") is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC), and V represents the fifth generation of RISC (reduced instruction set computer). RISC is a computer that contains a small number of instructions with high frequency of use and provides some necessary instructions to support operating systems and high-level languages. According to this principle, the RISC-V instruction set is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC). RISCV is a new instruction set established on the basis of the continuous development and maturity of the instruction set.

[0050] The instruction set is a set of instructions used to calculate and control the computer system in the CPU, and each new type of CPU specifies a series of instruction systems that cooperate with other hardware circuits when designed. The advancement of the instruction set also relates to the performance of the CPU, and it is also an important symbol of the performance of the CPU.

[0051] Terminal, the terminal device in the embodiments of the present application is a device with wireless transceiving function, which can be referred to as terminal, user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal device, vehicle-mounted terminal device, industrial control terminal device, UE unit, UE station, mobile station, remote station, remote terminal device, mobile device, UE terminal device, wireless communication device, UE agent or UE apparatus, etc. The terminal device can be fixed or mobile, for example, the terminal device can be mobile phone, pad, desktop computer, notebook computer, all-in-one machine, vehicle-mounted terminal, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, cellular phone, cordless phone, session initiation protocol (SIP) phone, wireless local loop (WLL) station, personal digital assistant (PDA), handheld device with wireless communication function, computing device or other processing device connected to wireless modem, wearable device, terminal device in future mobile communication network or terminal device in future evolved public land mobile network (PLMN), etc.

[0052] To solve at least one of the above problems or improve the related art, a method and device for generating an assembly code file of a test case, an electronic device, a computer readable storage medium, and a computer program product are provided. The method includes determining at least one target instruction that meets a preset specified condition from an instruction set test point file, reading test point information of the at least one target instruction, obtaining a random value generation condition corresponding to the at least one target instruction, generating at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction, and generating an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value. The critical scenario can be covered, the coverage of the critical scenario is improved, the instruction set information can be verified comprehensively, and potential faults can be found.

[0053] The technical solutions of the embodiments of the present application and the technical effects of the technical solutions of the present application are described below through the description of several exemplary embodiments. It should be noted that the following embodiments can be mutually referenced, borrowed or combined. For the same terms, similar features and similar implementation steps in different embodiments, they are not described repeatedly.

[0054] In the embodiments of the present application, a method for generating an assembly code file of a test case is provided, as shown in Figure 1 The method includes the following steps.

[0055] In step S101, at least one target instruction that meets a preset specified condition is determined from an instruction set test point file, and test point information of the at least one target instruction is read. The instruction set test point file includes at least one instruction and test point information of the at least one instruction.

[0056] In the embodiments of the present application, the instruction set test point file refers to a collection of instructions and a collection of test point information corresponding to the instructions. Specifically, the instruction set test point file can be an excel file.

[0057] In the embodiments of the present application, the instruction set test point file includes at least one instruction and test point information of the at least one instruction. The instruction set can be a RISCV instruction set, which can include instructions such as logical AND, logical integer AND, logical addition, logical integer addition, etc.

[0058] In the embodiments of the present application, the instruction set test point file includes target instructions and partial test point information of the target instructions. The test point information in the instruction set test point file includes some typical values, boundary values and user-defined values taken by each source operand.

[0059] It should be emphasized that the test points of the embodiments of the present application are not limited to any one or a combination of the above-mentioned critical values, typical values and user-defined values, the above-mentioned combination cannot cover all critical scenarios, and a random value needs to be introduced, that is, the test point is any one or a combination of several of the critical value, the typical value, the user-defined value and the random value, such as for the operation of two source operands, the test point can be a combination of random values and random values, a combination of critical values and random values, a combination of typical values and critical values, and the like, and the determination of the random value will be described in detail later.

[0060] The test point information of the embodiments of the present application includes a unique identifier of the instruction, at least one source operand and the value of each source operand.

[0061] The unique identifier of the instruction can be an instruction name, such as the instruction name of the logical AND instruction is "RV64I_ogical_AND", where "RV64I" is a basic integer instruction set, 64-bit register bit width, the basic integer instruction is named "I" (the prefixes RV32, RV64 and RV128 represent the register bit width), which includes integer calculation instructions, integer load, integer store and control flow instructions, and the "I" class instruction of the corresponding bit width must be implemented in the design of the RISC-V of different register bit widths, that is, the "I" class instruction must be implemented.

[0062] The instruction set test point file of the embodiments of the present application stores various instructions and test point information of various instructions, but not all instructions need to generate a corresponding test case code file, therefore, some limited conditions are set to filter out the target instruction from the instruction set test point file through the preset limited conditions.

[0063] Specifically, the preset defined conditions can be "inst_only", "inst_category_only", "inst_exclusive", and "inst_category_exclusive", etc., wherein "inst_only" is used to limit the assembly code for generating the test case of the specified instruction, for example, the code file for limiting to generate the test case corresponding to the "logical and" instruction, and the "logical and" instruction is the target instruction; "inst_category_only" is used to limit the code file for generating the test case of the specified category instruction, for example, the logical integer addition "ADDI", the "I" identifier integer instruction, the assembly code for limiting to generate the test case of the instruction with the integer as the source operand, and the instruction with the integer as the source operand is determined as the target instruction, in addition to I, the types such as " / M / A / F / D / C" can also be used, which respectively correspond to the multiplication and division, atom, single precision, double precision, and compressed instruction types; "inst_exclusive" is opposite to "inst_only", and is used to limit the code file for not generating the test case of the specified category, for example, the code file for limiting to not generate the test case corresponding to the logical minus instruction, and the instructions other than the "logical minus" instruction are the target instructions; "inst_category_exclusive" is opposite to "inst_category_only", and is used to limit the code file for not generating the test case of the specified category instruction, for example, the code file for limiting to not generate the test case of the instruction with the floating point number as the source operand, and the like.

[0064] The embodiment of the present application reads the instruction set test point file by calling the python openpyxl module, reads the excel file, and needs to import the python openpyxl module. Specifically, when reading an excel file, the Path module and the openpyxl module are needed to be imported, the Path module is used to set the path and the file name, and the excel file is read through the openpyxl module.

[0065] In addition, it needs to be emphasized that the instruction set test point file in the embodiment of the present application stores a plurality of instructions and test point information of each instruction, the test point information in the instruction set test point file is recorded according to a certain rule, and the openpyxl module also follows the rule when reading the instruction set test point file, for example, as shown in the following table. Figure 2

[0066] ​The instruction in the first row is "AND", involving the operator "AND", involving the operation number "rs1", "rs2" and "rd", wherein "rs1" and "rs2" are source operation numbers, and "rd" is a destination operation number; the operation logic involved is x[rd] = x[rs1] & x[rs2], that is, the result of the bitwise "AND" of register x[rs1] and register x[rs2] is written to x[rd], and the macro command involved is Macro:TEST_RR_OP;

[0067] "AND_rs1_max" in the second row indicates the maximum value of the source operation number rs1 in the instruction "AND", which is "u64'hFFFF_FFFF_FFFF_FFFF", and note that the underscore is used in "AND_rs1_max" to indicate that this is a critical value, and "u" indicates an unsigned number and "s" indicates a signed number;

[0068] "AND_rs1_min" in the third row indicates the minimum value of the source operation number rs1 in the instruction "AND", which is "u64'h0000_0000_0000_0000", and note that the underscore is used in "AND_rs1_min" to indicate that this is a critical value;

[0069] "AND.rs1.typical" in the fourth to seventh rows indicates that the typical value of the source operation number rs1 in the instruction "AND" is "u64'h5555_5555_5555_5555", "u64'hAAAA_AAAA_AAAA_AAAA", "u64'hFFFFF_FFFF_FFFF_FFFE (next smaller value)", and "u64'h0000_0000_0000_0001 (next smaller value)";

[0070] Similarly, "AND_rs2_max" in the eighth row indicates the maximum value of the source operation number rs2 in the instruction "AND", which is "u64'hFFFF_FFFF_FFFF_FFFF"; "AND_rs2_min" in the ninth row indicates the minimum value of the source operation number rs2 in the instruction "AND", which is "u64'h0000_0000_0000_0000", and "AND.rs2.min" in the ninth to twelfth rows indicates that the typical value of the source operation number rs1 in the instruction "AND" is "u64'h5555_5555_5555_5555", "u64'hAAAA_AAAA_AAAA_AAAA", "u64'hFFFFF_FFFF_FFFF_FFFE", and "u64'h0000_0000_0000_0001".

[0071] In step S102, a random value generation condition corresponding to at least one target instruction is acquired, and at least one random value corresponding to the at least one target instruction is generated according to the random value generation condition corresponding to the at least one target instruction.

[0072] The random value generation condition in the embodiment of the present application is used to limit the generated random value, for example, setting a seed for the target instruction. The seed affects the result of randomization. Specifically, for example, if the seed is set to 0, the same random value is generated. If the seed is set to 1, a sequence of random values is generated, for example, the generated random value sequence is “10, 20, 30, 40……”.

[0073] In addition to setting the seed, the random value generation condition in the embodiment of the present application can also set the number of iterations. For example, if the number of iterations is 1, 1 set of random values is generated, and the assembly code of the test case of each group of target instructions in the generated test case assembly code file is 1 set. On the basis of the number of iterations being 1, if the number of iterations is limited to 2, two sets of random values will be generated, and another test case assembly code file will be generated. The assembly code of the test case assembly in the test case assembly code file is 2 sets.

[0074] The random value generation conditions corresponding to different target instructions in the embodiment of the present application can be different. The random value generation conditions need to be set for each target instruction according to the actual situation. The embodiment of the present application does not limit this.

[0075] In step S103, the test case assembly code file corresponding to the instruction set test point file is generated according to the test point information of the at least one target instruction and the at least one random value.

[0076] In the embodiment of the present application, after reading the test point information of the target instruction and generating the at least one random value corresponding to the target instruction, the test case assembly code file corresponding to the instruction set test point file is generated according to the test point information of the target instruction and the at least one random value.

[0077] As shown in FIG. 1, Figure 3 The process of converting the instruction set test point file into the test case assembly code file is shown in the embodiment of the present application. The target instruction is determined from the instruction set test point file. The target instruction and the test point information of the target instruction are read and parsed using the pythonopenpyxl module. Then, at least one random value corresponding to at least one target instruction is generated using the random value generation condition. The test case assembly code file corresponding to the instruction set test point file is generated according to the test point information of each target instruction and the random value.

[0078] The embodiment of the present application first determines at least one target instruction meeting a preset specified condition from an instruction set test point file, reads test point information of the at least one target instruction; then acquires a random value generation condition corresponding to the at least one target instruction, and generates at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction, and generates an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value. The embodiment of the present application realizes coverage of a critical scenario, improves the coverage rate of the critical scenario, can comprehensively verify instruction set information, and further discovers potential faults.

[0079] The embodiment of the present application provides a possible implementation manner, and the test point information includes at least one source operand and a corresponding value of the source operand;

[0080] According to the random value generation condition corresponding to the at least one target instruction, the at least one random value corresponding to the at least one target instruction is generated, including:

[0081] The value of the at least one source operand of the at least one target instruction is acquired, and the value range of the source operand is determined according to the value of the source operand;

[0082] According to the value range of the source operand, the value range of the random value is determined;

[0083] According to the random value generation condition and the value range of the random value, the at least one random value corresponding to the at least one target instruction is generated.

[0084] The random value of the embodiment of the present application is randomly generated through the random value generation condition. Different instructions can correspond to different random value generation conditions, and the random value is generated according to the random value generation condition. However, the random value is also the value of the operand, therefore, the random value needs to be located in the value range of the source operand, and the value range of the source operand is the value range of the random value.

[0085] Specifically, continuing the above example, the maximum value of the above source operand rs1 is “u64’hFFFF_FFFF_FFFF_FFFF”, and the minimum value is “u64’h0000_0000_0000_0000”, and the value range of the generated random value is between “u64’h0000_0000_0000_0000” and “u64’hFFFF_FFFF_FFFF_FFFF”.

[0086] The embodiment of the present application generates at least one random value located in the value range of the random value according to the random value generation condition after determining the value range of the random value.

[0087] The embodiment of the present application provides a possible implementation manner, and at least one random value corresponding to at least one target instruction is determined according to a random value generation condition and a value range of the random value, including:

[0088] If the random value generation condition includes the setting seed condition, a seed set for the at least one target instruction is acquired, and at least one random value corresponding to the at least one target instruction is generated according to the value range of the random value and the seed set for the at least one target instruction.

[0089] If the random value generation condition includes the setting seed condition, the setting seed condition is a condition for setting a seed for a target instruction, if the random value generation condition of a certain target instruction is the setting seed condition, it is indicated that a seed is set for the target instruction, the setting seed will affect the result of randomization, and is used to specify an integer value at which an algorithm used for random value generation starts; if the same seed is used, the generated random value is the same each time; if no seed is set, the system selects the value by time; at this time, the generated random value is different each time due to time difference, and the set seed value is valid only once.

[0090] The embodiment of the present application generates at least one random value corresponding to the target instruction after determining the value range of the random value and the seed set for the target instruction.

[0091] The embodiment of the present application provides a possible implementation manner, and at least one random value corresponding to at least one target instruction is determined according to a random value generation condition and a value range of the random value, including:

[0092] If the random value generation condition includes the setting iteration number condition, an iteration number of a random value set for the at least one target instruction is acquired, and at least one random value corresponding to the at least one target instruction is generated according to the value range of the random value and the iteration number of the random value.

[0093] If the random value generation condition is the setting iteration number condition, if the random value generation condition includes the setting iteration number condition, it is indicated that an iteration number of a random value is set for the target instruction, the iteration number of the random value set for the target instruction needs to be acquired, the iteration number is 1, which indicates that only one group of random values is generated, the iteration number is 2, which indicates that two groups of random values are generated, and so on, and any random value in the two groups of random values is different.

[0094] Specifically, assuming that the random value generation conditions set for a target instruction only have the second generation condition, if the iteration number is 2, a generated first group of random values are "u64'h0000_0000_0100_0000", "u64'h0010_0000_0000_0000", "u64'h0000_00EF_0000_0000" and so on, and each random value in a generated second group of random values is different from the first group of random values.

[0095] The embodiment of the present application provides a possible implementation manner, and the assembly code file of the test case corresponding to the instruction set test point file is generated according to the test point information of at least one target instruction and the assembly code file of the test case corresponding to at least one random value generation instruction set.

[0096] The assembly code of the test case corresponding to each target instruction is generated according to the test point information of each target instruction and at least one random value of each target instruction.

[0097] The assembly code of the test case corresponding to each target instruction is combined according to a preset rule to generate the assembly code file of the test case corresponding to the instruction set test point file.

[0098] The assembly code file of the test case corresponding to the instruction set test point file is combined by the assembly code file of the test case of each target instruction, and the assembly code of the test case corresponding to each target instruction is generated first, and then the assembly code of each target instruction is combined to generate the assembly code of the test case corresponding to the instruction set test point file. Details are shown in the subsequent part.

[0099] The embodiment of the present application provides a possible implementation manner, and the test point information further includes an instruction unique identifier; the value of the source operand includes a typical value, a critical value and a user-defined value;

[0100] The assembly code of the test case corresponding to each target instruction is generated according to the test point information of each target instruction and at least one random value of each target instruction, including:

[0101] At least one of the typical value, the critical value, the user-defined value and the random value is selected as the input value of the source operand of the target instruction;

[0102] The test case assembly template corresponding to each target instruction is called, and the instruction unique identifier, the source operand and the input value of the source operand of each target instruction are filled into the corresponding test case assembly template to generate the assembly code of the test case of each target instruction.

[0103] The value of the source operand includes the critical value, the typical value, the user-defined value and the random value. The critical value includes the maximum value and the minimum value, and the typical value can be the second maximum value and the second minimum value.

[0104] For integer type source operand, typical values can be all 0, all 1, 10 interlaced, 01 interlaced, walking one and walking zero. Walking zero refers to a hexadecimal number having only one bit as 0, and the value of the number can be changed by moving the position of 0 to the left or right. For example, for the hexadecimal number "u64'h1111_1111_1111_1110", the walking one can obtain "u64'h1111_1111_1111_1101, u64'h1111_1111_1111_1011, u64'h1111_1111_1111_0111, u64'h1111_1111_1110_1111, …… u64'h1110_1111_1111_1111, u64'h1101_1111_1111_1111, u64'h1011_1111_1111_1111 and u64'h0111_1111_1111_1111". Similarly, for walking one, the value of the number can be changed by moving the position of "1" to the left or right. The embodiments of the present application will not be described here.

[0105] For floating point type source operand, typical values can also be adjacent values of positive and negative canonical number boundary values, adjacent values of positive and negative non-canonical number boundary values, ±0, ±1, positive and negative infinity, static non-number (qNaN) and signal non-number (sNaN).

[0106] The various values of the embodiments of the present application can be combined with each other as input values of source operand. Taking the target instruction containing two source operands as an example, the input values of the two source operands can be the combination of critical value and critical value, the combination of critical value and typical value, the combination of critical value and user-defined value, the combination of critical value and random value, the combination of typical value and typical value, the combination of typical value and user-defined value, the combination of typical value and random value, the combination of user-defined value and user-defined value, the combination of user-defined value and random value, and the combination of random value and random value. These two-by-two combinations can be used as input values of two operands to cover various test scenarios.

[0107] After determining the input values of the source operands of each target instruction, the embodiments of the present application call the test case assembly template corresponding to each target instruction, and fill the unique identifier of each target instruction, the source operand and the input value of the source operand into the corresponding test case assembly template to generate the assembly code of the test case corresponding to each target instruction.

[0108] The embodiment of the application includes the unique identifier of the target instruction, the source operand, the source operand and the placeholder corresponding to the input value of the source operand in the test case assembly template. By calling the openpyxl module, the unique identifier of the target instruction, the source operand and the input value of the source operand can be filled into the corresponding placeholder, so as to generate the assembly code of the test case corresponding to the target instruction.

[0109] As shown in Figure 4 , an example of a test case assembly template is exemplarily shown, which is a logical and corresponding test case assembly template. The instruction unique identifier and the input value of each source operand need to be filled into the corresponding placeholder. In addition, the test case assembly template also has the corresponding placeholder of other information, such as the macro command Macro and the like.

[0110] It should be emphasized that the above-mentioned test case assembly template is only a specific example. Other information can also be added to the test case assembly template, which can be set according to actual conditions.

[0111] The embodiment of the application provides a possible implementation manner. The test case assembly template includes the unique identifier of the target instruction and the input value of the source operand corresponding to the placeholder. The specific content is as described in the above embodiment, which will not be repeated here.

[0112] As shown in Figure 5 , an example of an instruction set test point file corresponding to the assembly code file of the test case is exemplarily shown. Taking “TEST_RR_OP(ADD,x11,x26,x21,dummy,0xfffffffffffffffff,0x5d7d56aef11622f,x2,8,x3)” as an example, TEST_RR_OP is a macro command, “0xfffffffffffffffff” is the input value corresponding to the original operation rs1, “0xfffffffffffffffff” is the input value corresponding to the source operand rs2. Obviously, “0xfffffffffffffffff” is the critical value, the maximum value that the source operand rs1 can take, and “0x5d7d56aef11622f” is a random value.

[0113] As shown in Figure 6As shown, it exemplarily shows the number of generated test points of each target instruction in the case of the same random value, the horizontal coordinate is the name of the target instruction, and the vertical coordinate is the number of test points corresponding to various target instructions, more than 100 RISCV instructions are involved, and since part of the floating-point instructions have a rounding mode, 309 test points are generated; the test points of most instructions are about 1000, and the test points corresponding to the target instruction with three source operation indexes and each source operand being a floating-point type are the most, such as instruction FMADD.S, which can be as high as 70000, which cannot be achieved by manual work.

[0114] The embodiment of the present application provides a test case assembly code file generation device, as shown in the figure, Figure 7 As shown, the test case assembly code file generation device 70 can include:

[0115] The target instruction acquisition module 710 is configured to determine at least one target instruction meeting a preset specified condition from an instruction set test point file, and read test point information of the at least one target instruction; the instruction set test point file includes at least one instruction and test point information of the at least one instruction;

[0116] The random value generation module 720 is configured to obtain a random value generation condition corresponding to the at least one target instruction, and generate at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction;

[0117] The assembly code generation module 730 is configured to generate an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.

[0118] The embodiment of the present application first determines at least one target instruction meeting a preset specified condition from an instruction set test point file, and reads test point information of the at least one target instruction; then obtains a random value generation condition corresponding to the at least one target instruction, and generates at least one random value corresponding to the at least one target instruction according to the random value generation condition corresponding to the at least one target instruction, and generates an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value. The embodiment of the present application realizes coverage of critical scenarios, improves the coverage rate of critical scenarios, can comprehensively verify the instruction set information, and further discovers potential faults.

[0119] The embodiment of the present application provides a possible implementation manner, the test point information includes at least one source operand and a corresponding value of the source operand;

[0120] The random value generation module includes:

[0121] The source operand value range determination submodule is configured to obtain values of at least one source operand of at least one target instruction, and determine a value range of the source operand according to the values of the source operand;

[0122] The random value value range determination submodule is configured to determine a value range of a random value according to the value range of the source operand;

[0123] The random value generation submodule is configured to generate at least one random value corresponding to at least one target instruction according to a random value generation condition and the value range of the random value.

[0124] The random value generation submodule provided in the embodiment of the present application comprises:

[0125] The random value generation first unit is configured to, if the random value generation condition comprises a seed setting condition, obtain a seed set for the at least one target instruction, and generate at least one random value corresponding to the at least one target instruction according to the value range of the random value and the seed set for the at least one target instruction;

[0126] The random value generation submodule provided in the embodiment of the present application comprises:

[0127] The random value generation second unit is configured to, if the random value generation condition comprises an iteration number setting condition, obtain an iteration number of the random value set for the at least one target instruction, and determine at least one random value corresponding to the at least one target instruction according to the value range of the random value and the iteration number of the random value.

[0128] The assembly code generation module provided in the embodiment of the present application comprises:

[0129] The target instruction test case assembly code generation module is configured to generate assembly code of a test case corresponding to each target instruction according to the test point information of each target instruction and the at least one random value of each target instruction;

[0130] The assembly code generation submodule is configured to combine the test case assembly code corresponding to each target instruction according to a preset rule to generate assembly code of a test case corresponding to an instruction set test point file.

[0131] The test point information further comprises an instruction unique identifier, and the values of the source operand comprise a typical value, a critical value and a user-defined value.

[0132] The assembly code generation submodule further comprises:

[0133] The input value determination unit is configured to select at least one of the typical value, the critical value, the user-defined value and the random value as an input value of the source operand of the target instruction.

[0134] The test case assembly code generation unit is used to call the test case assembly template corresponding to each target instruction, fill the unique identifier of each target instruction and the input value of the source operand into the corresponding test case assembly template, and generate the assembly code of the test case corresponding to each target instruction.

[0135] This application provides a possible implementation method in which the test case assembly template includes a unique identifier for the target instruction and placeholders corresponding to the input values ​​of the source operands.

[0136] The apparatus in this application embodiment can execute the method provided in this application embodiment, and the implementation principle is similar. The actions performed by each module in the apparatus of each embodiment of this application correspond to the steps in the method of each embodiment of this application. For detailed functional descriptions of each module of the apparatus, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0137] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement a method for generating assembly code files for test cases. Compared with the prior art, this application first determines at least one target instruction that meets preset conditions from an instruction set test point file, and reads the test point information of the at least one target instruction; then, it obtains the random value generation conditions corresponding to the at least one target instruction, generates at least one random value corresponding to the at least one target instruction based on the random value generation conditions, and generates the assembly code file of the test cases corresponding to the instruction set test point file based on the test point information of the at least one target instruction and the at least one random value. This application achieves coverage of critical scenarios, improves the coverage rate of critical scenarios, and can comprehensively verify instruction set information, thereby discovering potential anomalies.

[0138] In one alternative embodiment, an electronic device is provided, such as Figure 8 As shown, Figure 8 The illustrated electronic device 8000 includes a processor 8001 and a memory 8003. The processor 8001 and the memory 8003 are connected, for example, via a bus 8002. Optionally, the electronic device 8000 may further include a transceiver 8004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 8004 is not limited to one type, and the structure of the electronic device 8000 does not constitute a limitation on the embodiments of this application.

[0139] The processor 8001 can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in connection with the disclosure. The processor 8001 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0140] The bus 8002 can include a path for transmitting information between the above-mentioned components. The bus 8002 can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 8002 can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, Figure 8 Only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0141] The memory 8003 can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, an optical disk storage (including a compact disk, a laser disk, an optical disk, a digital versatile disk, a Blu-ray disk, etc.), a magnetic disk storage medium, other magnetic storage device, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation.

[0142] The memory 8003 is configured to store a computer program for implementing the embodiments of the present application, and the processor 8001 is configured to control the execution of the computer program stored in the memory 8003. The processor 8001 is configured to execute the computer program stored in the memory 8003 to implement the steps of the foregoing method embodiments.

[0143] The electronic device can include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Personal Computer), a PMP (Portable Multimedia Player), a car terminal (for example, a car navigation terminal), and the like, and a stationary terminal such as a digital TV, a desktop computer, and the like. Figure 5 The electronic device shown is merely an example and should not limit the functions and use range of the embodiments of the present disclosure.

[0144] The computer readable storage medium provided by the embodiments of the present application stores a computer program, and the computer program is executed by a processor to implement the steps and corresponding contents of the foregoing method embodiments. Compared with the prior art, the embodiments of the present application can achieve the following: first, at least one target instruction meeting a preset specified condition is determined from an instruction set test point file, and test point information of the at least one target instruction is read; then, a random value generation condition corresponding to the at least one target instruction is obtained, at least one random value corresponding to the at least one target instruction is generated according to the random value generation condition corresponding to the at least one target instruction, and an assembly code file of a test case corresponding to the instruction set test point file is generated according to the test point information of the at least one target instruction and the at least one random value. The embodiments of the present application achieve coverage of critical scenarios, improve the coverage rate of critical scenarios, can comprehensively verify the instruction set information, and further find potential abnormalities.

[0145] It should be noted that the computer readable medium of the present disclosure described above can be a computer readable signal medium or a computer readable medium or any combination of the above two. The computer readable storage medium may, for example, be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of computer readable storage media can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. In the present disclosure, the computer readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer readable program code. Such a propagated data signal can take many forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus. The program code contained on the computer readable medium can be transmitted by any suitable medium, including but not limited to a wire, a cable, an RF (radio frequency) or the like, or any suitable combination of the above.

[0146] The application embodiment also provides a computer program product comprising a computer program, which, when executed by a processor, can implement the steps and corresponding contents of the foregoing method embodiments. Compared with the prior art, the application embodiment can achieve the following: first, at least one target instruction meeting a preset specified condition is determined from an instruction set test point file, and test point information of the at least one target instruction is read; then, a random value generation condition corresponding to the at least one target instruction is obtained, and at least one random value corresponding to the at least one target instruction is generated according to the random value generation condition corresponding to the at least one target instruction, and an assembly code file of a test case corresponding to the instruction set test point file is generated according to the test point information of the at least one target instruction and the at least one random value. The application embodiment achieves coverage of critical scenarios, improves the coverage rate of critical scenarios, can comprehensively verify instruction set information, and further discovers potential abnormalities.

[0147] It should be understood that although the various operation steps in the flowcharts of the embodiments of the present application are indicated by arrows, the implementation order of the steps is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of the embodiments of the present application, the implementation steps in each flowchart can be executed in other orders as required. In addition, part or all of the steps in each flowchart can include multiple sub-steps or multiple stages based on the actual implementation scenario. Part or all of the sub-steps or stages can be executed at the same time, and each of the sub-steps or stages can also be executed at different times. In the scenario where the execution times are different, the execution order of the sub-steps or stages can be flexibly configured as required, and the embodiments of the present application do not limit this.

[0148] The above is only an optional implementation of some implementation scenarios of the present application. It should be pointed out that, for those skilled in the art, other similar implementation means based on the technical idea of the present application without departing from the technical concept of the present application also belong to the protection scope of the embodiments of the present application.

Claims

1. A method of generating an assembly code file of a test case, characterized by, The method comprises the following steps: determining at least one target instruction meeting preset conditions from an instruction set test point file, and reading test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction; wherein the instruction set test point file is an excel file; obtaining a random value generation condition corresponding to the at least one target instruction, obtaining a value of at least one source operand of the at least one target instruction, and determining a value range of the source operand according to the value of the source operand; the test point information comprises at least one source operand and a corresponding value of the source operand; the test point information further comprises an instruction unique identifier; the value of the source operand comprises a typical value, a critical value and a user-defined value; determining a value range of the random value according to the value range of the source operand; if the random value generation condition comprises a set iteration number condition, obtaining an iteration number of the random value set for the at least one target instruction, and determining at least one random value corresponding to the at least one target instruction according to the value range of the random value and the iteration number of the random value; wherein each random value between each group of random values generated in different iteration rounds is different; generating an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.

2. The method of claim 1, wherein, The method comprises the following steps: if the random value generation condition comprises a set seed condition, obtaining a seed set for the at least one target instruction, and generating at least one random value corresponding to the at least one target instruction according to the value range of the random value and the seed.

3. The method of claim 1, wherein, The method comprises the following steps: generating an assembly code of a test case corresponding to each target instruction according to the test point information of each target instruction and at least one random value of each target instruction; combining the test case assembly codes corresponding to each target instruction according to a preset rule to generate an assembly code file of a test case corresponding to the instruction set test point file.

4. The method of claim 3, wherein, The method comprises the following steps: selecting at least one of the typical value, the critical value, the user-defined value and the random value as an input value of the source operand of the target instruction; calling a test case assembly template corresponding to each target instruction, filling the instruction unique identifier of each target instruction and the input value of the source operand into the corresponding test case assembly template, and generating an assembly code of a test case corresponding to each target instruction.

5. The method of claim 4, wherein, The test case assembly template comprises a placeholder corresponding to the unique identifier of the target instruction and the input value of the source operand.

6. An apparatus for generating assembly code files for test cases, characterized in that, The method comprises the following steps: The target instruction obtaining module is configured to determine at least one target instruction meeting a preset limited condition from an instruction set test point file, and read test point information of the at least one target instruction; the instruction set test point file comprises at least one instruction and test point information of the at least one instruction; and the instruction set test point file is an excel file. The random value generating module is configured to obtain a random value generating condition corresponding to the at least one target instruction, obtain a value of at least one source operand of the at least one target instruction, and determine a value range of the source operand according to the value of the source operand; the test point information comprises at least one source operand and a corresponding value of the source operand; the test point information further comprises an instruction unique identifier; the value of the source operand comprises a typical value, a critical value and a user-defined value; The value range of the random value is determined according to the value range of the source operand; If the random value generating condition comprises a set iteration number condition, an iteration number of a random value set for the at least one target instruction is obtained, and at least one random value corresponding to the at least one target instruction is determined according to the value range of the random value and the iteration number of the random value; wherein each random value in each group of random values generated in different iteration rounds is different; The assembly code generating module is configured to generate an assembly code file of a test case corresponding to the instruction set test point file according to the test point information of the at least one target instruction and the at least one random value.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory, wherein the computer program comprises instructions that, when executed by the processor, cause the electronic device to perform the method of any one of claims 1-6. The processor executes the computer program to implement the steps of the method of any one of claims 1-5.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of any one of claims 1-5.

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