A method, device, storage medium and equipment for auxiliary graphics construction

Abstract

The present invention belongs to the field of microelectronics technology, and in particular, relates to an auxiliary pattern construction method and a corresponding device, storage medium and equipment. By introducing a seed pattern, the method of the present invention can construct as many auxiliary patterns as possible to improve the OPC characteristics. In addition, priorities can be set for different constraints and layouts to maximize the process window; in particular, with the help of a pixel-based OPC process, the layout of the feature pattern can be further improved.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to an auxiliary graphic construction method, device, storage medium and equipment. Background Art

[0002] Since the Sub Resolution Assist Features (SRAF) of the hole or through-hole HL (Hole Layer) is different from other specific layers (CL) and its SRAF rules are relatively complex, SRAF missing often occurs when writing process flow script recipes, which weakens the function of SRAF and increases the difficulty of OPC (Optical Proximity Correction).

[0003] The SRAF process is one of the cores of HL layer process optimization. Through the improvement of SRAF, the efficiency of the process can be effectively improved, the risk of re-issuing the mask can be reduced, and the positive effect of saving resources, improving production capacity and efficiency can be achieved. Summary of the invention

[0004] The inventors found that if the SRAF in the prior art is constructed and inserted based on the target T (Target) edge of the HL layer, its length will be adjusted based on the T edge, and the distance between the SRAF and the T edge is determined by the target space TS (Target Space), which leads to the SRAF missing phenomenon.

[0005] The present invention discloses a SRAF method based on DL (Draw Layer), including data collection, seed construction and graphics generation steps; wherein:

[0006] The data acquisition step obtains the first layout information and the second layout information to analyze the feasibility of the construction process; wherein the first layout information includes hole and / or through-hole layer information, that is, characteristic graphics of the layout holes and / or through-hole layers; the second layout information contains constraint information of the auxiliary graphics to be inserted.

[0007] The seed construction step obtains the first seed pattern as the base (bottom) of the SRAF construction; wherein the first seed pattern is located in the second layout, and its length and width are smaller than the preset values; on the one hand, the interference of the pattern pieces is avoided; on the other hand, the position of the base (bottom) can be more flexibly selected.

[0008] The pattern generation step extends the first sub-pattern and constructs a first auxiliary pattern, and implements a corresponding optical function by inserting the first layout information.

[0009] Furthermore, for different sizes and layouts of characteristic patterns, the first sub-pattern may be a square element or pattern; the element is a characteristic pattern of the integrated circuit, and the constraint information includes optical rules, especially scattering and diffraction rules of light waves.

[0010] The iterative optimization step corrects the size information of the first seed pattern according to the optical proximity correction rule to obtain the second seed pattern; verifies the validity of the second seed through the optical correction model, filters the part that may have a projection on the workpiece, and iteratively updates the second seed pattern.

[0011] Furthermore, by acquiring the environmental parameters of the first layout information and the second layout information, the seed pattern can be corrected in a wider range; wherein the environmental parameters include the first position information and the first size information of the hole and / or through-hole layer; at this time, the first layout information can also be subjected to model-based or rule-based SRAF processing; the advantages of the method of the present invention are complementary, and the present invention has the characteristic of fast convergence, while the model-based method will have higher correction accuracy.

[0012] If the first auxiliary graphic conflicts with the environmental parameters or conflicts with the first position information and / or the first size information, the insertion process of the first auxiliary graphic is canceled. Here, a protection mechanism is provided to prevent invalid corrections from entering unnecessary loops.

[0013] If the insertion process of the first auxiliary pattern is cancelled, the seed pattern is corrected for the Nth time, and the above steps are performed again until a valid correction is generated; wherein N is an integer greater than 2.

[0014] If N is greater than a preset value, the first position information and the first size information are adjusted or the construction of the first auxiliary pattern is terminated, and the steps related to the present invention are executed again after iterative design of the first layout.

[0015] Corresponding to the above method, the present invention further discloses an auxiliary graphics processing device, including a data acquisition unit, a seed construction unit and a graphics generation unit.

[0016] Among them, the data acquisition unit obtains first layout information and second layout information; the first layout information includes hole and / or through-hole layer information, and the first layout information includes characteristic graphics of the hole and / or through-hole layer; obtains second layout information; wherein the second layout information contains constraint information of the layer to be inserted.

[0017] Correspondingly, the seed construction unit is used to obtain a first seed pattern; wherein the first seed pattern is located in the second layout, and its length and width are smaller than preset values.

[0018] The first sub-graphic is extended by a graphic generation unit, a first auxiliary graphic is constructed, and first layout information is inserted, thereby realizing the construction of the auxiliary graphic.

[0019] Furthermore, the device of the present invention may also include an iterative optimization unit; wherein the iterative optimization unit corrects the size information of the first seed pattern according to the optical proximity correction rule to obtain the second seed pattern; verifies the validity of the second seed through the optical correction model, filters out parts that may have unexpected and / or unknown projections on the workpiece, iteratively updates the second seed pattern and completes the corresponding method of the present invention, and constructs a corresponding auxiliary pattern to supplement the influence of effects such as diffraction and scattering of light on the layout transfer process.

[0020] Furthermore, the device of the present invention may also include a rule optimization and exception processing unit; wherein the rule optimization and exception processing unit obtains environmental parameters of the first layout information and the second layout information; the environmental parameters include first position information and first size information of the hole and / or through-hole layer; if necessary, the first layout information is subjected to model- or rule-based SRAF processing.

[0021] If the first auxiliary graphic conflicts with the environmental parameters or conflicts with the first position information and / or the first size information, the insertion process of the first auxiliary graphic is canceled; based on the above design, the reliability and applicability of the device of the present invention are guaranteed.

[0022] Furthermore, if the insertion process of the first auxiliary pattern is cancelled, the seed pattern is corrected for the Nth time, and the necessary construction steps are performed again.

[0023] If N is greater than a preset value, the first position information and the first size information are adjusted or the construction of the first auxiliary pattern is terminated, and the first layout is iteratively designed and then the corresponding steps are executed again to complete the construction process of the auxiliary pattern.

[0024] By implanting the method of the present invention into a computer storage medium or using it for the generation, manufacture and function expansion of intelligent devices, the corresponding method and device are naturally applied to actual products, and the implementation process will not be described in detail here.

[0025] Due to the introduction of the method of the present invention, the occurrence of SRAF pattern loss is avoided, and the SRAF is guaranteed to give full play to the requirements of the exposure system's wider adaptability to focal length and light intensity, thereby increasing the process window PW (ProcessWindow) of the process, which is also beneficial to improving the overall process yield and quality.

[0026] It should be noted that the terms "first", "second" and similar terms used in this article are only for describing the various components in the technical solution, and do not constitute a limitation of the technical solution, nor can they be understood as an indication or suggestion of the importance of the corresponding elements; elements with "first", "second" and similar terms indicate that the corresponding technical solution contains at least one of the element. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solution of the present invention and facilitate further understanding of the technical effects, technical features and purposes of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings. The accompanying drawings constitute an essential part of the specification and are used together with the embodiments of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation to the present invention.

[0028] The same reference numerals in the accompanying drawings represent the same components, specifically:

[0029] Figure 1 A schematic diagram of a process of an embodiment of the method of the present invention;

[0030] Figure 2 A schematic diagram of the structure and information flow of an embodiment of the device of the present invention;

[0031] Figure 3 An example of SRAF loss in the prior art is given;

[0032] Figure 4 The SRAF constructed in the first embodiment of the method of the present invention;

[0033] Figure 5 The SRAF is constructed by the method of the present invention based on the specified seed graph (222, 333, 444);

[0034] Figure 6 The plate processed by the method of the present invention Figure 2 ;

[0035] Figure 7 An example of a layout processed by the method of the present invention;

[0036] Figure 8 Based on Figure 7 The SRAF constructed after pixel OPC.

[0037] in:

[0038] 1-Layout information to be acquired, 2-SARF information;

[0039] 10-data collection step, 11 data collection unit;

[0040] 20-seed construction step, 22-seed construction unit;

[0041] 30-graphics generation step, 33-graphics generation unit;

[0042] 44-iterative optimization unit;

[0043] 55-Rule optimization and exception handling unit

[0044] 101, 102, 103, 104, 105—SRAF graphics that may be set in the first embodiment;

[0045] 111, 222, 333, 444 - first seed pattern;

[0046] 201, 202, 203 SRAF graphics that may be set in the second embodiment;

[0047] 211, 212, 213, 214, 215, 216, 217, 218, 219, 21A, 21B, square layout of characteristic patterns in Example 2;

[0048] 901-the first layout information in Example 1, 902-the first layout information in Example 2. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Of course, the specific embodiments described below are only for explaining the technical solutions of the present invention, rather than for limiting the present invention. In addition, the parts described in the embodiments or the accompanying drawings are only examples of the relevant parts of the present invention, rather than the whole of the present invention.

[0050] like Figure 1 and Figures 3 to 8 As shown, a flow chart of an embodiment of the method of the present invention is shown, in which the first layout information 901, 902 is obtained through the data acquisition step 10; wherein the first layout information 901, 902 includes hole and / or through-hole layer information, that is, characteristic graphics of the hole and / or through-hole layer; and the second layout information is further obtained to introduce constraint information for inserting auxiliary graphics.

[0051] like Figure 4 , 5 As shown, in the seed construction step 20, the first seed graphics 111, 222, 333, 444 located in the second layout are obtained and the length and width of the first seed graphics 111, 222, 333, 444 are limited to meet the preset values.

[0052] Furthermore, in the graphic generation step 30 , the first seed graphics 111 , 222 , 333 , 444 are extended, the first auxiliary graphics are constructed and the first layout information 901 , 902 is inserted.

[0053] like Figure 4 , 5 The first sub-patterns 111, 222, 333, 444 are square elements or patterns; the elements are characteristic patterns of the integrated circuit; in addition, the constraint information includes optical rules, especially the scattering and diffraction rules of light waves.

[0054] In the iterative optimization step, the size information of the first seed patterns 111, 222, 333, 444 is corrected according to the optical proximity correction rule to obtain the second seed pattern; the validity of the second seed is checked by the optical correction model, the parts that may have projections on the workpiece are filtered, and the second seed pattern is iteratively updated.

[0055] Furthermore, by acquiring the environmental parameters of the first layout information 901, 902 and the second layout information, namely the first position information and the first size information of the hole and / or through-hole layer; the first layout information 901, 902 is subjected to model- or rule-based SRAF processing to improve parameter details.

[0056] If the first auxiliary graphic conflicts with the environmental parameters or conflicts with the first position information and / or the first size information, the insertion process of the first auxiliary graphic is canceled.

[0057] Similarly, if the insertion process of the first auxiliary pattern is cancelled, the seed pattern is corrected for the Nth time, and the relevant construction steps are performed again; wherein N is an integer greater than 2;

[0058] If N is greater than a preset value, the first position information and the first size information are adjusted or the construction of the first auxiliary pattern is terminated, and the corresponding construction method is executed again after iterative design of the first layout.

[0059] like Figure 2 , a schematic diagram of the structure and information flow of an embodiment of the device of the present invention, including a data acquisition unit 11, a seed construction unit 22 and a graphic generation unit 33.

[0060] Among them, the data acquisition unit 11 obtains the first layout information 901, 902 and the second layout information; the first layout information 901, 902 includes hole and / or through-hole layer information, that is, the characteristic graphics of the hole and / or through-hole layer; obtains the second layout information; wherein the constraint information of the insertion layer.

[0061] In the seed construction unit 22, the first seed graphics 111, 222, 333, 444 are obtained; wherein the first seed graphics 111, 222, 333, 444 are located in the second layout, and the length and width of the first seed graphics 111, 222, 333, 444 are required to be smaller than preset values.

[0062] Furthermore, the graphic generation unit 33 extends the first seed graphics 111 , 222 , 333 , 444 , constructs the first auxiliary graphics and inserts the first layout information 901 , 902 .

[0063] Furthermore, if Figure 2The device also includes an iterative optimization unit 44; wherein the iterative optimization unit 44 corrects the size information of the first seed pattern 111, 222, 333, 444 according to the optical proximity correction rule to obtain the second seed pattern; verifies the validity of the second seed through the optical correction model, filters the parts that may have unexpected and / or unknown projections on the workpiece, iteratively updates the second seed pattern and completes the construction of the auxiliary pattern.

[0064] In addition, a rule optimization and exception handling unit 55 may be provided, wherein the rule optimization and exception handling unit 55 obtains the environmental parameters of the first layout information 901, 902 and the second layout information, i.e., the first position information and the first size information of the hole and / or through-hole layer; and performs model-based or rule-based SRAF processing on the first layout information.

[0065] If the first auxiliary graphic conflicts with the environmental parameters or conflicts with the first position information and / or the first size information, the insertion process of the first auxiliary graphic is canceled.

[0066] Furthermore, if the insertion process of the first auxiliary pattern is cancelled, the seed pattern is corrected for the Nth time, and other related steps are performed again; wherein N is an integer greater than 2.

[0067] If N is greater than a preset value, the first position information and the first size information are adjusted or the construction of the first auxiliary pattern is terminated, and the first layout is iteratively designed and then the relevant construction steps are executed again.

[0068] For example Figure 5 In the layout form shown, the SRAF seed length obtained based on the borders of the seed graphics 222, 333, and 444 is smaller than the adjacent borders, so it can be effectively retained in the layout processing and can be further extended accordingly.

[0069] like Figure 8 As shown in the figure, after the pixel-based OPC constraint rules are added, Figure 7 The SRAF of the process is optimized; the process window PW is increased from 60nm to 100nm; priorities can be set for different constraints and layouts to maximize PW; or the layout of feature graphics can be improved with the help of a pixel-based OPC process.

[0070] It should be noted that the above embodiments are only for more clearly illustrating the technical solutions of the present invention. Those skilled in the art will understand that the implementation methods of the present invention are not limited to the above contents, and obvious changes, replacements or substitutions based on the above contents do not exceed the scope of the technical solutions of the present invention; other implementation methods will also fall within the scope of the present invention without departing from the concept of the present invention.

Claims

1. A method for constructing an auxiliary graph, characterized in that: include: Data collection step (10); obtaining first layout information (901, 902); wherein the first layout information (901, 902) includes hole and / or through-hole layer information, and the first layout information (901, 902) includes characteristic patterns of the hole and / or through-hole layer; obtaining second layout information; wherein the second layout information includes constraint information of the auxiliary pattern to be inserted; Seed construction step (20); obtaining a first seed graphic (111, 222, 333, 444); wherein the first seed graphic (111, 222, 333, 444) is located in the second layout, and the length and width of the first seed graphic (111, 222, 333, 444) are smaller than preset values; Graphics generation step (30): extending the first seed graphics (111, 222, 333, 444), constructing a first auxiliary graphics and inserting the first layout information (901, 902); Iterative optimization unit (44); correcting the size information of the first seed pattern (111, 222, 333, 444) according to the optical proximity correction rule to obtain a second seed pattern; verifying the validity of the second seed pattern through the optical correction model, filtering out parts that may have unexpected and / or unknown projections on the workpiece, iteratively updating the second seed pattern and completing the construction of the auxiliary pattern; The first sub-pattern (111, 222, 333, 444) is a square element or pattern; the element is a characteristic pattern of an integrated circuit; the constraint information includes optical rules, and the optical rules include scattering and diffraction rules of light waves.

2. The method of claim 1, wherein: Acquiring environmental parameters of the first layout information (901, 902) and the second layout information, wherein the environmental parameters include first position information and first size information of the hole and / or through-hole layer; performing model- or rule-based SRAF processing on the first layout information (901, 902); If the first auxiliary graphic conflicts with the environmental parameter, the inserting process of the first auxiliary graphic is canceled.

3. The method of claim 2, wherein: If the insertion process of the first auxiliary pattern is cancelled, the first sub-pattern is corrected for the Nth time, and the steps as claimed in claim 2 are performed again; wherein N is an integer greater than 2; If N is greater than a preset value, the first position information and the first size information are adjusted or the construction of the first auxiliary pattern is terminated, and the method as claimed in claim 2 is executed again after iterative design of the first layout.

4. A computer storage medium comprising: A storage medium for storing a computer program; When the computer program is executed by a microprocessor, the method according to any one of claims 1 to 3 is implemented.

5. A layout production device, comprising: The storage medium as claimed in claim 4.

Images