Floating gate type split-gate flash memory device and manufacturing method thereof

Abstract

The present invention discloses a floating gate split-gate flash memory device and a manufacturing method thereof. The floating gate split-gate flash memory device includes a P-type well, a select gate oxide layer, a select gate polysilicon layer, a second silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer, which are sequentially located above the P-type well. Two sidewall control gate polysilicon layers and an isolation dielectric layer are both located within a gap X in the third silicon oxide layer. The floating gate silicon oxide dielectric layer is located outside the third silicon oxide layer and outside the isolation dielectric layer. Two sidewall floating gate polysilicon layers are located outside the floating gate silicon oxide dielectric layer and correspond to the two sidewall control gate polysilicon layers, respectively. A second LDD region and a source / drain region are both located on top of both sides of the P-type well. The present invention can effectively reduce the WL-FG coupling coefficient while increasing the CG-FG coupling coefficient, thereby enhancing the CG control capability, reducing device leakage, and improving the performance of the flash memory device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a floating gate split-gate flash memory device and a manufacturing method thereof. Background Art

[0002] Split-gate floating-gate flash memory technology is widely used in various embedded electronic products such as financial IC cards and automotive electronics. This flash memory can improve storage integration density, which helps save chip area and reduce manufacturing costs.

[0003] like Figures 1 to 7 The existing method for manufacturing a 2-bit / cell (two bits per memory cell) split-gate floating gate flash memory device includes the following steps:

[0004] In step 1, a P-type well 101 is formed by implantation on a P-type substrate, and a floating gate oxide layer 102, a floating gate polysilicon (Poly) layer 103, and a first silicon nitride layer 502 are grown by thermal oxidation on the P-type well 101; an STI (Shallow-Trench-Isolation) process is performed to form a shallow trench 501; and active areas of the flash memory and peripheral logic areas are defined at the same time.

[0005] Step 2: Deposit an inter-polysilicon ONO (Oxide-Nitride-Oxide, oxide / nitride / oxide) layer 104, a control gate polysilicon layer 105, and a thick silicon nitride layer 504 in sequence; define the flash memory cell area by photolithography, and etch away the thick silicon nitride layer in the opening area.

[0006] Step three: depositing a first silicon oxide layer and forming a first spacer dielectric layer 112 by anisotropic etching. The bottom width of the spacer defines the length of the control gate.

[0007] Step 4: Using the first spacer dielectric layer as a hard mask, anisotropically etch the control gate polysilicon to form a self-aligned control gate, and etch the ONO layer.

[0008] Step five: deposit an insulating dielectric layer, and anisotropically etch to form a second spacer dielectric layer 106 . Use the second spacer and the first spacer together as a hard mask to self-align and etch to form a floating gate.

[0009] Step six: depositing a select gate dielectric layer 107 and a select gate polysilicon layer 108 in sequence, and forming a self-aligned select gate by CMP (Chemical Mechanical Polish).

[0010] In step seven, thermal oxidation is performed to form silicon oxide above the select gate polysilicon layer 108, and the first sidewall 112 and the select gate dielectric layer 107 are used as a hard mask to remove the remaining thick silicon nitride layer 504, the control gate polysilicon layer 105, the inter-polysilicon ONO layer 104, and the floating gate polysilicon layer 103 on both sides. LDD (Lightly Doped Drain) implantation is performed in sequence to form a first LDD region 110, deposition and etching are performed to form a third sidewall dielectric layer 109, source and drain implantation is performed to form source and drain regions (i.e., source and drain regions) 111, and a metal silicide process is performed to form a low-resistivity metal silicide 113.

[0011] Further scaling of floating-gate split-gate flash memory devices revealed that the coupling coefficient from CG to FG decreased significantly due to the reduction in the overlap area between the CG (Control-Gate) and the FG (Floating Gate), while the coupling coefficient from WL (Word-Line) to FG increased rapidly from 13.7% to 24.6%. This rapid increase in the WL coupling coefficient deteriorated the device's CG turn-off capability (CG control capability) and resulted in severe leakage (the relationship between the BL (Bit Line) current and CG voltage curve shows a subthreshold swing of 800mV / decade, as shown in Figure 1). Figure 8 Therefore, how to increase the coupling coefficient of CG (i.e., increase the overlapping area of ​​CG and FG) and reduce the coupling coefficient of WL is very important for further miniaturization of floating gate split gate flash memory. Figure 8 The horizontal axis represents the control gate voltage, Figure 8 The vertical axis represents the bit line current. Summary of the Invention

[0012] In view of the above situation, in order to overcome the defects of the prior art, the present invention provides a floating gate split-gate flash memory device and a manufacturing method thereof.

[0013] The present invention solves the above technical problems through the following technical solutions: a floating gate split-gate flash memory device, characterized in that it includes a P-type well, a selection gate oxide layer, a selection gate polysilicon layer, a second silicon oxide layer, a second silicon nitride layer, a third silicon oxide layer, a sidewall type control gate polysilicon layer, an isolation dielectric layer, a floating gate silicon oxide dielectric layer, a sidewall type floating gate polysilicon layer, a second LDD region, a source and drain region, a fourth sidewall dielectric layer and a fifth sidewall dielectric layer, a selection gate oxide layer, a selection gate polysilicon layer, a second silicon oxide layer, a second silicon nitride layer, The third silicon oxide layer is sequentially located above the P-type well; the two sidewall-type control gate polysilicon layers and the isolation dielectric layer are all located within a gap X in the third silicon oxide layer; the floating gate silicon oxide dielectric layer is located outside the third silicon oxide layer and outside the isolation dielectric layer; the two sidewall-type floating gate polysilicon layers are located outside the floating gate silicon oxide dielectric layer and correspond to the two sidewall-type control gate polysilicon layers, respectively; the second LDD region and the source and drain regions are both located on top of both sides of the P-type well; and the fourth sidewall dielectric layer and the fifth sidewall dielectric layer are sequentially located outside the sidewall-type floating gate polysilicon layer.

[0014] The present invention also provides a method for manufacturing a floating gate split-gate flash memory device, characterized in that it comprises the following steps:

[0015] Step 11: implanting a P-type well on the P-type substrate, sequentially forming a select gate oxide layer, a select gate polysilicon layer, a second silicon oxide layer in the inter-polysilicon ONO layer, and a second silicon nitride layer on the P-type well, wherein the inter-polysilicon ONO layer includes a second silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer; then depositing an etch stop layer and a first silicon nitride layer; photolithographically defining an area for the select transistor gate, and etching the first silicon nitride layer and the etch stop layer to form an opening;

[0016] Step 12: depositing a third silicon oxide layer and a control gate polysilicon layer in sequence, and performing anisotropic etching to form a sidewall type control gate polysilicon layer; the sidewall type control gate polysilicon layer is located in the opening;

[0017] Step 13: depositing an isolation dielectric layer between the two sidewall-type control gate polysilicon layers, and performing chemical mechanical polishing using the first silicon nitride layer as a CMP stop layer;

[0018] Step 14: Using the third silicon oxide layer and the isolation dielectric layer as etching masks, wet-etch the first silicon nitride layer; using the third silicon oxide layer and the isolation dielectric layer as masks, sequentially etching the etch stop layer, the second silicon nitride layer, the second silicon oxide layer, and the select gate polysilicon layer, thermally oxidizing the side of the select gate polysilicon layer to form a thermal oxide layer, and then etching the select gate oxide layer;

[0019] Step 15: depositing a floating gate silicon oxide dielectric layer, then depositing a floating gate polysilicon layer, then etching the floating gate polysilicon layer to form a sidewall floating gate polysilicon layer, selectively etching the floating gate in the width direction of the device to form isolated floating gate polysilicon blocks, oxidizing the floating gate sidewalls to form a fourth silicon oxide layer, and performing LDD implantation to form a second LDD region;

[0020] Step 16: depositing and etching to form a fourth sidewall dielectric layer and a fifth sidewall dielectric layer, and performing source and drain heavy doping implantation to form source and drain regions.

[0021] Preferably, the step eleven is to first define the region of the selection transistor gate by photolithography, and then etch away the first silicon nitride layer and the etch stop layer in the opening region.

[0022] Preferably, the third silicon oxide layer in step twelve is located on the first silicon nitride layer and the second silicon nitride layer, the sidewall-type control gate polysilicon layer is located on the third silicon oxide layer and is located in a gap in the third silicon oxide layer, and the two sidewall-type floating gate polysilicon layers are located outside the floating gate silicon oxide dielectric layer and correspond to the two sidewall-type control gate polysilicon layers respectively.

[0023] Preferably, the etch stop layer is located between the second silicon nitride layer and the first silicon nitride layer.

[0024] Preferably, the second LDD region and the source and drain regions are both located on top of both sides of the P-type well.

[0025] Preferably, the fourth spacer dielectric layer and the fifth spacer dielectric layer are sequentially located outside the spacer-type floating gate polysilicon layer.

[0026] Preferably, the etch stop layer is made of silicon oxide.

[0027] The positive progress of the present invention is that the present invention changes the original CG and FG from longitudinal coupling to lateral coupling, that is, the sidewall type control gate polysilicon layer and the sidewall type floating gate polysilicon layer have an overlapping area in the horizontal (i.e., lateral) direction. By increasing the height of the sidewall type control gate polysilicon layer, the overlapping area of ​​CG and FG is increased, thereby improving the coupling coefficient from CG to FG of the device. Since it is through lateral coupling (the overlapping area is only related to the height of CG), reducing the size of the device will not reduce the CG-FG coupling coefficient, which is beneficial to the device. Miniaturization; the overlapping area of ​​WL-FG depends on the thickness of WL-Poly. The thickness of WL-Poly is less than 500A, and the height of CG-Poly is >1000A, which can effectively reduce the coupling coefficient of WL-FG and increase the coupling coefficient of CG-FG, thereby enhancing the CG control capability, reducing device leakage, and improving the performance of flash memory devices; the sidewall-type control gate polysilicon layer and the sidewall-type floating gate polysilicon layer are both sidewall-type polysilicon, which can realize self-aligned etching of control gate and floating gate, which is conducive to reducing the size of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 7 A diagram showing the process steps of a split-gate floating-gate flash memory device in the prior art.

[0029] Figure 8 FIG. 1 is a schematic diagram of a curve showing the relationship between the current on the bit line and the voltage of CG in the prior art.

[0030] Figures 9 to 14 This is a process step diagram of the floating gate split-gate flash memory device of the present invention.

[0031] Figure 15 Schematic diagram of the relationship curve between the current on the bit line and the voltage of CG according to the present invention. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0033] The floating gate split-gate flash memory device of the present invention comprises a P-type well 101, a selection gate oxide layer 1021, a selection gate polysilicon layer 1031, a second silicon oxide layer 1041, a second silicon nitride layer 1042, a third silicon oxide layer 1043, a sidewall type control gate polysilicon layer 1051, an isolation dielectric layer 1061, a floating gate silicon oxide dielectric layer 1071, a sidewall type floating gate polysilicon layer 1081, a second LDD region 1091, a source / drain region 111, a fourth sidewall dielectric layer 1101, and a fifth sidewall dielectric layer 1102. The selection gate oxide layer 1021, the selection gate polysilicon layer 1031, the second silicon oxide layer 1041, the second silicon nitride layer 1042, and the third silicon oxide layer 1043 are arranged in the order On top of the P-type well 101, two sidewall-type control gate polysilicon layers 1051 and an isolation dielectric layer 1061 are both located within a gap X in the third silicon oxide layer 1043. A floating gate silicon oxide dielectric layer 1071 is located outside the third silicon oxide layer 1043 and outside the isolation dielectric layer 1061. Two sidewall-type floating gate polysilicon layers 1081 are located outside the floating gate silicon oxide dielectric layer 1071 and correspond to the two sidewall-type control gate polysilicon layers 1051, respectively. A second LDD region 1091 and a source / drain region 111 are both located on top of both sides of the P-type well 101. A fourth sidewall dielectric layer 1101 and a fifth sidewall dielectric layer 1102 are sequentially located outside the sidewall-type floating gate polysilicon layer 1081.

[0034] like Figures 9 to 14 As shown, the manufacturing method of the floating gate split-gate flash memory device of the present invention includes the following steps:

[0035] Step 11: A P-type well 101 is formed by implantation on the P-type substrate. A select gate oxide layer 1021, a select gate polysilicon layer 1031, a second silicon oxide layer 1041 in the inter-polysilicon ONO layer, and a second silicon nitride layer 1042 are sequentially formed on the P-type well 101. The inter-polysilicon ONO layer includes the second silicon oxide layer 1041, the second silicon nitride layer 1042, and the third silicon oxide layer 1043. An etch stop layer 5011 and a first silicon nitride layer 502 are then deposited. The region of the select transistor gate is defined by photolithography, and the first silicon nitride layer 502 and the etch stop layer 5011 are etched to form an opening L.

[0036] Step 12: depositing a third silicon oxide layer 1043 and a control gate polysilicon layer in sequence, and performing anisotropic etching to form a sidewall type control gate polysilicon layer 1051; the sidewall type control gate polysilicon layer 1051 is located in the opening L;

[0037] In step 13, an isolation dielectric layer 1061 is deposited between the two sidewall-type control gate polysilicon layers 1051, and CMP (chemical mechanical polishing) is performed using the first silicon nitride layer 502 as a CMP stop layer; the isolation dielectric layer 1061 is used to isolate the two sidewall-type control gate polysilicon layers 1051 to prevent them from being connected together.

[0038] Step 14: Using the third silicon oxide layer 1043 and the isolation dielectric layer 1061 as etching masks, the first silicon nitride layer 502 is removed by wet etching. Using the third silicon oxide layer 1043 and the isolation dielectric layer 1061 as masks, the etch stop layer 5011, the second silicon nitride layer 1042, the second silicon oxide layer 1041, and the select gate polysilicon layer 1031 are etched in sequence. A thermal oxide layer 503 is formed on the side of the select gate polysilicon layer 1031 by thermal oxidation, and then the select gate oxide layer 1021 is etched.

[0039] Step 15: Deposit a floating gate silicon oxide dielectric layer 1071, then deposit a floating gate polysilicon layer, and then etch the floating gate polysilicon layer to form a sidewall floating gate polysilicon layer 1081. Photolithography is selectively performed to form isolated floating gate polysilicon blocks along the width direction of the device. Oxidation is then performed to form a fourth silicon oxide layer 5041 on the floating gate sidewalls, and LDD implantation is performed to form a second LDD region 1091.

[0040] Step 16: depositing and etching to form a fourth spacer dielectric layer 1101 and a fifth spacer dielectric layer 1102 , and performing source and drain heavy doping implantation to form source and drain regions 111 .

[0041] Step 11 specifically involves first photolithography to define the region for selecting the transistor gate, and then etching away the first silicon nitride layer 502 and the etch stop layer 5011 in the opening region to prevent subsequent etching errors.

[0042] In step twelve, the third silicon oxide layer 1043 is located on the first silicon nitride layer 502 and the second silicon nitride layer 1042. The sidewall-type control gate polysilicon layer 1051 is located on the third silicon oxide layer 1043 and within a gap X in the third silicon oxide layer 1043. The two sidewall-type floating gate polysilicon layers 1081 are located outside the floating gate silicon oxide dielectric layer 1071 and correspond to the two sidewall-type control gate polysilicon layers 1051, respectively, so that the sidewall-type control gate polysilicon layer 1051 and the sidewall-type floating gate polysilicon layer 1081 form an overlapping region in the horizontal direction. The overlapping area is determined by the height of the sidewall-type control gate polysilicon layer 1051. Increasing the height of the sidewall-type control gate polysilicon layer 1051 will not increase the lateral size of the device, which is conducive to reducing the area.

[0043] The etch stop layer 5011 is located between the second silicon nitride layer 1042 and the first silicon nitride layer 502 . The etch stop layer 5011 serves as a stop layer when etching the first silicon nitride layer 502 .

[0044] The second LDD region 1091 and the source and drain regions 111 are both located on top of both sides of the P-type well 101 , which helps to reduce the channel leakage current effect between the source and drain.

[0045] The fourth spacer dielectric layer 1101 and the fifth spacer dielectric layer 1102 are sequentially located outside the spacer-type floating gate polysilicon layer 1081 , so that the N-type heavily doped region is far away from the channel.

[0046] The etching stop layer 5011 is made of silicon oxide to reduce costs.

[0047] from Figure 15 As can be seen, the upper curve shows the prior art relationship, while the lower curve shows the relationship of the present invention. By increasing the overlap area of ​​the CG and FG while maintaining the effective overlap area of ​​the WL and FG essentially unchanged, the sub-threshold slope is reduced by 50% without changing any injection conditions. Due to the significant increase in the coupling area of ​​the CG control gate, the leakage current is reduced by at least seven orders of magnitude, while the read current is increased by 52%, significantly expanding the read current window of the memory device.

[0048] In summary, the present invention changes the original CG and FG coupling from longitudinal to lateral coupling, that is, the sidewall control gate polysilicon layer and the sidewall floating gate polysilicon layer have an overlapping area horizontally (i.e., laterally). By increasing the height of the sidewall control gate polysilicon layer, the overlapping area of ​​CG and FG is increased, thereby improving the CG to FG coupling coefficient of the device. Since this is lateral coupling (the overlapping area is only related to the CG height), reducing the size of the device does not reduce the CG-FG coupling coefficient, which is beneficial to device miniaturization. The WL-FG overlapping area depends on the thickness of the WL-Poly. When the WL-Poly thickness is less than 500 Å and the CG-Poly height is greater than 1000 Å, the WL-FG coupling coefficient can be effectively reduced while increasing the CG-FG coupling coefficient, thereby enhancing the CG control capability, reducing device leakage, and improving the performance of the flash memory device. The sidewall control gate polysilicon layer and the sidewall floating gate polysilicon layer are both sidewall polysilicon, which can achieve self-aligned etching of the control gate and floating gate, which is beneficial to device size reduction.

[0049] The above specific implementation manner is a preferred embodiment of the present invention and does not limit the present invention. Any other changes or other equivalent replacement methods that do not deviate from the technical solution of the present invention are included in the protection scope of the present invention.

Claims

1. A floating gate split-gate flash memory device, characterized in that: It includes a P-type well, a selection gate oxide layer, a selection gate polysilicon layer, a second silicon oxide layer, a second silicon nitride layer, a third silicon oxide layer, a sidewall type control gate polysilicon layer, an isolation dielectric layer, a floating gate silicon oxide dielectric layer, a sidewall type floating gate polysilicon layer, a second LDD region, a source and drain region, a fourth sidewall dielectric layer and a fifth sidewall dielectric layer. The select gate oxide layer, the select gate polysilicon layer, the second silicon oxide layer, the second silicon nitride layer, and the third silicon oxide layer are sequentially located on top of the P-type well; the two sidewall control gate polysilicon layers and the isolation dielectric layer are both located in a gap in the third silicon oxide layer; the floating gate silicon oxide dielectric layer is located outside the third silicon oxide layer and outside the isolation dielectric layer; the two sidewall floating gate polysilicon layers are located outside the floating gate silicon oxide dielectric layer and correspond to the two sidewall control gate polysilicon layers, respectively; the sidewall control gate polysilicon layer and the sidewall floating gate polysilicon layer have an overlapping area in the lateral direction; the second LDD region and the source and drain regions are both located on top of both sides of the P-type well; the fourth sidewall dielectric layer and the fifth sidewall dielectric layer are sequentially located outside the sidewall floating gate polysilicon layer.

2. A method for manufacturing a floating gate split-gate flash memory device, characterized in that: It includes the following steps: Step 11: implanting a P-type well on the P-type substrate, sequentially forming a select gate oxide layer, a select gate polysilicon layer, a second silicon oxide layer in the inter-polysilicon ONO layer, and a second silicon nitride layer on the P-type well, wherein the inter-polysilicon ONO layer includes a second silicon oxide layer, a second silicon nitride layer, and a third silicon oxide layer; then depositing an etch stop layer and a first silicon nitride layer; photolithographically defining an area for the select transistor gate, and etching the first silicon nitride layer and the etch stop layer to form an opening; Step 12: depositing a third silicon oxide layer and a control gate polysilicon layer in sequence, and performing anisotropic etching to form a sidewall control gate polysilicon layer; the sidewall control gate polysilicon layer is located within the opening; and the sidewall control gate polysilicon layer and the sidewall floating gate polysilicon layer have an overlapping area in the lateral direction; Step 13: depositing an isolation dielectric layer between the two sidewall-type control gate polysilicon layers, and performing chemical mechanical polishing using the first silicon nitride layer as a CMP stop layer; Step 14: using the third silicon oxide layer and the isolation dielectric layer as etching masks, wet-etching and removing the first silicon nitride layer; Using the third silicon oxide layer and the isolation dielectric layer as masks, the etch stop layer, the second silicon nitride layer, the second silicon oxide layer, and the select gate polysilicon layer are sequentially etched, thermal oxidation is performed on the side of the select gate polysilicon layer to form a thermal oxide layer, and then the select gate oxide layer is etched; Step 15: depositing a floating gate silicon oxide dielectric layer, then depositing a floating gate polysilicon layer, then etching the floating gate polysilicon layer to form a sidewall floating gate polysilicon layer, selectively etching the floating gate in the width direction of the device to form isolated floating gate polysilicon blocks, oxidizing the floating gate sidewalls to form a fourth silicon oxide layer, and performing LDD implantation to form a second LDD region; Step 16: depositing and etching to form a fourth sidewall dielectric layer and a fifth sidewall dielectric layer, and performing source and drain heavy doping implantation to form source and drain regions.

3. The method for manufacturing a floating gate split-gate flash memory device according to claim 2, wherein: The step eleven specifically comprises first photolithographically defining the region of the selection transistor gate, and then etching away the first silicon nitride layer and the etch stop layer in the opening region.

4. The method for manufacturing a floating gate split-gate flash memory device according to claim 2, wherein: The third silicon oxide layer in step 12 is located on the first silicon nitride layer and the second silicon nitride layer, the sidewall-type control gate polysilicon layer is located on the third silicon oxide layer and in a gap in the third silicon oxide layer, and the two sidewall-type floating gate polysilicon layers are located outside the floating gate silicon oxide dielectric layer and correspond to the two sidewall-type control gate polysilicon layers respectively.

5. The method for manufacturing a floating gate split-gate flash memory device according to claim 2, wherein: The etch stop layer is located between the second silicon nitride layer and the first silicon nitride layer.

6. The method for manufacturing a floating gate split-gate flash memory device according to claim 2, wherein: The second LDD region and the source and drain regions are both located on top of both sides of the P-type well.

7. The method for manufacturing a floating gate split-gate flash memory device according to claim 2, wherein: The fourth sidewall dielectric layer and the fifth sidewall dielectric layer are sequentially located on the outer sides of the sidewall type floating gate polysilicon layer.

8. The method for manufacturing a floating gate split-gate flash memory device according to claim 2, wherein: The etching stop layer is made of silicon oxide.

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